954
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 6, DECEMBER 1987
`
`A Pipelined 5-Msample/s 9-bit
`Analog-to-Digital Converter
`
`STEPHEN H. LEWIS anp PAUL R. GRAY,FELLOW, IEEE
`
`Abstract —A pipelined, 5-Msample/s, 9-bit analog-to-digital (A/D) con-
`verter with digital correction has been designed and fabricated in 3-~m
`CMOStechnology. It requires 8500 mil”, consumes 180 mW,and has an
`input capacitance of 3 pF. A fully differential architecture is used; only a
`two-phase nonoverlapping clockis required, and an on-chip sample-and-hold
`(S/H) amplifier is included.
`
`I.
`
`INTRODUCTION
`
`RADITIONALdesigns of high-speed CMOSanalog-
`to-digital (A/D) converters have used parallel (flash)
`architectures [1]-[13]. While flash architectures usually
`yield the highest
`throughput rate,
`they tend to require
`large silicon areas because of
`the many comparators
`required. An important objective is the realization of
`high-speed A/D converters in much less area than that
`required by flash converters so that the A/D interface
`function can be integrated on the same chip with associ-
`ated complex, high-speed,
`image-processing functions.
`Multistage conversion architectures reduce the required
`area by reducing the total number of comparators [14]-[19].
`Using a pipelined mode of operation in these architectures
`allows the stages to operate concurrently and makes the
`maximum throughputrate almost independentof the num-
`ber of stages. Also, digital correction techniques signifi-
`cantly reduce the sensitivity of the architecture to certain
`component nonidealities. Pipelined configurations have
`been previously applied in high-performance board-level
`converters, but they have not been applied to monolithic
`CMOS A/Dconverters because of the difficulty of realiz-
`ing high-speed interstage sample-and-hold (S/H) gain
`functions in CMOStechnologies. In this paper, an experi-
`mental four-stage pipelined A/D converter with digital
`correction that has 9-bit resolution and 5-Msample/s con-
`version rate in a 3-4m CMOStechnology is described.
`The experimental converter uses high-speed differential
`switched-capacitorcircuitry to carry out the interstage gain
`functions.
`In
`This paper is divided into four additional parts.
`Section I], pipelined A/D architectures are described con-
`
`Manuscript received May 8, 1987; revised July 24, 1987. This work was
`supported by DARPA under Contract N00039-C-0107 and by the Na-
`tional Science Foundation under Contract DCI-8603430.
`The authors are with the Electronics Research Laboratory, University
`of California, Berkeley, CA 94720.
`IEEE Log Number 8716973.
`
`ceptually, and their advantages over flash and two-step
`subranging architectures [17] are explained. In Section JIT,
`the error sources present in pipelined A/D converters are
`identified,
`and the way in which digital correction
`eliminates the effects of some of these errors is shown. In
`Section IV, the circuits in an experimental prototype are
`described. Finally, experimental results from the prototype
`converters are given in Section V.
`
`II. CONCEPTUAL DESCRIPTION
`
`A block diagram of a general pipelined A/D converter
`with k stages is shown in Fig. 1. Each stage contains an
`S/H circuit, a low-resolution A/D subconverter, a low-
`resolution digital-to-analog (D/A) converter, and a dif-
`ferencing fixed-gain amplifier.
`In operation, each stage
`initially samples and holds the output from the previous
`stage. Each stage then does a low-resolution A/D conver-
`sion on the held input, and the code just produced is
`converted back into an analog signal by a D/A converter.
`Finally, the D/A converter output is subtracted from the
`held input, producing a residue that is amplified and sent
`to the next stage.
`The primary potential advantages of the pipelined archi-
`tecture are high throughput rate and low hardwarecost.
`The high throughput rate of the pipelined architecture
`stems from concurrent operation of the stages. At any
`time, the first stage operates on the most recent sample,
`while the next stage operates on the residue from the
`previous sample, and so forth. If the A/D subconversions
`are done with flash converters, a pipelined architecture
`only needs two clock phases per conversion. Flash archi-
`tectures also require two clock phases per conversion, one
`each for sampling and A/D conversion, and use pipelining
`to do the digital decoding operation. The throughput rate
`of flash converters is maximized because their pipelined
`information is entirely digital and can be transferred to
`1-bit accuracy in less time than it takes to generate and
`transfer the analog residue in a pipelined multistage archi-
`tecture. The area and consequent manufacturing cost of
`pipelined converters is small compared to those of flash
`converters, however, because pipelined converters require
`fewer comparators than flash converters. For example, the
`9-bit prototype pipelined converter described in Section IV
`
`0018-9200/87/1200-0954$01.00 ©1987 IEEE
`
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`offset and gain errors.
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`LEWIS AND GRAY: PIPELINED 5-MSAMPLE/S 9-BIT ANALOG-TO-DIGITAL CONVERTER
`
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`Fig. 1. Block diagram ofa general pipelined A/D converter.
`
`uses 28 comparators and, requires.a core area of 8500
`mil? in a 3-4m CMOStechnology. A 9-bit flash converter
`~ would use 512 comparators and would be more than ten
`times larger than the pipelined prototype in the same
`technology. Not only is the area small for pipelined con-
`verters, but also it
`is linearly related to the resolution
`because if the necessary accuracy can be achieved through
`calibration or trimming, the resolution can be increased by
`adding stages to the end of the pipeline without increasing
`the numberof clock phases required per conversion. In
`contrast, flash and subranging architectures need exponen-
`tial, rather than linear, increases in area to increase their
`resolution and also require trimming or calibration for
`greater than 8- or 9-bit linearity.
`Other advantages of
`the pipelined architecture stem
`from the use of S/H amplifiers to isolate the stages. First,
`because an S/H amplifier can also be used on the input of
`the A/D converter, pipelined architectures can accurately
`sample high-frequency input signals. Second,the interstage
`gains from these amplifiers diminish the effects of non-
`idealities in all stages after the first stage on the linéarity of
`the entire conversion; furthermore,
`this allows the con-
`verter to use a digital correction technique in which non-
`linearity in the A/D subconversionshaslittle effect on the
`overall linearity. This subject is presented in Section III.
`The main disadvantage of pipelined A/D converters is
`that
`they require the use of operational amplifiers (op
`amps) to realize parasitic-insensitive S/H amplifiers. Al-
`though the S/H amplifiers improve many aspects of the
`converter performance,
`the op amps within the S/H
`amplifiers limit the speed of the pipelined converters. In
`contrast, op ampsaré not required in subranging architec-
`tures. Because high-speed op ampsaredifficult ‘to realize, a
`commongoalin the designof subranging A/D converters
`is to avoid using op amps. If op amps are not used,
`however,
`it
`is impossible to realize parasitic-insensitive
`S/H amplifiers. The consequent high-frequency input
`sampling is poor, stage operation is sequential, and toler-
`ance to error sources in stages after the first is unimproved
`from that of the first stage. Also, flash converters usually
`do not use an input S/H amplifier because of the diffi-
`culty in realizing an op amp in CMOStechnologies thatis
`fast enough to drive the inherently large input load. There-
`fore, flash converters often suffer reduced performance at
`high input signal frequencies.
`
`II]. Error SOURCES
`
`The primary error sources present in a pipelined A/D
`converter are offset errors in the 8/H circuits and ampli-
`fiers, gain errors in the S/H circuits and amplifiers, A/D
`subconverter nonlinearity, D/A subconverter nonlinearity,
`and op-amp settling-time errors. With digital correction, as
`shown below,the effects of offset, gain, and A/D subcon-
`verter nonlinearity are reduced or eliminated;
`therefore,
`the D/A converter. nonlinearity and op-ampsettling-time
`errors limit the performance of pipelined A/D converters.
`To begin the error analysis, the effects of offset and gain
`errors are considered next.
`A block diagram of a two-stage pipelined A/D con-
`verter with offset and gain errors in each of the S/H
`circuits and the interstage amplifier is shown as a repre-
`sentative example in Fig. 2. The nonideal S/H circuits and
`interstage amplifier are replaced by ideal eléments in series
`with gain and offset errors, and each of these replacements
`is surrounded by a dotted line. The gain error in the
`first-stage S/H circuit changes the conversion range of the
`A/D converter and does not affect
`linearity. The gain
`errors in the interstage amplifier and second-stage S/H
`circuit can be combined into one equivalent error that does
`affect linearity. However, because the interstage gain only
`has to be accurate enough to preserve the linearity of the
`stages after the first stage, the effect of this gain error on
`linearity is small. For example, if both stages in Fig, 2 have
`4-bit resolution, and if the only error is in the gain of the
`interstage amplifier, the interstage amplifier gain should be
`equal to 16 and must be accurate to within +3 percent.
`The offset error in the first-stage S/H circuit causes an
`input-referred offset but does not affect linearity. The
`offset errors in the interstage amplifier and second-stage
`S/H circuit can be combined into one equivalent offset
`that does not affect linearity if digital correction is used.
`Because addition is commutative, the equivalent offset can
`be pushedto theleft of the first-stage subtractor. To move
`the equivalent offset to the input branch, where is causes
`an input-referred offset; an equal but opposite offset must
`be inserted in the first-stage A/D subconverter branch. As
`shown below,the effect of the offset in the first-stage A/D
`subconverter is eliminated by the digital correction.
`Next, the effect of nonlinearity in the first-stage A/D
`subconversion is considered. A block diagram of one stage
`in a pipelined A/D converter is shown in Fig. 3(a). A 2-bit
`stage is used as a representative example. Nonlinearity in
`
`

`

`956
`
`IEEE JOURNALOF SOLID-STATE CIRCUITS, VOL. SC-22, NO, 6, DECEMBER 1987
`
`0.5
`IN
`
`
`——| Stage 1 >— Stage 2
`n2bit
`
`
`
`
`
`
`tg|Correction
`
`
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`Logic
`nt bit
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`reg|———+|_ reg
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`ni+n2-1
`Outputs
`
`Residue
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`
`
`Fig. 4. Block diagram of a two-stage pipelined A/D converter with
`digital correction.
`
`Residue
`
`
`
`
`
`
`
`(b)
`
`Residue
`
`nn
`1/2 LSB
`cause the D/A converter is assumed to be ideal,
`these
`Conv. Range
`0
`increased residues are accurate for the codes to which they
`Vin|of Next Stage
`W/Z LSB
`PK nn nnn Benne nnn nn
`correspond; therefore, at this point, no information is lost.
`If the interstage gain is still 4, however, information 1s lost
`when the larger residues saturate the next stage and pro-
`duce missing codes in the conversion. Therefore, if the
`conversion range of the second stage is increased to handle
`the larger residues,
`they can be encoded and the errors
`corrected. This process is called digital correction [20], [21]
`and is described next.
`A block diagram of a two-stage pipelined A/D con-
`verter with digital correction is shown in Fig. 4. The new
`elements in this diagram are the pipelined latches,
`the
`digital correction logic circuit, and the amplifier with a
`gain of 0.5. The amplifier with a gain of 0.5 is conceptual
`only and is drawn to show that
`the interstage gain is
`reduced by a factor of 2 so that nonlinearity error in an
`amount between +1/2 LSB at a nl-bit level in the first-
`stage A/D subconversion does not produce residues that
`saturate the second stage. If the first stage is perfectly
`linear, only half the conversion range of the secondstage is
`used. Therefore, 1 bit from the second stage is saved to
`digitally correct the outputs from the first stage; the other
`n2-1 bits from the second stage are added to the overall
`resolution. After the pipelined latches align the outputs in
`time so that
`they correspond to one input,
`the digital
`correction block detects overrange in the outputs of the
`second stage and changes the output of thefirst stage by 1
`LSB at a nl-bit level if overrange occurs. Digital correc-
`tion improves linearity by allowing the converter to post-
`pone decisions on inputs that are near the first-stage A/D
`subconverter decision levels until the residues from these
`inputs are amplified’ to the point where similar nonlinear-
`ity in later-stage A/D subconverters is insignificant.
`To do the digital correction, a correction logic circuit is
`required. Also,if flash converters are used in the stages,all
`stages after the first require twice as many comparators as
`without digital correction. The logic is simple, however,
`and none the comparators needs to be offset canceled.
`_
`It is shown above that with digital correction, nonlinear-
`ity in the A/D subconverters can be corrected if the D/A
`converter is ideal. Therefore,
`the D/A coriverter in the
`first stage determines the linearity of the entire A/D
`converter. Such D/A converters can be realized with resis-
`tor strings for linearities in the 89-bit range. For integral
`linearity greater than 9 bits,
`the design of such.a D/A
`converter is not trivial and either requires calibration or
`
`1 LSB
`12 ISB -
`1/2 LSB
`-1LSB)
`
`/ Conv. Range
`Vin ofNext Stage
`
`/¢
`
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`
`
`
`Positive Decision
`Negative Decision
`Level Error Level Error
`
`(c)
`
`(a) Block diagram of one 2-bit stage in a pipelined A/D
`Fig. 3.
`converter. (b) Ideal residue versus input. (c) Residue versus input with
`A/D subconverter nonlinearity.
`
`the A/D subconverter is modeled .as an input-referred
`linearity error. The effect of this nonlinearity is studied by
`examining plots of the residue versus the input. Two such
`plots are shown in Fig. 3(b)-and(c).
`In Fig. 3(b), both the A/D subconverter and the D/A
`converter are assumedto be ideal. The plot has a sawtooth
`shape because when the input is between the decision
`levels determined by the A/D subconverter,
`the A/D
`subconverter and D/A converter outputs are constant;
`therefore, the residue rises with the input. When the input
`crosses a decision level, the A/D subconverter and D/A
`converter outputs increase by one least significant bit
`(LSB) at a 2-bit level, so the residue decreases by 1 LSB.
`Here, the residue is always between +1/2 LSB and con-
`sists only of the part of the input that is not quantized by
`the first stage. With the interstage gain equal to 4,
`the
`maximum residue is amplified into a full-scale input to the
`next stage;
`therefore,
`the conversion range of the next
`stage is equal
`to the maximum residue out of the first
`stage.
`A similar curve is shown in Fig. 3(c) for a case when the
`A/D subconverter has some nonlinearity, but the D/A
`’ converter is still ideal. In this example, two of the A/D
`subconverter decision levels are shifted, one by —1/2 LSB
`and the other by +1/2 LSB. When the input crosses a
`shifted decision level, the residue decreases by 1 LSB. If
`the decision levels are shifted by less than 1/2 LSB, the
`residue is. always between +1.LSB. Here,
`the residue
`consists of both the unquantized part of the input and the
`error caused by the A/D subconverter nonlinearity. Be-
`
`

`

`LEWIS AND GRAY: PIPELINED 5-MSAMPLE/S 9-BIT ANALOG-TO-DIGITAL CONVERTER
`
`957
`
`trimming. Also, fast settling op amps. are required to do
`analog subtraction and amplification at the sampling rate
`of the A/D converter. The 3-um CMOSprototype de-
`scribed in Section IV is able to do these functions at 5
`Msample/s. The maximum speed. of such processing in-
`creases in scaled technologies, and video conversion rates
`should be achievable in 1.5-2-~m CMOStechnologies.
`
`IV. PRororyPe
`
`Several important design considerations for the proto-
`type converter are now presented. To minimize design
`time, assume that all stages are identical. Fast op amps
`and flash subconverters are used to operate at as high a
`speed as possible. The most basic architectural decision is
`to choose the resolution per stage; for efficient use of the
`conversion range of each stage, this choice determines the
`corresponding value of interstage gain. To attain maxi-
`mum throughput rate, the resolution per stage should be
`small so that the interstage gain is small and the corre-
`sponding closed-loop bandwidth of the gain blockis large.
`Conversely, large ‘resolution and corresponding gain per
`stage are desirable to achieve high linearity because the
`contributions of nonidealities in all stages after the first
`are reduced by the combinedinterstage gain preceding the
`nonideality. Thus the speed and linearity requirements
`conflict in determining the optimum resolution per stage.
`It also can be shown under certain simplifying assump-
`tions that to minimize the amount of. required hardware,
`the optimum resolution per stage is about 3 or 4 bits per
`stage, which is about midway between the high and low
`end. This compromise in the resolution per stage keeps
`both the number of op amps and the number of compara-
`tors small. Finally, because the goal of this project wasto
`realize an A/D converter small enough that it could be
`incorporated within a primarily digital chip,
`the A/D
`converter must be able to operate in the presence of large
`power supply noise caused by the digital circtiits. To
`reduce the sensitivity of the converter to this ribise, all
`analog signal paths in the prototype are fully differential.
`To meet these requirements,
`the prototype is divided
`into four stages with 3 bits produced per stage. A block
`diagram of one stage is shown in Fig. 5. The A/D subcon-
`versions are done with flash converters, so each stage
`needs seven comparators. The S/H amplifier block re-
`places both the S/H circuit and interstage amplifiershown
`in earlier figures. Because theinterstage gain is.4 iristead of
`8, half the range and one bit from each of the last three
`stages are saved to digitally correct the outputs of the
`previous stages. Thus, instead of obtaining 3 bits of resolu-
`tion from each of these stages, only 2 bits of resolution are
`obtained from each. The digital correction is done off the
`chip. In total, 9. bits of resolution are produced, using 28
`comparator and four op amps.
`The S/H amplifier block is expandediin Fig. 6(a). Fig.
`6(b) shows that the clock is divided into two nonoverlap-
`ping phases. On clock phase $,, the input is sampled onto
`
`
`
`Fig. 5. Block diagram of one stage in the prototype.
`
`
`
`
`
`Fig. 6.
`
`by
`(a) Schematic ‘of S/H amplifier. (b). Timing diagram of a two-
`phase nonoverlapping clock.
`
`the 4C, capacitors, and the integrating C, and common-
`mode feedback C.,, capacitors are resét. On $5, the left
`sides of the sampling capacitors are connected together so
`the difference between the two sampled inputs is amplified
`by the ratio of the sampling to integrating capacitors. To
`the extent that the op ampin aclosed--loop configuration
`drives its differential-‘input to zero, the gain is insénsitive
`to parasitic capacitances on either the top or bottom plates
`of any of these capacitors. Meanwhile, the common-mode
`feedback (CMFB)capacitors are connected to the outputs
`of the op ampto start the CMFBcircuit: Switched-capaci-
`tor CMFB is useful in pipelined A/D converters because
`pipelined converters inherently allow a clock phase needed
`to reset the capacitorbias.
`As a result of the use of digital correction, the offsets of
`all the op amps are simply referred to thé input of the
`A/D converter, each in an amount diminished by the
`combined interstage amplifier gain preceding the offset.
`Therefore, the op amps do not. have to be offset canceled
`and do not have to be placed in a unity-gain feedback
`configuration. Since the op amps do not have to be unity-
`gain stable, their speed can be optimizedfor a closed loop
`gain of 4. The op amp, shown in Fig. 7, uses a fully
`differential, class A/B configuration with dynamic bias.
`The class A/B structure gives both high slew rate and high
`gain after. slewing. According to simulation, the amplifier.
`dissipates 20 mW andsettles in 50 ns to an accuracy of 0.1
`percent with a 5-V differential step intoa4-pF load.
`
`

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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 6, DECEMBER 1987
`
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`Fig. 7. Op-amp schematic.
`
`The op amp is similar to one reported by Castello and
`Gray [22], and its operation is now described. Transistors
`M,-M, form the input stage and generate the class A/B
`action. Source followers M,-—M, are used to bias the input
`stage so that
`it conducts some current even for zero
`differential input. For an increase in the voltage on the
`positive input and a corresponding decrease on the nega-
`tive input, the gate-to-source voltages of both M, and M,
`increase while those of M, and M, decrease; therefore, the
`current in M, and M,increases and that in M, and M,
`decreases from their standby values. Transistors M, and
`M,,, M,) and M,,, M,, and M,,, and M,, and M,, form
`current mirrors that reflect and amplify current from the
`input branches to the output branches. Cascode transistors
`M,,-—M,, increase the gain of the op amp by increasing
`the output resistance of the output nodes to ground. A
`high-swing dynamic bias circuit composed of transistors
`M,,—M,, adjusts the gate bias on the cascode transistors
`so that the output branches can conduct large currents
`during slewing and have high swings during settling. Tran-
`sistors M,,—-M,,
`together with the C-,, capacitors and
`associated switches in Fig. 6(a), form the CMFB circuit.
`Because the gates of M,, and M,, are tied to a constant
`bias voltage, these transistors are constant-current sources.
`The gates of M,, and M,, are connected to the CMBIAS
`terminal shown in Fig. 6(a). This point is alternatively
`switched from a bias voltage on @,
`to a capacitively
`coupled version of the output on ¢,. During 5, the
`CMBIASpoint rises and falls with changes in the com-
`mon-modeoutput voltage. This change adjusts the current
`drawn through M,, and M,, so that the common-mode
`output voltage is held constant near 0 V. Note that if the
`two halves of
`the differential circuit match perfectly,
`
`changes in the differential output voltage do not change
`the CMBIASpoint.
`Because the speed of this op ampis limited by the speed
`of its current mirrors, wide-band current mirrors are used
`to increase the speed. To this end, transistors M,—M,, are
`not simply diode connected, but instead are buffered by
`source followers MB,—MB,. Because of this change, the
`currents needed to supply the parasitic capacitance be-
`tween the gates and sources of the current mirrors at high
`frequencies come from the power supplies instead of from
`the input branch. The drawback to this approach is that
`the drain-to-source voltages of transistors M,—M,, are
`increased by the gate-to-source voltages of
`transistors
`MB,-— MB,, respectively. Therefore, input stage transistors
`M,-M, operate with less drain-to-source voltage than if
`M,-—M,, were diode connected. As a result, 4f,—M, enter
`the triode region for smaller differential inputs than with
`diode-connected loads, and the amountof current that the
`input stage can produce while slewing is limited. Because a
`high-swing dynamic bias circuit
`is used,
`this is not a
`problem for +5-V operation; however, for +5-V oper-
`ation,
`these wide-band current mirrors probably would
`limit the slew rate of the op amp.
`A block diagram of an A/D, D/A subsection is shown
`in Fig. 8. To save area, one resistor string is shared for
`both the A/D and D/A functions. The resistor string
`divides the reference into equal segments and provides the
`boundaries between these segments as thresholds for a
`bank of comparators. The comparators are clocked at the
`end of $,. On ¢,, eight D/A converter outputs are en-
`abled and oneis selected based on control signals gener-
`ated from the comparator outputs (9,,---, ¥g). Although
`Fig. 8 shows a single-ended representation of both the
`
`

`

`LEWIS AND GRAY: PIPELINED 5-MSAMPLE/$ 9-BIT ANALOG-TO-DIGITAL CONVERTER
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`Fig. 8. Block diagram of A/D, D/A subsection.
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`Fig. 9. Connection of comparator with A/D, D/A subsection.
`
`Fig. 10. Comparator schematic.
`
`Conversion Rate = 5 Ms/s
`Input Frequency = 2 MHz
`
`|
`
`TAY
`
`A
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`i,
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`|
`CA
`LA RA AL
`
`0.75
`0.50
`
`0.25
`
`DNL
`(LSBs)°-OFh
`0.25
`
`0
`
`128
`
`256
`Code
`
`384
`
`512
`
`Fig. 11. DNL versus code.
`
`differential amplifier, and ML, and ML, formalatch. |
`
`A/D subconverter and D/A converter functions, on the
`
`prototype, both functions are fully differential. Therefore,
`Transistors MCS, and MCS, form a current switch that
`instead of just one D/A converter output, equal and,
`allows the bias current from MB, to flow through either
`opposite D/A converter outputs are used. Also, each
`the differential amplifier or the latch. With the latch signal
`comparator comparesa differential input to a differential
`low,
`the inputs are amplified. Because M, and M, are
`reference instead of a single-ended input to a single-ended
`biased in the triode region, the gain of the amplifier is only
`reference.
`about 20 dB. When the latch signal is raised,
`the bias
`The connection of a comparator within an A/D, D/A
`current is switched from the amplifier to the latch. During
`subsection is shown in Fig. 9. The points labeled VR +
`the transition, the parasitic capacitances on the inputs to
`and VR — are connected to taps on theresistor string that
`the latch hold the amplified input. Finally,
`the latch
`depend on which comparator in the. bank is under consid-
`switches, and the comparison is completed.
`eration. For example, for the top comparator, VR+ is
`connected to the most positive A/D subconverter tap, and
`VR — is connected to the most negative A/D subconverter
`tap. On clock $,, the comparator inputs are grounded, and
`the capacitors sample the differential reference. On @, the
`left sides of the capacitors are connected to the differential
`input.
`Ignoring parasitic capacitance,
`the input to the
`comparator is then the difference between the differential
`input and the differential reference. The parasitic capaci-
`tances on the inputs to the comparator attenuate the input
`slightly, but the decision is not affected if the comparator
`‘has enough gain. As mentioned in Section III, because of ©
`digital correction, no offset cancellation on the comparator
`is required. Therefore, the comparator is never placed in a
`feedback loop and does not have to be stable in a closed-
`loop configuration.
`The comparator, shown in Fig. 10, uses a conventional
`latched-differential-amplifier configuration. Transistors M,
`and M, are source followers. Transistors M,—M, form a
`
`V. EXPERIMENTAL RESULTS
`
`the digital correction is
`As mentioned in Section IV,
`done off chip. This allows tests to be run to evaluate the
`need for the correction. Unless stated otherwise, all results
`are obtained using the full correction;
`that
`is, digital
`correction is applied to the first three stages. The proto-
`type has been tested primarily in two ways [23], [24]: first
`with a code density test, and second with a signal-to-noise
`ratio (SNR) test. Both tests have used high- and low-
`frequency input signals. Results of the code density test
`are shown in Figs. 11 and 12.
`In Fig. 11, differential nonlinearity (DNL) is plotted on
`the y axis versus code on the x axis for all 512 codes. The
`conversion rate is 5 Msample/s, and the input frequencyis
`2 MHz. Because the DNL never goes down to —1 LSB,-
`
`

`

`960
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 6, DECEMBER 1987
`
`Conversion Rate = 5 Ms/s
`
`1.25,
`
`TABLE I
`DATA SUMMARY OVER INPUT FREQUENCY VARIATION
`9-bit Resolution; 5-Msample/s Conversion
`Rate; +5-V Power Supplies
`
`
`Input Frequency
`2kHz
`2MHz
`45.002 MHz
`Peak DNL (LSB)
`0.5
`0.6
`0.5
`Peak INL (LSB)
`1.0
`LL
`1.2
`
`Peak SNR (dB)
`50
`50
`- 49
`
`Input Frequency = 2 MHz ma)
`
`
`
`128° 256°384°512
`Code
`frequencies: 2 kHz, 22 kHz, 202 kHz, 2.002 MHz, and
`5.002 MHz. The curve for 5.002 MHz represents a beat
`frequency test on the converter when compared to the
`curve for 2 kHz because the converter is running at the
`difference between these two frequencies or 5 Msample/s.
`An ideal 9-bit curve is also shown. The peak SNR is
`around 50 dB instead of 56 dB, as would be expected with
`a 9-bit converter; this difference is accounted for by distor-
`tion generated from the INL for large input signals. When
`the input signal is reduced in amplitude, the distortion is
`reduced and the real curves approach the ideal 9-bit curve.
`Note that there is little difference in the curves for differ-
`ent input frequencies, showing that
`the first-stage S/H
`amplifier is able to accurately sample high-frequency input
`signals.
`The results of the code density and SNR tests for
`variations in the input frequency are summarized in Table
`I. Peak DNL, INL, and SNR are shown for three input
`frequencies, and the performance is almost constant. This
`is important because it shows that
`the first-stage S/H
`amplifier is able to accurately sample high-frequency input
`signals.
`A photograph of the core of a prototype chip is shown
`in Fig. 14. The core is about 50 mil high by 150 mil wide.
`The stages follow one after another and are identical
`except that the fourth stage does not have a D/A con-
`verter or a subtractor and the two-phase nonoverlapping
`clock alternates from stage to stage. A test op amp and a
`test comparator are at the end. The prototype was made
`by MOSIS in a 3-ym, double-polysilicon, p-well, CMOS
`process.
`
`Fig. 12.
`
`INL versus code.
`
`56
`
`Conversion Rate = 5 Ms/s
`
`
`“42
`-36
`-30
`-24
`-18 -12
`-6
`0
`Input Level (dB)
`Fig. 13. SNR versus inputlevel.
`
`there are no missing codes. The maximum DNLisless
`than 0.6 LSB.
`In Fig, 12, integral nonlinearity (INL) is plotted on the
`y axis versus code on the x axis. Again, the conversion rate
`is 5 Msample/s and the input frequency is 2 MHz. The
`maximum INLis 1.1 LSB. The nonideality in the curve is
`caused by both nonlinearity in the first-stage D/A con-
`verter and incomplete settling of the first-stage op-amp
`output.
`Under the same conditions as in Figs. 11 and 12 but
`with the digital correction completely disabled,
`the maxi-
`mum DNL and INL are about 10 LSB at a 9-bit level,
`owing to comparator offsets. If the correction is applied
`only on the first stage, the maximum DNL and INL drop
`to about 3. LSB. When digital correction is applied on the
`first two stages, the maximum DNLis about 0.9 LSB and
`the maximum INL is about 1.5 LSB; therefore, there are
`no missing codes in this case. Also, the uncorrected histo-
`gram data from the code density test show that there are
`no codes for which any residue is greater than the refer-
`ence level for comparator C, or less than the reference
`level for comparator C, as labeled in Fig. 8. This means
`that the maximum absolute value of nonlinearity in an
`A/D subconversion is less than or equal to 1/4 LSB at a
`3-bit level, and the full digital correction range (41/2
`LSB) is not used. Therefore, comparators C, and: C, are
`not neededin the last three stages.
`SNR measurements were made by taking fast Fourier
`transforms on 1024 samples from the A/D converter at
`the downsampled rate of 20 kHz while the converter was
`running at 5 Msample/s. In Fig. 13, SNRis plotted on the
`y axis versus input
`level on the x axis for five imput
`
`VI.
`
`SUMMARY
`
`This paper reports on a prototype pipelined A/D con-
`verter with typical characteristics summarized in Table ITI.
`In summary,
`the prototype demonstrates that pipelined
`architectures and digital correction techniques are of
`potential interest for high-speed CMOS A/D conversion
`applications.
`
`ACKNOWLEDGMENT
`
`The authors gratefully acknowledge the help of R.
`Kavaler and J. Doernberg with the testing of the prototype
`converters.
`
`

`

`961
`
`LEWIS AND GRAY: PIPELINED 5-MSAMPLE/S 9-BIT ANALOG-TO-DIGITAL CONVERTER
`
`
`
`
`
`Fig. 14.
`
`Photograph of the core of the prototype.
`
`Y. Akazawa et al, “A 400MSPS 8b flash AD conversion LSI,”