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`
`IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 54, NO. 4, AUGUST 2005
`
`A State of the Art on ADC Error
`Compensation Methods
`
`Eulalia Balestrieri, Pasquale Daponte, Senior Member, IEEE, and Sergio Rapuano, Member, IEEE
`
`Abstract—Analog-to-digital converters (ADCs) are critical com-
`ponents of signal-processing systems. ADC errors can compromise
`the overall accuracy and the effectiveness of the whole system. This
`leads researchers to direct increasing attention to error correction
`topics. In this paper, some ADC error compensation methods are
`briefly introduced according to a classification criterion based on
`the main research trends.
`
`Index Terms—Analog-to-digital converter (ADC), dithering,
`error compensation, lookup table, modeling.
`
`I. INTRODUCTION
`
`O NE OF THE key components in modern signal-pro-
`
`cessing systems is the analog-to-digital converter (ADC),
`which interfaces the analog physical world with digital sys-
`tems. Digital signal-processing systems are usually designed
`by considering ADCs as ideal components affected only by
`sampling and quantization errors. However, unfortunately, the
`effects of ADC actual errors strongly affect the overall accuracy
`and can compromise the effectiveness of the system as a whole.
`Consequently, the problem of metrological characterization
`of the ADC error sources assumes particular relevance for
`manufacturers as well as for system integrators and for end
`users. The role of modeling techniques is also important in
`order to predict the actual behavior of the ADCs and to define
`a suitable correction of the converter nonidealities.
`This paper is part of a research project oriented to provide a
`comprehensive overview on ADC topics. Previous works pro-
`vided the state of the art and the leading trends of the research
`in the fields of ADC standardization, testing, and modeling [1],
`[2], [3].
`This paper is aimed at providing a state of the art and the
`leading trends of the research in the field of ADC error correc-
`tion. In that direction, several methods have been proposed over
`the years. This paper analyzes these methods by referring to the
`following:
`1) lookup-table-based methods;
`2) dithering-based methods;
`3) methods based on a model inversion;
`4) architecture-based methods.
`
`II. LOOKUP-TABLE-BASED METHODS
`
`Lookup-table-based methods produce a corrected ADC
`output by using an array called a lookup table (LUT) where
`
`Manuscript received June 15, 2004; revised April 15, 2005.
`The authors are with the Department of Engineering, Università
`del Sannio, 82100 Benevento,
`Italy (e-mail: balestrieri@unisannio.it;
`daponte@unisannio.it; rapuano@unisannio.it).
`Digital Object Identifier 10.1109/TIM.2005.851083
`
`Fig. 1. Two-dimensional state–space correction table [6], [7].
`
`Fig. 2. Outline of the dynamic post-correction system with error table
`reduction [8].
`
`Fig. 3. Two-dimensional phase-plane correction table [9].
`
`precalculated values are stored. The static LUT correction
`scheme maps every possible output state into a corrected state
`by addressing an
`-size table, for
`quantization regions [4].
`An alternative approach consists in storing in the table only the
`correction terms that should be added to the output [4], [5].
`In the state-space correction, the LUT is extended to two di-
`mensions. The current sample and the previous sample are used
`to address the table (Fig. 1) [6], [7]. The method proposed in [8]
`is a generalization of the LUT correction methods listed above.
`is used together with
`In particular, the present sample
`delayed samples to address a (
`1)-dimensional table. With
`more table dimensions, a better estimate of the error can be pro-
`duced. The address space considerably grows with
`. The so-
`lution proposed in [8] uses only a subset of the
`available bits
`in each sample (Fig. 2).
`In the phase-plane approach (Fig. 3), described in [9], the cor-
`rection is based on a two-dimensional correction table that is
`
`0018-9456/$20.00 © 2005 IEEE
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`BALESTRIERI et al.: A STATE OF THE ART ON ADC ERROR COMPENSATION METHODS
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`
`addressed with the present sample and the slope of the input
`signal that can be either measured with extra hardware [10] or
`estimated from the output of a digital filter [11]. Addressing the
`table with higher order derivatives has been reported in [12].
`This improves the accuracy in slope estimation but does not
`greatly improve the spurious-free dynamic range (SFDR). The
`size of the table is still too large to be used for high speed ADCs.
`In [13], the required memory size is reduced by approximating
`the table values with triangular basis functions, while in [14],
`a neural network is used to achieve that result. A model-based
`method for correcting dynamic errors in a digitizer is proposed
`in [15]. In this paper, the previous work on phase-plane com-
`pensation [16] is extended to include the correction of the error
`in the fundamental component, not included in the phase-plane
`compensation methods.
`In [17], error compensation is based on a general model for
`error mechanisms that uses the present ADC output code, the
`slope of the input signal, and the previous output code. This
`provides an effective way of dealing with multiple error mecha-
`nisms simultaneously. However, the method is computationally
`expensive.
`A method based on sine wave histograms for dynamic error
`estimation necessary to adequately fill the LUT is used in [18].
`Two histograms are used: one for negative slopes and one for
`positive slopes. In this approach, the amplitude distribution of
`the input signal must be known. A different method for es-
`timating matching errors in subranging ADCs is presented in
`[19]. The information used by the method to calculate the LUT
`is a histogram of the ADC output. It does not require any knowl-
`edge of the input signal, except that its amplitude distribution
`should be smooth. The online correction of static nonlineari-
`ties in a Nyquist-rate ADC proposed in [20] also uses output
`code-density histograms. The estimation of integral nonlinearity
`(INL) is made at each output level, followed by the creation of
`a corresponding entry in the LUT for error correction.
`An extension of static LUT-based methods, due to the fre-
`quency-dependent nature of ADC errors, is presented in [21].
`The one-dimensional correction table of static compensation
`is extended to a two-dimensional table, using both the present
`ADC output and the present frequency region estimate to obtain
`the error value. In practice, a specific one-dimensional correc-
`tion table is selected for each frequency estimate.
`In order to obtain a good representation of the system nonlin-
`earities, the error table must be generated with calibration sig-
`nals that adequately stimulate the ADC. For practical reasons,
`only a limited number of calibration signals are used for gener-
`ating error tables. In [22], the error tables are generated using
`a single frequency sinusoidal input with increasing amplitude,
`while in [6], signals including three sine waves with different
`frequencies and increasing amplitudes are used. However, both
`types of calibration signal are not capable of completely filling
`the error table. In [7], it is shown that the use of pseudorandom
`calibration signals gives better error table coverage resulting in
`better ADC error compensation.
`Latest developments for phase-plane correction were related
`to the introduction of a dual-tone calibration signal for its in-
`trinsic capability of extensively mapping the phase-plane. In
`[23], the two-tone signal is obtained by adding two sine waves
`
`Fig. 4. Coverage of (a) the two-dimensional histogram and (b) the standard
`one with the same sample number for an elementary subdomain of the
`phase-plane [24].
`
`with the same amplitude and approximately the same frequency,
`but there is no accuracy specification for the frequency value.
`A bidimensional histogram based on the dual-tone signal of
`[23] is proposed in [24] for testing ADC in the phase-plane. A
`unique histogram procedure, based on a unique test signal ad-
`equately covering the phase plane, is exploited. The resulting
`two-dimensional histogram of the actual code occurrences in
`the phase plane is compared with the ideal dual-tone probability
`distribution function in order to derive the actual transfer charac-
`teristic. The use of a dual-tone test signal allows coverage of the
`phase plane intrinsically higher than the standard histogram via
`several test sine waves with the same sample number [24]. The
`proposed two-dimensional histogram spreads the samples better
`than the standard one (Fig. 4). Results of experimental tests
`show the method effectiveness in correcting the phase-plane
`error of some actual ADCs.
`Concerning the calibration problem, in [25], a comprehen-
`sive analytical approach to the use of dual-tone, as a calibra-
`tion signal, is proposed. Moreover, a figure of merit assessing
`the quality of the phase-plane coverage is introduced and evalu-
`ated. An operating guide for selecting optimal input frequencies
`of the dual-tone test signal in phase-plane metrological charac-
`terization of ADCs is given too.
`Results of ADC error compensation implemented on a VLSI
`chip are shown in [26], which gives details about an error
`table compensator system that uses a VLSI chip including the
`following:
`1) a transversal filter programmed as a wide-band differen-
`tiator;
`2) some additional on chip circuits;
`3) an LUT stored in an external memory.
`
`III. DITHERING-BASED METHODS
`
`Dithering is a method for randomizing the ADC quantization
`errors by adding a stimulus uncorrelated to the desired signal at
`the ADC input. Two basic topologies are mainly used: nonsub-
`tractive and subtractive [27]. In the former case the dither is only
`added to the input signal and then removed by low-pass filtering
`the output signal. In the latter case the dither is also subtracted
`from the quantizer output to yield the system output. Several pa-
`pers have been published on the performance of different dither
`signals [28]–[30] and on different dither topologies [28], [31].
`The idea of dithering is suitable for measurement systems
`based on PC plug-in cards [32]. In [33], it is shown how
`dithering can be implemented to correct the output of an ADC
`included in a single chip microcontroller.
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`

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`
`Fig. 5. Additive FS dither hardware block diagram [35].
`
`Dithering cannot adequately compensate some ADC errors,
`like, for example, nonlocal errors of integral linearity. This
`means that analog-to-digital (A/D) conversion error remains
`relevant for some values of the input signal. Therefore, it is
`necessary to separate the errors produced at different scales of
`the ADC. The multiscale analysis method based on the contin-
`uous wavelet transform (CWT), proposed in [34], can help to
`predict the results of dithering application. If nonzero values
`appear in some typical areas in the CWT graph, the dithering
`will not be able to compensate errors of the entire transfer
`characteristic. The position of these areas can be read from the
`CWT graph, and the amount of noise necessary to their partial
`suppression can be estimated. The remaining large-scale errors
`can be eliminated by additional mechanisms (such as LUT).
`In [35], additive dither and frequency shift dither techniques
`are used to extend the ADC dynamic range in microwave appli-
`cations. The paper shows how the dynamic range versus input
`frequency could be made almost constant by adding dither. As a
`consequence, the level of spurious frequencies is also reduced,
`and a better amplitude accuracy for low input signal ampli-
`tudes could be obtained. The frequency shift (FS) plus addi-
`tive dither block diagram is shown in Fig. 5. A pseudorandom
`noise source is used to generate the noise. The propagation delay
`through the ADC must be considered for delaying the noise
`before the digital adder. The amplitude, sign, and delay of the
`noise is adjusted carefully to achieve complete cancellation of
`the noise at the digital output. The frequency shift dither is ob-
`tained by frequency modulating the last local oscillator before
`the ADC, so the whole input spectrum to the ADC is shifted in
`frequency. In order to realize FS dither, an accurate voltage-con-
`trolled oscillator (VCO) is required. This VCO must be able to
`be controlled in a precise manner, such that the resulting fre-
`quency modulation can be removed using digital signal-pro-
`cessing techniques after digitizing. The low-pass filter removes
`any high-frequency component produced by the mixer and also
`serves as an anti-alias filter. By applying frequency shift and
`additive dither, the ADC gives good performance for both large
`and small signals.
`The use of the fast Fourier transform (FFT) to derive the INL
`of a converter is proposed in [36]. In particular, the proposed
`method derives the INL in parametric form as a linear combina-
`tion of Chebyshev polynomials. Moreover, the paper shows that
`frequency-domain measurement of nonlinearity allows also the
`implementation of an efficient linearization algorithm that uses
`
`Fig. 6. Probabilistic model of the ADC [38].
`
`the parametric description obtained by the FFT test. The mea-
`surement and the correction of the nonlinearity have been joint
`in a single fast and simple procedure, which is especially advan-
`tageous in connection with dither techniques.
`It is well known that dithering can be used in general to
`compensate only such nonlinearities whose amplitude are over-
`lapped by the dithering signal amplitude [37]. So, large-scale
`errors require large dithering amplitude. In [38], a probabilistic
`model of the ADC is realized by a noisy channel on the base of
`Bayes theorem (Fig. 6). After the noisy channel, the data flux
`could be recovered by using a suitable postprocessing method.
`In particular, by providing an opportune oversampling factor
`[39] and adding a dithering signal, an inverse Bayesian filter
`followed by a low-pass filter could return damaged data in their
`right positions [38]. The application of the method based on
`the Bayesian filter to the oversampled data flux has shown that
`low amplitude peak–peak dithering can be used to reduce also
`the effect of large INLs. Interpolation process based on Bayes
`theorem, in fact, smooths the distortion in the output signal
`caused by the INL in the ADC transfer characteristic.
`
`IV. METHODS BASED ON A MODEL INVERSION
`
`The closely related Volterra and Wiener models can represent
`a wide class of nonlinear systems with memory. In particular,
`the Volterra model is a mathematical approach for description
`of causal time-invariant systems, where dynamic and nonlinear
`phenomena are simultaneously present. Therefore, a possible
`approach to compensating ADC nonlinearities is to obtain a
`Volterra model for them by estimating the Volterra kernels and
`using an approximate Volterra inverse to recover the distortion.
`A behavioral nonlinear dynamic model predicting the non-
`linear dynamics of sample-and-hold (S/H) ADC devices has
`been recently proposed. The nonlinear dynamic system is rep-
`resented as the cascade of two subblocks (Fig. 7). The first ele-
`ment of the cascade is a purely linear system, which describes
`the memory effects introduced by the input signal conditioning
`circuits (amplifiers, filters, etc.) and the S/H process. The second
`block in the cascade, controlled by the linear transformation re-
`sult and providing the ideal device input signal, is a nonlinear
`system with a memory time which can be considered not only
`finite but also “short” if compared to the typical minimum pe-
`riod of the input signal. This hypothesis is justified by the nature
`of the dynamic nonlinearities, which can be considered related
`only to the active electron devices, usually characterized by fast
`dynamics. Under such conditions, the modified Volterra series
`approach can be applied to the second block of the cascade,
`taking into account only the zero-order and first-order terms of
`the series expansion and without introducing relevant truncation
`
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`BALESTRIERI et al.: A STATE OF THE ART ON ADC ERROR COMPENSATION METHODS
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`Fig. 7. Functional description of the S/H-ADC for the characterization of
`nonlinear (both static and dynamic) effects [40].
`
`A. Successive Approximation Register Converters
`
`Fig. 8. Schematic implementation of the INL correction [44].
`
`errors. The reported experimental results show good agreement
`among the model predictions and the actual device response,
`under operating conditions [40].
`In [41], a fifth-order Volterra model is used to represent the
`sampler’s timing jitter error. The Volterra kernels are obtained
`by using either the Lee–Schetzen method and relating the
`Wiener and the Volterra kernels or an adaptive method to obtain
`the Volterra kernels directly. However, the principle of non-
`linear system identification by means of adaptive Volterra filters
`requires a stationary input signal, but a more complex signal
`is required by the twofold exigencies of mapping exhaustively
`the phase and the memory planes. For these reasons, a different
`approach was followed in [42] by exploiting the mathematical
`error model for a given ADC architecture. This method can be
`considered as the natural evolution of the a priori approach to
`ADC error modeling [43] for a correction-aimed application.
`The a priori approach simplifies the analytical description of the
`filter expression by taking into account specific characteristics
`of the ADC errors. This allows
`
`1) obtaining a more compact expression in the model
`definition;
`2) avoiding a complicated adaptive scheme in model special-
`ization;
`3) computing the Volterra filter coefficients very easily in
`filter identification;
`4) using a simpler signal for calibration.
`
`Another ADC error compensation method, based on a model
`inversion, is proposed in [44]. The method makes the on-line
`correction of the INL by using two identical ADCs, which are
`perfectly matched, one taking the on-line input and the other one
`taking an attenuated version of it (Fig. 8). The INL is modeled
`as an th-order polynomial. The distorted output of the ADC
`is passed through a correction block whose parameters are pe-
`riodically updated by continuously monitoring and estimating
`the INL.
`
`V. ARCHITECTURE-BASED METHODS
`
`In this section, architecture-based compensation methods are
`presented by referring to
`
`1) successive approximation register converters;
`2)
`-
`converters;
`3) pipelined converters;
`4) all-digital converters;
`5) scan conversion-based transient digitizers.
`
`The successive approximation register (SAR) conversion
`principle works under the typical assumption that a maximum
`input signal variation less than 1 LSB is allowed during con-
`version time. So an intrinsic dynamic error arises. In [45], the
`resulting dynamic differential nonlinearity (DNL) has been
`modeled in the phase-plane and then analytically related to the
`bit composition of the ADC output code. This a priori modeling
`approach allows the burden related to model identification to
`be significantly reduced.
`In [46], errors intrinsic to the SAR algorithm are modeled as
`a function of both the output code and the time slope of the input
`signal. The resulting DNL is analytically related to the bit com-
`position of the ADC output code. A compensation based on the
`maximization of the signal-to-noise ratio (SNR) is applied. In
`[46], the method validation results on actual ADCs are reported
`too. They show a good recovery of the phase anticipation in-
`troduced by intrinsic SAR dynamic nonlinearities. The corre-
`sponding SNR increase is also reported.
`
`B.
`
`- Converters
`
`- ADC can achieve high resolution without re-
`A multibit
`quiring high-order modulators and high oversampling ratios, as
`a single-bit design requires. However, in a multibit
`- modu-
`lator, quantization-level errors in the internal multibit quantizer
`can limit the
`- modulator signal-to-(noise and distortion)
`ratio (SINAD) and SFDR. In particular, the comparator offset
`is a relevant source of quantization errors. A comparator offset
`dynamic element matching (DEM) technique for mitigating the
`distortion caused by comparator offsets is presented in [47]. In
`particular, the distortion is reduced by modulating the sign of
`each offset with a random bit sequence.
`- ADCs, the key problem is
`In most state-of-the-art
`how to deal with the inherent nonlinearity of the feedback
`digital-to-analog converter (DAC). Various techniques have
`been suggested to improve the effective DAC linearity. These
`include randomization [48], mismatch error shaping [49], direct
`error correction [50], and digital error correction [51], [52].
`Randomization removes harmonics but raises the noise floor.
`Mismatch error shaping is effective for high oversampling
`) but not useful for wide-band ADCs where
`ratios (OSR
`OSR values can be as low as four. The digital correction tech-
`nique [51] needs extra DAC unit elements and a modified noise
`transfer function, while the method proposed in [52] needs an
`auxiliary ADC for calibration.
`A fully digital algorithm is described in [53] for acquiring
`and correcting the errors of the feedback DAC used in a multibit
`- multistage noise shaping (MASH) ADC (Fig. 9). The
`
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`
`Fig. 9. MASH ADC with the error correction system proposed in [53].
`
`method operates in the background and is highly accurate.
`The method is combined with an improved digital adaptive
`compensation technique, which greatly reduces the raw quan-
`tization leakage in MASH architecture. This solution makes
`possible the design of fast and accurate ADCs using inaccurate
`components.
`
`C. Pipelined Converters
`
`Pipelined ADCs have been shown to work at very high
`speeds, but
`their resolution is limited by component mis-
`matches, op-amp gain error, offsets, charge injection errors,
`and component nonlinearities. Background calibration tech-
`niques have been developed to compensate these error sources
`[54], [55]. Moreover, none of these techniques corrects all the
`systematic nonidealities within a single framework.
`A least mean square (LMS)-based mixed-signal scheme for
`self-calibration of pipelined ADCs is presented in [56]. The
`technique corrects for gain and offset errors in a pipeline stage
`with minimal area and power overhead. In particular, the error
`compensation is performed in the analog domain through the
`reference voltages regulation at each pipeline stage.
`A new background calibration all-digital, adaptive, and data-
`driven algorithm for pipelined ADCs is proposed in [57]. An a
`priori model of pipelined ADC errors is postulated considering
`that these errors can be modeled as distortion in code domain.
`Then an adaptive linear equalization (LE) technique is intro-
`duced to remove memoryless linear errors.
`In particular, [57] proposes an adaptive digital background
`calibration scheme using the steepest gradient descent algorithm
`of a high speed, inaccu-
`shown in Fig. 10. The output vector
`rate pipelined ADC is decimated and applied to an adaptive dig-
`ital filter (ADF). A parallel, slow-but-accurate ADC is used to
`obtain
`while the ADF tap values are updated using an LMS
`algorithm driven by the error signal
`. The update is performed
`at the speed of the slow ADC. After the initial acquisition, the
`slow ADC sampling should be fast enough to track only tem-
`perature variation, supply voltage drift, and component aging.
`In [58], an improved calibration and compensation scheme
`for pipeline ADCs utilizes the intermediate stage outputs in the
`pipeline to characterize error mechanisms in the architecture.
`The main goal of this compensation scheme is to increase the
`ADC dynamic range. Dominant error mechanisms are defined
`and characterized for an arbitrary stage in the pipeline. These
`error mechanisms are modeled with a basis function decompo-
`sition. The calibration scheme proposed in [16] is modified and
`used to iteratively calculate the error characteristics. The infor-
`mation from calibration is then used to compensate the ADC.
`
`Fig. 10. Error correction of pipelined ADC: code-domain LMS adaptive LE
`[57].
`
`Fig. 11. Block diagram of A/D converter (TAD) [60].
`
`D. All-Digital Converters
`
`High-resolution ADC architectures have analog circuits such
`as op-amps, resistors, and capacitors. To overcome the errors
`introduced by such components, an all-digital architecture has
`been proposed in [59] and [60]. The basic structure of this con-
`verter, called time ADC (TAD), is a completely digital circuit
`including a ring-delay-line (RDL) with delay units (DUs), along
`with a frequency counter, latch, and encoder (Fig. 11). The op-
`erating principle is to count the number of DUs through which
`the delay pulse passes within a sampling interval. At the time of
`latch clock (CKL) pulse, the position of the propagation pulse
`that goes around the RDL is digitized by the encoder, and then
`is provided at the output as the low-order bit data. With input
`of CKL, the output data of the counter that counts up P16 are
`latched and taken unchanged as the high-order bit data. Each
`time of the latch clock CKL pulse, the preceding datum is sub-
`tracted from the new datum made up of the high-order bit data
`and low-order bit data, providing as output the digital data of
`the inverted gate number between two consecutive latch clock
`CKLs.
`This architecture does not require S/H circuits, while their
`inner low-pass filter function removes high-frequency noise si-
`multaneously with A/D conversion. The correction of residual
`nonlinearity error is then made by digital processing. The TAD
`behavior in fact can be predicted by using an approximation
`equation.
`The previously quoted papers propose two correction
`methods:
`the former uses multistraight
`line approximation
`with three voltage references and the latter uses a parabolic
`approximation.
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`E. Scan Conversion-Based Transient Digitizers
`
`Waveform recorders using the scan principle are widely em-
`ployed in the acquisition of ultra-high-speed transients. This ap-
`proach allows the realization of transient digitizers having real-
`time sampling rates of up to some hundreds of Gigasamples per
`second. However, due to the working principle, in commercial
`solutions the digitizer bandwidth is limited to a few gigahertz by
`the on-line memorization process in the writing cathode tube.
`Moreover, for not very high-frequency signals, both standard
`and specific techniques of characterization showed the nominal
`metrological performance by manufacturers to be reduced.
`In order to overcome these limits, a correction technique has
`been developed for this particular type of waveform recorder. It
`is based on an algorithmic distortion model of the error on the
`matrix column and on the availability of an internal reference
`offset source [61].
`
`VI. CONCLUSION
`
`ADC error compensation is a very attractive research field, as
`evidenced by the large number of scientific contributions. In this
`paper, the state of the art and the leading trends of the research
`in the field of ADC error correction have been presented. This
`paper can help young researchers interested in ADCs to orien-
`tate themselves in this research field. Due to the large number of
`activities in this field and the quickness with which they evolve
`in time, the authors beg the reader’s pardon in advance for the
`omissions surely present in this paper, principally due to time,
`space, and manpower limits.
`
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