[19]
`United States Patent
`5,010,339
`{11] Patent Number:
`Apr. 23, 1991
`[45] Date of Patent:
`Gianganoet al.
`
`[54] ULTRA LINEAR SPECTROSCOPIC
`ANALOG-TO-DIGITAL CONVERTER
`
`[75]
`
`Inventors: David A. Giangano, Elmhurst; Martin
`Kesselman, Commack; Steven
`Bocsker, Ronkonkoma; Anthony R.
`Celona, Northport, all of N.Y.
`
`[73] Assignee:
`
`Grumman Aerospace Corporation,
`Bethpage, N.Y.
`
`"
`
`[21] Appl. No.: 502,746
`(22) Filed:
`Apr.2, 1990
`[SV]
`Tmt, CUS cecssssssscsscssscssesssessssnenessesese HO03M 1/34
`[52] U.S. CU. caesessssssssnsscseseessssseesees 341/164; 341/165;
`341/127
`[58] Field of Search............... 341/165, 164, 163, 155,
`.
`341/127, 118
`References Cited
`U.S. PATENT DOCUMENTS
`
`[56]
`
`4,839,650 6/1989 Geen etal. ......cccsssreseee 341/155 X
`4,897,650
`1/1990 Shott, Iet al.
`.............. 341/164 X
`
`OTHER PUBLICATIONS
`
`Giangano, D.A., “Ultra-Linear, 14-Bit Spectroscopy
`ADC,” Grumman Corporate Research Center, Beth-
`page, New York.
`Cottini, et al., “Letters to the Editor—A New Method
`for Analog to Digital Conversion,” Nuclear Instru-
`ments and Methods, 24 (1963) 241-242; North—Hol-
`land Publishing Co.
`Correia,et al., “An Analog-to-Digital Converter Mod-
`
`ule for Nuclear Spectrometry,” Nuclear Instruments
`and Methods in Physics Research, A235 (1985) 536-241
`North—Holland, Amsterdam.
`Xianjie, et al., “A New Sliding Scale Principle and the
`Spectroscopic ADC Based onthis Principle,” Nuclear
`Instruments and Methods in Physics Research, A259
`(1987) 521-524, North Holland, Amsterdam.
`Morita, M., et al. “An Ultra High Throughput ADC,”
`IEEE Transactions on Nuclear Science, vol. 36, No. 1,
`Feb. 1989.
`Ditigal Device Corp., 12-bit, +4 LSB DNL, 500 nSec,
`Subranging ADC.
`
`Primary Examiner—A.D. Pellinen
`Assistant Examiner—Sharon D. Logan
`Attorney, Agent, or Firm—Pollock, VandeSande &
`Priddy
`
`ABSTRACT
`[57]
`A sliding scale averaging technique is employed for an
`analog-to-digital converter. An analog signal is summed
`with a varying numberprior to conversion. This causes
`repeated input voltage signals of the same value to be
`converted in different bins of the ADC converter
`thereby minimizing errors due to unequal bin widths.
`Thepresent invention includes a comparator technique
`for ensuring that the summedsignal does not exceed the
`full dynamic range of the ADC.
`
`9 Claims, 2 Drawing Sheets
`
`
`
`
`VIN
`DOUT
`
`
`REF.
`OUT
`
`
`
`Xilinx Exhibit 1013
`
`Page 1
`
`

`

`U.S. Patent
`
`Apr. 23, 1991
`
`Sheet 1 of 2
`
`5,010,339
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`
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`U.S. Patent
`
`Apr, 23, 1991
`
`Sheet 2 of 2
`
`5,010,339
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`3,010,339
`
`1
`
`ULTRA LINEAR SPECTROSCOPIC
`ANALOG-TO-DIGITAL CONVERTER
`
`FIELD OF THE INVENTION
`
`Thepresent inventionrelates to pulse height spectro-
`scopic analyzers, and more particularly to an analog-to-
`digital converting system for such analyzers.
`BACKGROUND OF THE INVENTION
`The analog-to-digital converters (ADCs) used in
`pulse-height spectroscopic analyzers displaying ampli-
`tude probability distributions of electric signals require
`low differential non-linearity (ONL) and low conver-
`sion time. Commercially available ADCs cannot be
`directly used for spectroscopic applications, since DNL
`associated with them can be as high as +1 least signifi-
`cant bit (LSB). This is unacceptable for spectroscopic
`applications, which require a DNL of +1/100 LSB.
`Many techniques have been developed to achieve this
`requirement. These techniques rise sharply in complex-
`ity as a direct result of higher resolution and utilization
`of full ADC dynamic range.
`BRIEF DESCRIPTION OF THE PRIOR ART
`
`The standard sliding scale method is discussed in the
`teference: Cottini, C., et al., Nucl Instru. and Meth. 24
`(1963) 241. The system of this reference utilizes a bin
`width averaging effect obtained by summing an auxil-
`iary incrementing analog signal to the ADC input,
`whose digital representation is subtracted from the
`ADC outputafter conversion in order to obtain the true
`digital representation of this input. This block diagram
`for carrying out this method is shownin FIG. 1, which
`is discussed herein. For each input value the ADC con-
`version pointis thus incrementally distributed assigning
`different channels to the input. The result of this opera-
`tion is the statistical equalization of the channel widths.
`A major drawback of this method is the reduction in
`ADC dynamic range by an amount equal to the auxil-
`iary level range. This is discussed in the reference:
`Correia, C. B. A., Nucl Instr. and Meth., A235 (1985)
`536. This effect takes place at the top of the inputscale,
`if the incrementing signal is positive, and can occur
`wheneverthe input voltage falls within the last M chan-
`nels of the ADCrange, M being the numberof channels
`swept by.
`the averaging digital-to-analog converter
`(DAC). A dilemmaarises from this limitation, because
`the sweeping range of the averaging DAC must be
`small in order to keep a large input range, but large
`enoughto have an efficient averaging effect.
`A morerecent approachto this problem incorporates
`upward and downward averaging, for no waste of dy-
`namic range. Such an approachis exploredin therefer-
`ence: Xianjie, X., Nucl. Instr. and Meth., A259 (1987)
`521. A threshold circuit is used in the ADCestablishing
`a comparator trip point somewhere around the middle
`of the ADC.If the amplitudeof the input signal exceeds
`the threshold, a downward averaging process is per-
`formed. If not, the upward averaging process will be
`used.
`Problems with this approach arise, because the
`threshold must not lie in the upper or lower 20"—)D
`channels. Channel width of the channel in which the
`threshold lies is not averaged. In order to equalize the
`channel width of this channel, the threshold must be
`modulated by a triangular voltage, so that the width of
`this special channel is also smoothed. The worst DNL
`
`2
`of a successive approximation ADC usually occurs3, 3,
`and § of full scale. Therefore, the modulated region of
`the threshold cannot be placed in the above areas, and
`at the same time it should not overlap the upper and
`lower 2¢"—!) channels. This limits the amount of aver-
`aging bits of M to (N—2) N being the resolution of the
`ADC.
`Complicating the matter further, new high speed
`subranging ADCs exhibit poor DNLat their internal
`transition between ranges. The internal architecture of
`this type of ADC performs a flash conversion on the
`seven MSBsfirst, then processes the five LSBs (25=32)
`next. This creates an internal split point that exhibits
`poor DNLassociated with that bit. Since all ADC
`manufacturers use varying techniques, DNL regions
`fluctuate from device to device.
`
`BRIEF DESCRIPTION OF THE INVENTION
`
`The simplicity of the ADC system presented herein,
`in comparison to conventional ones, achieves a success-
`ful solution of the aforesaid problem by presenting a
`realizable technique for achieving higher stability and
`accuracy with lower DNLand circuit complexity.
`A newsliding scale averaging technique has been
`used for an N-bit ADC. The numberof bits M for a
`sliding scale may be increased from (N—2) defined in
`the previous method to N. This obtains 100 percent
`averaging while still maintaining full ADC dynamic
`range. The modulation circuit required in the previous
`method is no longer needed. This change in design
`methodology lowers part count, circuit complexity, and
`improves circuit stability.
`BRIEF DESCRIPTION OF THE FIGURES
`
`The above-mentioned objects and advantages of the
`present invention will be more clearly understood when
`considered in conjunction with the accompanying
`drawings, in which:
`FIG.1 is a block diagram ofthe priorart;
`FIG.2 is a block diagram of the present invention;
`FIG.3 is a plot of a histogram obtained with channel
`averaging;
`FIG. 4is a plot of a histogram obtained without chan-
`nel averaging.
`DETAILED DESCRIPTION OFTHE
`INVENTION
`
`Prior to exploring the operation of the present inven-
`tion, the prior art of FIG. 1 will be discussed since the
`present invention is an improvement thereover. Con-
`ventional ADCcircuits, such as indicated by reference
`numeral 8, perform conversions in a numberof contigu-
`ous channels, a particular channel depending upon the
`value of the analog input voltage. Conceptually, the
`channels are to have equal width so that input voltage
`signals across the entire dynamic range of the converter
`should be evenly distributed within the various chan-
`nels. However,in reality, this is not the case; and in fact,
`certain bins will be larger than others. In order to avoid
`this problem,the priorart illustrated in FIG. 1 basically
`variably shifts the level of the input voltage to the con-
`verter so that the same input voltage during different
`inputintervals will be converted in different channels of
`the converter. Accordingly, any errors will be averaged
`thereby minimizing their effect.
`In order to understand how this is accomplished,
`continuing reference is made to FIG. 1 wherein number
`
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`5,010,339
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`3
`exceeds the full range reference output (“B”), the com-
`generator1 is included in the circuit to achieve the level
`parison by comparator 26 will generate a binary 1
`shifting just discussed. The generator 1 may be a ran-
`which is transferred to the most significant bit (MSB)
`dom numberor sequential number generator of conven-
`tional design. Its output forms the input 2 of DAC3.
`input 23 of DAC 22. This causes the summer 14 to
`subtract the inputs 17 and 18 thereby ensuring that the
`After conversion to an analog form, the generated num-
`analog output from summer 14 will not exceed the full
`ber is summed, via line 4, with the input voltage 4 (at
`range of the ADC 28.
`:
`input contact 6) in a unity operational amplifier summer
`The output of summer14 is connected to the input 27
`5. The resultant output at line 7 is input to the ADC 8.
`of ADC 28. The output of the ADC 28is supplied to the
`Thus, during two successive intervals wherein the same
`input “A”of a digital adder 30. A parallel output of the
`input voltage is present, the generated number will be
`different so that the resultant summed numberat line 7
`counter 20 is connected to the input “B”of digital adder
`30.
`will be converted by different bins of the ADC 8. Now,
`Thedigital adder 30 performs a 2’s complementaddi-
`it is importantto restore the original input voltage. This
`tion which,in effect, subtracts the counter numberfrom
`is accomplished at a digital subtractor 11. This sub-
`the output of the ADC 28so that the output 32 of adder
`tractor has the first level shifted input “a” while the
`30 is a converted digital transformation of the analog
`number generator is connected to a second input “b”
`input at 15. However, in the event that the summer 14
`along connecting lead 10. The subtractor then subtracts
`sums two quantities which exceed the full range of
`the value of the generated number so that the original
`ADC 28, and as a consequence the MSB of DAC22is
`voltageis retrieved The end result is that the conversion
`set, the terminal 25 of the threshold comparator 26 is
`for the same value of input voltage will occur in differ-
`also connected to the “carry in” input of the digital
`ent bins of the ADC 8 so that any conversion errors due
`adder 30 thereby resulting in normal addition. As a
`to uneven channel widths is averaged out.
`consequence, a proper digital output from the adder 30
`In order to obtain a spectroscopic distribution of the
`is again obtained representing the digital analog of the
`input voltages, a computer 13 is connected to the output
`of the subtractor 11. The computer performs an ampli-
`input voltage at 15. In a preferred embodiment of the
`tude probability distribution in accordance with well-
`present invention, the ADC 28 is a 14-bit converteras is
`known techniques so that a histogram of counts for
`the bi-polar DAC22.In order to ensure proper conver-
`sion of the analog input, the “B” input of adder 30 in-
`particular input voltages may be obtained as a function
`of ADC channel number.
`cludes the 13 bits of the counter output 20 while a most
`significant bit is formed at terminal 36, in parallel with
`FIG.4 illustrates a typical amplitude probability dis-
`tribution from a straightforward ADC 8 withoututiliz-
`the output terminal 25 of comparator 26 and control
`carry input 34.
`ing the averaging technique just discussed. The sharper
`Since regular subtraction (at summer 14) or down-
`and moreclearly defined distribution of FIG.4 is typi-
`cal for the same inputsignal and data collection time for
`ward averaging takes place as a result of the summed
`an ADC 8 whichis connected as shown in FIG. 1 and
`input voltage and DACvoltage exceeding the dynamic
`wherein the discussed averaging technique is employed.
`range of the ADC 28,the input threshold trigger point
`However, as previously discussed, the dynamic range
`for the ADC constantly changes. This eliminates the
`of ADC8is reduced by an amount equal to the auxil-
`need for a modulation circuit as required by the prior
`iary level shifting of the converted generated number
`art to average the threshold point.
`supplied to summer5.
`Thus, as a result of the present invention, a newslid-
`The improvement constituting the present invention
`ing scale averaging technique has been developed
`which utilizes a greater number of bits for a sliding
`is illustrated in FIG. 2. The system set forth in FIG. 2
`also accomplishes a bin averaging technique but avoids
`scale. The end result is 100 percent averaging which
`the problems discussed in connection with the imple-
`produces an improvementin differential non-linearity
`mentation shown in FIG. 1. In greater detail, this is
`(DNL)bya factorof4, whilestill maintaining full ADC
`accomplished whenan input voltage appearing at termi-
`dynamic range. The modulation circuit of the prior art
`nal 15 is sampled by a track-and-hold circuit 16. The
`being no longer required results in fewer circuit parts
`outputofthe latter circuit is input at 17 to the unity gain
`and complexity as well as a reduced potential drift prob-
`operational amplifier summer 14. A secondinput to the
`lem. Calibration time is also reduced andcircuit stability
`summer 14 occurs at terminal 18 which carries the ana-
`is enhanced.
`log form of the converted digital count at the sampling
`A computer 13 is connected to the output of adder 30
`moment. The counter 20 is basically a sequential gener-
`so that a histogram showinga clear amplitude probabil-
`ator that is input to DAC 22at the latter circuit’s least
`ity distribution can be generated, as shown in FIG.3.
`significantbit inputs (LSB). Prior to any conversion, the
`Thedistribution of FIG. 3 is merely illustrative of the
`output 24 of summer 14 is compared with the full range
`ability of the present invention to serve in a spectro-
`scopic system. FIG. 3 illustrates the advantage of an
`of the ADC 28 to determine whether the summedsignal
`falls outside its full range. To accomplish this, the ADC
`averaging technique as opposed to the acquisition of a
`28 has a full range output signal at 29 which serves as
`histogram without an averaging technique, the latter
`input “B” of threshold comparator 26. The output of
`being demonstrated in FIG.4.
`It should be understood that the invention is not lim-
`summer 14 is directly connected to input “A” of the
`ited to the exact details of construction shown and de-
`comparator 26. If the full scale reference output of
`scribed herein for obvious modifications will occur to
`ADC 28 (“B”) is greater than the signal summed at
`summer14 (‘‘A”), the output of the threshold compara-
`personsskilled in the art.
`Weclaim:
`tor generates a binary zero so that the mostsignificant
`bit (CMSB) of the bi-polar DAC 22 is not set and the
`1. In an analog-to-digital converter (ADC) network
`circuit will operate in a mannersimilar to that explained
`having meansfor generating a variable analog countfor
`in connection with the priorart circuit of FIG. 1. How-
`summing with an analog input signal,
`the result of
`ever, in the event that the addition at summer 14 (“A”)
`which is converted to a digital number by an ADC,the
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`5
`variable count being subtracted thereafter for a final
`digital output, the improvement comprising:
`bi-polar digital-to-analog converter (DAC) means
`connected between a digital number generator
`which generates the variable count anda first input
`of a summing means;
`means for sampling the input signal;
`means for connecting the sampled input signal to a
`second input of the summing means;
`a comparator;
`means connecting a full scale reference voltage of the
`ADC to a first input of the comparator;
`means connecting the output of the summing means
`to a second input of the comparator to obtain a
`comparison;
`the bi-polar DAC having a most significant bit CMSB)
`input connected to the output of the comparator
`for setting the MSB of the DAC whenthe compar-
`ison indicates the full scale of the ADC is exceeded;
`wherein first and second inputs of the summing
`means are subtracted thereby producing a compar-
`ator input within range for the ADC; and
`means connected to the output of the ADC and the
`numbergenerator for separating the variable count
`from the output of the DAC thereby reconstruct-
`ing the digitally converted analog input signal.
`2. The subject matter set forth in claim 1 wherein the
`sampling meansis a track-and-holdcircuit.
`3. The subject matter set forth in claim 1 wherein the
`number generator generates sequential numbers.
`4. An analog-to-digital converter (ADC) network
`comprising:
`°
`a summingcircuit connected at a first input to a sam-
`pled input analog signal voltage;
`a digital number generator;
`a bi-polar digital-to-analog converter (DAC) con-
`nected between the digital number generator and a
`second input of the summingcircuit;
`an ADC having a full scale reference voltage output
`connected to a first input of a comparator, the
`comparator having a second input connected to an
`output of the summing circuit for determining
`whether a summed sampledsignal and a converted
`count from the generator exceedsthe full range of
`the ADC;
`means connecting an output of the comparator to a
`most significant bit (MSB) input of the bi-polar
`DAC for reversing the polarity of the bi-polar
`DAC whenthe full range is exceeded;
`means havingfirst and second inputs connected to an
`output of the ADC and an output of the number
`generator for eliminating any contribution of a
`
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`6
`converted count from the output of the ADC
`thereby reconstructing a digital value of the sam-
`pled input analog voltage signal.
`5. The structure set forth in claim 4 wherein a track-
`and-hold circuit samples the input analog signal volt-
`age.
`6. The structure set forth in claim § wherein the num-
`ber generator generates sequential numbers.
`7. The structure set forth in claim 4 together with
`computer meansfor storing the numberoftimes partic-
`ular ranges of the values of input analog signal voltage
`occur thereby permitting the generation of a histogram
`from the input analog signal voltage.
`8. A method for generating a spectroscopic histo-
`gram comprising the. steps:
`subjecting detectors to nuclear particles for generat-
`ing a characteristic voltage therefrom;
`generating a variable count;
`converting the count to an analog quantity;
`summing the voltage with the analog quantity;
`comparing the summed voltage and quantity to a full
`scale reference voltage of an analog-to-digital con-
`verter;
`in the event the summed values areless than the refer-
`ence voltage
`(a) performing an analog-to-digital conversion on
`the summed voltage and quantity;
`(b) subtracting the converted analog count quan-
`tity from the converted summed quantity and
`voltage thereby producing a digital output repre-
`sentative of the characteristic voltage;
`in the event the summed value is greater than the
`reference voltage
`(a) subtracting the converted analog count quantity
`from the voltage;
`(b) performing an analog-to-digital conversion on
`the result of the immediately preceding step; and
`(c) adding the digital count to the digital result of
`the immediately preceding step thereby produc-
`ing a digital output representative of the charac-
`teristic voltage;
`dividing digital outputs representative of the charac-
`teristic voltage into corresponding continuous
`channels;
`storing the number of occurrences in each channel
`over a preselected interval thereby creating data
`for a histogram.
`9. The method set forth in claim 8 together with the
`preliminary step of tracking and holding each generated
`characteristic voltage.x
`*
`x
`*
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