Trials@uspto.gov
`571-272-7822
`
`Paper 33
`Entered: January 19, 2022
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_________________
`
`XILINX, INC. and
`TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.,
`Petitioner
`
`v.
`
`ARBOR GLOBAL STRATEGIES LLC,
`Patent Owner.
`_________________
`
`IPR2020-01567 (Patent 7,126,214 B2)
`IPR2020-01568 (Patent 7,282,951 B2)
`IPR2020-01570 (Patent RE 42,035)
`IPR2020-01571 (Patent 6,781,226 B2)
`_________________
`
`Record of Oral Hearing
`Held Virtually: December 3, 2021
`_________________
`
`Before KARL D. EASTHOM, BARBARA A. BENOIT and
`SHARON FENICK, Administrative Patent Judges.
`
`
`
`

`

`IPR2020-01567 (Patent 7,126,214 B2)
`IPR2020-01568 (Patent 7,282,951 B2)
`IPR2020-01570 (Patent RE 42,035)
`IPR2020-01571 (Patent 6,781,226 B2)
`
`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
`
`
`KENNETH W. DARBY, JR., ESQ.
`DAVID M. HOFFMAN, ESQ.
`Fish & Richardson, P.C.
`111 Congress Avenue, Suite 810
`Austin, Texas 78701
`(512) 226-8126 (K. Darby)
`(512) 226-8154 (D. Hoffman)
`k.darby@fr.com
`hoffman@fr.com
`
`JEFFREY SHNEIDMAN, Ph.D.
`Fish & Richardson, P.C.
`One Marina Park Drive
`Boston, Massachusetts 02210-1878
`(617) 542-7045
`shneidman@fr.com
`ptabinbound@fr.com
`
`and
`
`JAMES GLASS, ESQ.
`Quinn Emanuel Urquhat & Sullivan, LLP
`51 Madison Avenue, 22nd Floor
`New York, New York 10010
`(212) 849-7142
`jimglass@quinnemanuel.com
`
`ZIYONG LI, ESQ.
`Quinn Emanuel Urquhat & Sullivan, LLP
`50 California Street, 22nd Floor
`San Francisco, California 94111
`(415) 875-6373
`seanli@quinnemanuel.com
`
`
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`2
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`

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`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
`
`ON BEHALF OF THE PATENT OWNER:
`
`
`
`
`JONATHAN S. CAPLAN, ESQ.
`JEFFREY H. PRICE, ESQ.
`Kramer Levin Naftalis & Frankel, LLP
`1177 Avenue of the Americas
`New York, New York 10036
`(212) 715-9488 (J. Caplan)
`(212) 715-7502 (J. Price)
`jcaplan@kramerlevin.com
`jprice@kramerlevin.com
`
`and
`
`JAMES HANNAH, ESQ.
`JENNA FULLER
`Kramer Levin Naftalis & Frankel, LLP
`990 Marsh Road
`Menlo Park, CA 94025
`(650) 752-1712 (J. Hannah)
`(650)752-1728 (J. Fuller)
`jhannah@kramerlevin.com
`jfuller@kramerlevin.com
`
`
`
`The above-entitled matter came on for hearing on Friday, December
`
`3, 2021, commencing at 9:00 a.m. EST, via Video Teleconference.
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`

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`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
`
`
`
`PROCEEDINGS
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`9:00 a.m.
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`JUDGE EASTHOM: Good morning. This is Judge Easthom and
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`with me is Judges Benoit and Fenick. This is case Xilinx Inc. and Taiwan
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`Semiconductor Manufacturing Company, Ltd., versus Arbor Global
`
`Strategies, LLC.
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`The case numbers are IPR 2020-01567, -01568, -01570, and -01571.
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`The patents in respective order are patent 7,126,214 B2, 7,282,951 B2,
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`Reissue 42,035 E, and then 6,781,226 B2. Who do we have on the record
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`for Petitioner?
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`MR. SHNEIDMAN: Good morning, Your Honors. This is Jeffrey
`
`Shneidman of Fish & Richardson and I am joined here today on behalf of
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`Petitioner Xilinx by my co-counsel David Hoffman and Kenneth Darby.
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`JUDGE EASTHOM: Welcome, gentlemen. So, Mr. Shneidman,
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`will you be presenting first or for most of it?
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`MR. SHNEIDMAN: Yes, sir, that is correct.
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`JUDGE EASTHOM: Great, okay, and then who do we have for
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`Patent Owner?
`
`MR. HANNAH: Good morning, Your Honor. This is James
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`Hannah on behalf of Arbor, and with me is Jeffrey Price and Jenna Fuller,
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`and Mr. Price will be taking the lead on the argument today.
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`JUDGE EASTHOM: Okay.
`
`MR. PRICE: Good morning, Your Honors.
`
`JUDGE EASTHOM: Good morning, Mr. Price, and Mr. Hannah,
`
`and Ms. Fuller. Okay, just a few ground rules really quickly. I think you’re
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`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
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`all familiar with the procedure here. I just want to make sure that everybody
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`
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`knows that first of all, we’re very grateful for your flexibility in conducting
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`this video hearing telephonically. We know it’s a departure from our past
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`practices, but we’re sort of used to it now.
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`Still, our primary concern is that you all have the right to be heard,
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`so anytime during this proceeding that anything goes awry, if you can’t hear
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`or you can’t see, please let us know immediately if you can. There are some
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`numbers you can call if you totally get cut off. For example, one of them is
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`571-272-6666 or you can call the Board at 571-272-9797.
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`And please, when you’’re not speaking, please mute yourself, and
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`when you first start speaking, introduce yourself or at least the first few
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`times until the court reporter and everybody gets used to you. I think your
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`name will show up, so maybe we don’’t need to do that except for the first
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`time. If the court reporter wants to let us know, that would be helpful if they
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`can’’t tell who is speaking.
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`But other than that, we can see the entire records, including
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`demonstratives, so, and when you refer to them, please give us the name and
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`clearly the slide number and the page number, and then just pause a couple
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`seconds so that we can turn to it and we know where you’’re going.
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`And then just a matter of bookkeeping, Petitioner is going to go first.
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`They have the burden of proof. Patent Owner will go next to rebut that case,
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`and then any rebuttal time that Petitioner reserves, then Petitioner can then
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`address Patent Owner’s arguments, and then Patent Owner can address
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`Petitioner in sur-reply arguments.
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`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
`
`
`
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`Then also, the panel wanted to make sure that everybody is aware,
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`and I’’m sure you are, that with three of the patents, the Board issued final
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`written decisions last week, and those involved patent 7,282,951 and that
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`case was IPR2020-01021, and then the reissue patent, RE42,035 E, we
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`issued a final written decision in IPR2020-01020, and then in the 6,781,226
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`B2 patent, we issued a final written decision in IPR2020-01022.
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`So, during the hearings, we could probably refer to those as the 1021
`
`case, the 1020 case, and the 1022 case, and we did issue claim construction
`
`in those cases. We would be interested for the parties to know what they
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`feel about those going forward here. I think there’’s a big overlap with what
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`’you’re going to be arguing here. The art is different and we understand
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`that.
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`So, with that, does anybody have any questions? Why don’’t we ask
`
`you, Petitioner?
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`MR. SHNEIDMAN: No questions, Your Honor.
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`JUDGE EASTHOM: Okay, how about, okay, Mr. Price, do you
`
`have any questions?
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`MR. PRICE: No, Your Honor.
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`JUDGE EASTHOM: Okay, and I’’m sorry, Mr. Price, you’’re going
`
`to be speaking first, is that right? I just want to --
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`MR. PRICE: No, Your Honor, I won’’t be speaking first.
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`JUDGE EASTHOM: Mr. Hannah would. Okay, I’’m sorry. I got
`
`my notes --
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`MR. PRICE: I’m sorry, it’’s Mr. Shneidman.
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`JUDGE EASTHOM: No, I mean --
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`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
`
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`MR. PRICE: Mr. Shneidman will be speaking.
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`JUDGE EASTHOM: Mr. Shneidman will be speaking for
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`Petitioner, but for Patent Owner, it will be Mr. Price, right? Okay, sorry
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`about that. I got it. Okay, Mr. Shneidman, you may begin.
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`MR. SHNEIDMAN: Great, thank you, Your Honors. Again, this is
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`Jeffrey Shneidman of Fish & Richardson on behalf of Petitioner Xilinx for
`
`these matters. I would like to reserve 40 minutes of my time today for
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`rebuttal.
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`And I’’m glad Your Honors raised the final written decisions that
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`concern three of the patents in today’s cases that were issued in the Samsung
`
`v. Arbor matters last week. I do want to be sure to address today how the
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`Board’s claim constructions in those matters reinforces the strength of
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`Xilinx’s position in these matters before you today, and so I want to make
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`sure that our position on that is considered as part of the record.
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`Now, we have submitted a slide deck, Exhibit 1109, in all of the
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`matters, and if you have that open, Exhibit 1109, I am not going to go
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`through every demonstrative slide, but I do plan today on hitting what I
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`believe are the core issues and disputes, but, of course, if the Board has
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`questions on certain items, I’m happy to jump to discuss what you want to
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`discuss today.
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`So, I’’ll pause to see if there are any initial questions, and if not, I
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`would ask you to turn to slide seven.
`
`So, by the time that the Huppenthal patents were filed starting in
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`2001, there was already considerable related relevant prior art in the field,
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`and even beyond the art at issue, at direct issue in these proceedings as the
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`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
`
`grounds, references like Koyanagi disclosed 100,000 distributed
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`
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`interconnections between layers of a 3D stack for the purpose of
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`acceleration.
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`References like Bertin 1998 shown here on the top showed a
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`programmable array stackable with a memory connected with a plurality of
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`contact points, and references like Casselman in the lower left here taught an
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`FPGA stacked with a microprocessor and memory and data shared between
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`those layers.
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`Xilinx’’s expert, Dr. Franzon, published a survey paper in 1998
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`which was titled “A Review of 3D Packaging Technology” that addressed
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`and summarized many of the issues that the Huppenthal patents claimed as
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`points of purported novelty.
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`So, many variations on this theme have been done and were known
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`to the POSITA, and were summarized at length by both Dr. Franzon and
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`others, but Dr. Franzon, in his expert reports, and his declarations, and his
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`1998 survey paper.
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`So, there can be no question that had the inventors put the relevant
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`prior art before the Patent Office, that none of these challenge claims would
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`have issued.
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`I can turn to slide nine. We lay out here on slide nine the disputes at
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`issue in these trials. Now, it’s notable that most of the examiner’s original
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`reasons for allowance on these patents has nothing to do with the disputes
`
`before the Board today.
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`As one example, Arbor has not alleged that there is any missing
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`element from the 035 patent claims 1 through 22, 31, 34, 35, or 37. Now,
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`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
`
`yes, Arbor is challenging the sufficiency of the motivation to combine, but
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`
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`Arbor is not challenging that any element is missing in the prior art from
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`these 26 claims.
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`So, the alleged disputes that Arbor raises are not really inventive
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`aspects. In most cases, they are claim elements with literally a couple of
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`words in support in the specification with no explanation. They were
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`commonly understood and readily found features in the prior art.
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`Now, I’m going to walk through several of these disputes starting
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`with the accelerate terms, which we identify as Issue 1A under the
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`Zavracky-Chiricescu-Akasaka ground, and this is a dispute relevant to the
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`claims in the 214, 951, and 035 patents as shown in this chart.
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`So, if we could turn to slide 22? So, slide 22 shows the
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`representative claim language in the 035 patent, independent claim 23 and
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`its dependent claim 24. And in general across the disputes today, I’m going
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`to be focusing on the examples from 035 and the 226 patents because
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`Arbor’s responses in the 951 and the 214 are largely subsets of the
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`arguments in these two cases. My arguments, of course, are applicable to all
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`of the proceedings.
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`On slide 23, I summarize Xilinx’s reasoning as to this issue. Now,
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`the first key point is that Arbor assumes and addresses these claims only
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`using its own erroneous claim construction. Arbor chose not to address the
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`Board’s institution decision claim construction and Arbor did not address
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`Petitioner’s plain and ordinary meaning of these accelerate terms.
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`Second, the Petitioner showed that the Zavracky-Chiricescu-Akasaka
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`combination provides this claim element under any reasonable construction
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`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
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`based on the specification, claims, and file history of these patents. Now,
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`
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`I’’m going to go through the Board’s construction as it was discussed in the
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`recent Samsung 951 opinion in a moment.
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`Third, even though Arbor’s attacks assume its own incorrect
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`construction for these accelerate terms, even using Arbor’s construction,
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`Arbor does not, excuse me, put forward a fair presentation of the evidence in
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`the record, and I’’m going to talk a little bit about that.
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`If you could turn with me to slide 25, I briefly want to address claim
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`construction. Now, I know the Board has spent considerable time on this
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`issue and I’m going to focus on the Board’s construction issued last week in
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`a moment, but I want to make a few points about Arbor’s position because it
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`goes to the credibility of Arbor’’s current expert.
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`In these matters, Arbor has taken the position that these accelerate
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`terms are plain meaning terms, but has also stated that the terms require a
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`wide configuration data port. And just a brief point here is that the claim
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`language says no such thing. It does not mention a wide configuration data
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`port. It’s not a requirement of these claims.
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`And on slide 26, we lay out how Arbor, in parallel proceedings, has
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`taken a litany of different positions as to the plain and ordinary meaning of
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`these accelerate terms. So, Arbor has cited the memory and using the
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`memory as an intermediary buffer that is as a cache for providing the claim
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`elements.
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`Arbor has cited the short interconnects to the memory die. Arbor has
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`cited the stacking techniques generally as providing the acceleration
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`elements. Arbor has cited close proximity of the interconnects to the
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`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
`
`memory die as providing the claim elements, and Arbor has stated that any
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`speed increase over what the speed would otherwise be without the memory
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`array is the claimed acceleration or meets the claimed acceleration elements.
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`So, turning to slide 27, Arbor has an expert supporting each of these
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`positions in the parallel proceeding and the positions are in the record. This
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`is Dr. Darveaux, I believe. His are in the record as Exhibit 1074, along with
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`Arbor’s prior briefing taking those positions, which are Exhibits 1072 and
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`1073, and the Board can see from the timeline that Arbor took these
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`positions after Xilinx filed the petitioner in the present cases.
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`And from the public docket, we can see that the District Court
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`accepted Arbor’s arguments, and the District Court’s claim construction
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`order is Exhibit 2005 in the 1570 IPR for the 035 patent, for example.
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`Now, if we turn to slide 30, I want to address the Board’s
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`construction and the recent Samsung 951 decision where the, quote,
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`functional to accelerate limitations were construed as, quote, a number of
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`vertical contacts distributed throughout the surface of and traversing the
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`memory die in a vertical direction, vias, to allow multiple short paths for
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`data transfer between the memory and processor.
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`And for clarity, we understand that when the Board wrote the word
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`processor in the Samsung 951 final written decision that the Board was
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`referencing the programmable array that is programmable as the processing
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`element that’s recited in some of the 951 claims, and that interpretation is
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`clear from the record, the claim language itself, and how the parties, you
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`know, interpreted the acceleration claim elements in that matter.
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`

`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
`
`
`
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`And what I’m saying here is that all the acceleration claims at issue
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`across the patents, there’s some programmable logic that is doing some
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`processing, and so I just wanted to flag that issue now for the Board so the
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`Board can avoid any ambiguity in the claim construction.
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`And so, for clarity, in the 951 patent, we understand the Board’s
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`construction to be a number of vertical contacts distributed throughout the
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`surface of and traversing the memory die in a vertical direction, vias, to
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`allow short paths for data transfer between the memory and programmable
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`array.
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`And in the 035 and 985 patent, we understand the Board’s
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`construction to be a number of vertical contacts distributed throughout the
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`surface of and traversing the memory die in a vertical direction, vias, to
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`allow multiple short paths for data transfer between the memory and field
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`programmable data array because those are the processing elements that are
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`referenced, but regardless of the way it’s stated, including if the Board keeps
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`its original processor language, the Zavracky-Chiricescu-Akasaka
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`combination provides that limitation.
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`Zavracky describes interlayer connections that provide for vertical
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`communication. Such communications, sorry, such connections, you can
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`see, can be placed anywhere on the die and therefore are not limited to
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`placement on the outer periphery.
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`Chiricescu further confirms that interpretation of Zavracky, stating
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`that Zavracky, quote, allows us to build chips with vertical metal
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`interconnections, i.e., interlayer vias, placed anywhere on the chip.
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`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
`
`
`
`
`And Akasaka teaches the exchange of signals between upper and
`
`lower active circuit layers through via poles in 3D integrated circuits, and
`
`that there can be tens of thousands of such connections.
`
`So, on slide 31, I’ve extracted here some of the acceleration
`
`teachings of Zavracky, Chiricescu, and Akasaka, and to read some of the
`
`quotes from these references, Zavracky’s approach accelerates
`
`communication between the dies and the chip by way of, quote, smaller
`
`delays and higher speed circuit performance. The arrangement results in
`
`reduced memory time, increasing the speed of the entire system.
`
`Chiricescu teaches significantly improved FPGA reconfiguration
`
`time, and Akasaka describes high-speed performance that is associated with
`
`shorter interconnection delay in parallel processing.
`
`And these are just some of the quotes from these references, and we,
`
`of course, go into more detail in our briefing, but the point here is that Xilinx
`
`shows that the combination teaches the claim elements under any reasonable
`
`construction, and that includes the Board’s construction of, quote, a number
`
`of vertical contacts distributed throughout the surface of and traversing the
`
`memory die in a vertical direction, vias, to allow multiple short paths for
`
`data transfer between the memory and processor or programmable array,
`
`field programmable data array. The point there is just the processing
`
`element.
`
`JUDGE EASTHOM: Mr. Shneidman, I was wondering what you
`
`think about -- there was some -- it seemed like the parties agreed to a certain
`
`extent in the 1021 and 1022 cases that because you have all of these vias that
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`

`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
`
`are short and also in parallel, they’re physically in parallel, that they enable
`
`
`
`parallel processing.
`
`Is that -- and so, although that’s not in the claim construction, it’s
`
`sort of part and parcel of what, I think, Patent Owner is arguing, that you
`
`need some kind of parallel processing or parallel data transfer to happen. Do
`
`you agree with that and do you think that you’ve shown that?
`
`MR. SHNEIDMAN: Yes, so the patent speaks of a parallelism in
`
`loading the configuration cells themselves if you look at where parallelism
`
`appears in the specification. You know, I understand the Patent Owner
`
`believes that it’s required to have parallel access, simultaneous parallel
`
`access and not just direct connections throughout the entire system really.
`
`You know, we have shown that. You know, our view is that we’ve
`
`shown all of the potential reasonable constructions here, but in particular, to
`
`the extent that parallelism and simultaneity of access is required, we detailed
`
`that in our Petitioner reply, for example, going through and explaining how,
`
`if parallelism is required in terms of simultaneity throughout the system,
`
`then that is shown by the prior art.
`
`Now, you know, from memory, I do want to recall that the patent
`
`speaks of being able to do loading of buffer cells, for example, as one
`
`example, while the FPGA is in operation, and so while the FPGA is in
`
`operation implies that there’s sort of some ticking going on, some additional
`
`advancement in clock cycles.
`
`So, you know, it’s certainly clear that there is direct connections
`
`required. I think Figure 3 versus Figure 5 shows that, but in terms of, you
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`

`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
`
`know, squaring, I know, you know, having read the transcript in the 1020
`
`
`
`and 1021, the parallelism is sort of assumed, and I suppose what we’re
`
`saying is under any construction, including the parallel construction, the art
`
`that we have put together in the petitions does show that.
`
`JUDGE EASTHOM: And do you agree that -- I think we made
`
`some findings, the Board did, in 1021 and 1022. A lot of it was in footnotes,
`
`some of it was, because it wasn’t totally an issue, but it seems like it’s
`
`rearing its head a little more here maybe, but it seems like -- I think Patent
`
`Owner agrees that bandwidth, increasing bandwidth is another way of saying
`
`parallel connections, but I don’t know how you feel about that or --
`
`MR. SHNEIDMAN: I think that’s a fairly fair characterization. Dr.
`
`Franzon testifies that the combination increases bandwidth, I think area wide
`
`interconnections such as taught by Akasaka, you know, and to jump ahead a
`
`little bit, for example, Trimberger in providing discussions of simultaneity
`
`and bit access. That really is getting to bandwidth. That’s getting to --
`
`JUDGE EASTHOM: I mean, I understand it’s dependent on the
`
`clock, right, according to, I think it was Dr. Chakrabarty in the 1021 and
`
`1029 hearings, but if the clock rate’s the same and you have more parallel
`
`connections, then the bandwidth goes up is the way I understand it.
`
`MR. SHNEIDMAN: I think that’s a fair statement, Your Honor.
`
`There a little bit of informality in the way some of these terms tend to be
`
`used in the art, and frankly, maybe a little sloppiness, but I believe that, you
`
`know, getting to bandwidth is a form of acceleration and increased
`
`bandwidth, that certainly if you can push more data through in one clock
`
`cycle, you can process that data faster.
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`

`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
`
`
`JUDGE EASTHOM: Okay, thank you.
`
`
`
`MR. SHNEIDMAN: All right, so unless there are further questions,
`
`I’d like to move to slide 38. Now, Arbor only did its analysis under its
`
`faulty wide configuration data port construction, and so our view is the
`
`response is really, frankly, nonresponsive. With that said, we rebutted
`
`each of Arbor’s attacks on this element anyway, and unless the Board has
`
`questions, I just want to highlight the second issue on this slide which is
`
`described at slide 40 because it’s a bigger concern in these proceedings.
`
`So, on slide 40, Arbor is not accurate in how it describes Xilinx’s
`
`expert’s testimony, and here on slide 40 is an example. At his deposition,
`
`Xilinx’s expert, Dr. Franzon, was asked about preloading memory cells in
`
`the context of the Trimberger reference. In other words, how does data get
`
`to the on-chip memory within the 3D chip in the first place?
`
`And Dr. Franzon, in his testimony, says the data comes from, quote,
`
`an off-chip memory. That is data that’s contained in the DRAM from
`
`outside of the 3D chip. That has nothing to do with the internals of the 3D
`
`chip. It has nothing to do with Chiricescu, and Arbor incorrectly cites this
`
`testimony to say that Dr. Franzon admitted something about Chiricescu and
`
`Chiricescu’s RLB BUS. He did not.
`
`The Board can confirm for itself by reference to the index of Dr.
`
`Franzon’s deposition transcript that Arbor did not ask a single question
`
`about Chiricescu in the transcript except warm-up questions to see if he was
`
`familiar with the reference, and the word RLB or RLB BUS is not
`
`mentioned once in the transcript. So, all of these supposed admissions on
`
`the left of the slide are just made up.
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`

`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
`
`
`
`
`On slide 41, we can see also that Arbor’s argument and criticism is
`
`factually incorrect. Specifically, Arbor argues that Chiricescu uses a narrow
`
`data port and does not use Zavracky’s interconnections for communication.
`
`It’s an odd argument because Chiricescu literally states that it uses
`
`Zavracky’s interlayer vias to connect the three separate layers and
`
`Chiricescu describes no other way of connecting the layers.
`
`More importantly, Xilinx is asserting a combination argument. That
`
`is even Zavracky provides, quote, a number of vertical contacts distributed
`
`throughout the surface of and traversing the memory die in a vertical
`
`direction, vias, to allow multiple short paths for data transfer between the
`
`memory and processing element, processor FPGA programmable array, and
`
`that teaching is further amplified by Chiricescu and Akasaka, so Arbor’s
`
`attacks are simply not correct and they are not attacking the relevant
`
`combination.
`
`So, in sum, our view is that the accelerate claims are taught by the
`
`combination, including under the Board’s construction issued last week in
`
`these terms. So, unless the Board has more questions on that, I’m going to
`
`switch gears to the other claims affected by the construction and the
`
`Samsung decisions involving the means plus function terms.
`
`For that, we want to go to slide 74. So, if you turn to slide 74, I want
`
`to discuss the one clock cycle means plus function limitations, and this is
`
`relevant only to the 226 patent.
`
`So, on slide 75, I show the means plus function claims at issue, and
`
`the limitations at dispute here are claim 13’s means for reconfiguring the
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`

`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
`
`programmable array within one clock cycle and claim 22’s means for
`
`
`
`updating the plurality of configuration logic box within one clock cycle.
`
`Now, as laid out in the papers, there is no dispute as to the function
`
`here for these claims. There is a dispute as to whether it is the
`
`corresponding structure for the functions of reconfiguring the programmable
`
`array within one clock cycle and updating the plurality of configuration logic
`
`cells within one clock cycle.
`
`So, if we move forward two slides to slide 77, the combination
`
`asserted here is Zavracky-Chiricescu-Akasaka, with the additional reference
`
`of Trimberger. Trimberger describes memory, quote, accessible so that the
`
`entire configuration of the FPGA can be changed in a single cycle.
`
`Now, on slide 78, Trimberger is describing memory as a memory
`
`plane which is comprised of cells that is instantaneously swapped to update
`
`programmable array configuration cells.
`
`On slide 79, first in the lower left, we see the description that the
`
`CLB configuration cells are connected to memory cells, and the
`
`configuration cells are part of the logic and interconnect array on the model
`
`shown on the right-hand side, which is Figure 1 of Trimberger. The memory
`
`cells are located in the plane on the configuration SRAM in the picture and
`
`there are 100,000 bit lines.
`
`Now, I’ll pause to note that this is similar to the connectivity taught
`
`in other references known to the POSITA. For example, Koyanagi also
`
`taught 10 to the 5 or 100,000 interconnections, and Akasaka taught tens of
`
`thousands of connections.
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`

`

`IPR2020-01567 (Patent: 7,126,214 B2)
`IPR2020-01568 (Patent: 7,282,951 B2)
`IPR2020-01570 (Patent: RE 42,035)
`IPR2020-01571 (Patent: 6,781,226 B2)
`
`
`
`
`So, one of the relevant teachings in Trimberger is the structure of
`
`how to connect the memory cells to the configuration logic cells so that the
`
`FPGA is configured in one clock cycle, and to quote from Dr. Franzon’s
`
`original report, Exhibit 1002 in all of the matters, which is paragraph 254,
`
`Trimberger teaches, quote, how to direct the connectivity permitted by
`
`Akasaka’s distributed contact points and Zavracky and Chiricescu’s teaching
`
`of contact points anywhere.
`
`JUDGE EASTHOM: Mr. Shneidman, are you arguing that the
`
`updated simultaneously, is that for all 100,000 bits on slide 79? You have a
`
`quote?
`
`MR. SHNEIDMAN: Yes, Your Honor, if I understand your
`
`question, you’ll see in the lower right --
`
`JUDGE EASTHOM: Yeah, okay, so that would be a parallel
`
`reconfiguration?
`
`MR. SHNEIDMAN: Correct, what’s happening is, okay, so if you
`
`see in the picture, there’s MC8 that’s highlighted in yellow on slide 79?
`
`JUDGE EASTHOM: Yes.
`
`MR. SHNEIDMAN: And that is one cell of many cells that is on a
`
`plane, one of these planes, and then what happens is in one clock cycle,
`
`there’s 100,000 of these blue, colored in blue bit lines that’s connecting the
`
`MC8 to the logic and interconnect array, and so what happens, as you can
`
`see in the lower right, the quote from Exhibit 1006, is when the device is
`
`flash reconfigured, and by flash, they mean quickly, all bits in the logic and
`
`interconnec