Paper 9
`Trials@uspto.gov
`Entered: June 14, 2021
`571-272-7822
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.,
`Petitioner,
`
` v.
`
`ARBOR GLOBAL STRATEGIES LLC,
` Patent Owner.
`
` IPR2021-00738
`Patent 6,781,226 B2
`
`
`
`
`
`
`
`
`
`
`
`Before KARL D. EASTHOM, BARBARA A. BENOIT, and
`SHARON FENICK, Administrative Patent Judges.
`
`FENICK, Administrative Patent Judge.
`
`
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`Granting Motion for Joinder
`35 U.S.C. § 315(c); 37 C.F.R. § 42.122
`
`
`Trials@uspto.gov
`Entered: June 14, 2021
`571-272-7822
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.,
`Petitioner,
`
` v.
`
`ARBOR GLOBAL STRATEGIES LLC,
` Patent Owner.
`
` IPR2021-00738
`Patent 6,781,226 B2
`
`
`
`
`
`
`
`
`
`
`
`Before KARL D. EASTHOM, BARBARA A. BENOIT, and
`SHARON FENICK, Administrative Patent Judges.
`
`FENICK, Administrative Patent Judge.
`
`
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`Granting Motion for Joinder
`35 U.S.C. § 315(c); 37 C.F.R. § 42.122
`
`
`
`
`
`
`
`
`
`IPR2021-00738
`Patent 6,781,226 B2
`
`
`On April 5, 2021, Taiwan Semiconductor Manufacturing Co.
`Ltd. (“Petitioner”) filed a Petition (Paper 1, “Pet.”) seeking inter partes
`review of claims 1–30 (the “challenged claims”) of U.S. Patent No.
`6,781,226 B2 (Ex. 1001, “the ’226 patent”). With the Petition, Petitioner
`filed a Motion for Joinder (Paper 3, “Motion” or “Mot.”) with Xilinx, Inc., v.
`Arbor Global Strategies LLC, IPR2020-01571 (the “Xilinx ’226 IPR”).
`Subsequently, during a conference call held on May 20, 2021, counsel for
`Patent Owner, Arbor Global Strategies LLC, confirmed that no opposition to
`the Motion had been filed and stated that no preliminary response to the
`Petition will be filed in view of representations that Petitioner made in its
`Motion. See Paper 8 (Order documenting the conference call).
`The Board has authority to determine whether to institute an inter
`partes review. See 35 U.S.C. § 314(b); 37 C.F.R. § 42.4(a) (2020). Under
`35 U.S.C. § 314(a), an inter partes review may not be authorized unless the
`information in the Petition and the Preliminary Response “shows that there
`is a reasonable likelihood that the petitioner would prevail with respect to at
`least 1 of the claims challenged in the petition.”
`For the reasons that follow, we institute an inter partes review as to
`the challenged claims of the ’226 patent on all grounds of unpatentability
`presented. We also grant Petitioner’s Motion.
`I. BACKGROUND
`A. Real Parties-in-Interest
`Petitioner identifies Taiwan Semiconductor Manufacturing Co. Ltd.
`and TSMC North America as real parties-in-interest. Pet. 69. Patent Owner
`identifies Arbor Global Strategies LLC. Paper 6, 1.
`
`2
`
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`IPR2021-00738
`Patent 6,781,226 B2
`
`
`B. Related Proceedings
`The parties identify Arbor Global Strategies LLC v. Samsung
`Electronics Co., Ltd. et al., 2:19-cv-00333-JRG-RSP (E.D. Tex.) and Arbor
`Global Strategies LLC v. Xilinx, Inc., 1:19-cv-1986-MN (D. Del.) as related
`proceedings. See Pet. 73; Paper 6, 1. In addition to the Xilinx ‘226 IPR to
`which Petitioner seeks joinder as a party, Patent Owner identifies two other
`pending inter partes reviews, IPR2020-01022 and IPR2021-00393, as
`pending challenges to the ’226 patent. Paper 6, 1.
`Concurrent with the instant Petition, Petitioner filed petitions
`challenging claims in three related patents, specifically IPR2021-00735
`challenging U.S. Patent No. 7,126,214 B2, IPR2021-00736 challenging U.S.
`Patent No. 7,282,951 B2, and IPR2021-00737 challenging U.S. Patent No.
`RE42,035 E.
`
`C. The ’226 Patent
`The ’226 patent describes a stack of integrated circuit (“IC”) die
`elements including a field programmable gate array (FPGA) on a die, a
`memory on a die, and a microprocessor on a die. Ex. 1001, code (57), Fig. 4.
`Multiple contacts traverse the thickness of the die elements of the stack to
`connect the gate array, memory, and microprocessor. Id. According to the
`’226 patent, this arrangement “allows for a significant acceleration in the
`sharing of data between the microprocessor and the FPGA element while
`advantageously increasing final assembly yield and concomitantly reducing
`final assembly cost.” Id.
`
`
`
`3
`
`
`
`
`
`IPR2021-00738
`Patent 6,781,226 B2
`Figure 4 follows:
`
`
`
`
`Figure 4 above depicts a stack of dies including FPGA die 68, memory die
`66, and microprocessor die 64, interconnected using contact holes 70. Id. at
`4:9–33.
`
`The ’226 patent explains that an FPGA provides known advantages as
`part of a “reconfigurable processor.” Id. at 1:19–35. Reconfiguring the
`FPGA gates alters the “hardware” of the combined “reconfigurable
`processor” (e.g., the processor and FPGA) making the processor faster than
`one that simply accesses memory (i.e., “the conventional ‘load/store’
`paradigm”) to run applications. See id. A “reconfigurable processor”
`provides a known benefit of flexibly providing the specific functional units
`needed for applications to be executed. See id.
`D. Illustrative Claims 1, 7, 13, and 22
`The Petition challenges independent claims 1, 7, 13, and 22 and claims
`2–6, 8–12, 14–21, and 23–30, which depend from one of the challenged
`4
`
`
`
`
`
`
`IPR2021-00738
`Patent 6,781,226 B2
`independent claims either directly or indirectly. Claims 1, 7, 13 and 22,
`
`reproduced below with bracketed numbering added for reference, illustrate
`the challenged claims at issue:
`1. A processor module comprising:
`[1.1] at least one field programmable gate array integrated circuit die
`element including a programmable array; and
`[1.2] at least one microprocessor integrated circuit die element stacked
`with and electrically coupled to said programmable array of said
`at least one field programmable gate array integrated circuit die
`element,
`[1.3] such that processing of data shared between the microprocessor
`and the field programmable gate array is accelerated.
`Ex. 1001, 6:16–26.
`7. A processor module comprising:
`[7.1] at least one field programmable gate array integrated circuit die
`element including a programmable array; and
`[7.2] at least one microprocessor integrated circuit die element stacked
`with and electrically coupled to said programmable array of said
`at least one field programmable gate array integrated circuit die
`element,
`[7.3] the at least one field programmable gate array integrated circuit
`die element being configured to provide test stimulus to the at
`least one microprocessor integrated circuit die element during
`manufacture and prior to completion of the module packaging.
`Ex. 1001, 6:45–57, Cert. of Corr.
`13. A processor module comprising:
`[13.1] at least a first integrated circuit die element including a
`programmable array;
`[13.2] at least a second integrated circuit die element including a
`processor stacked with and electrically coupled to said
`programmable array of said first integrated circuit die element;
`[13.3] at least a third integrated circuit die element including a memory
`stacked with and electrically coupled to said programmable
`
`
`
`5
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`IPR2021-00738
`Patent 6,781,226 B2
`array and said processor of said first and second integrated
`
`circuit die elements respectively; and
`[13.4] means for reconfiguring the programmable array within one
`clock cycle.
`
`Ex. 1001, 7:9–22.
`22. A processor module comprising:
`at least a first integrated circuit die element including a programmable
`array and a plurality of configuration logic cells;
`at least a second integrated circuit die element including a processor
`stacked with and electrically coupled to said programmable
`array of said first integrated circuit die element;
`at least a third integrated circuit die element including a memory
`stacked with and electrically coupled to said programmable
`array and said processor of said first and second integrated
`circuit die elements respectively; and
`[22.4] means for updating the plurality of configuration logic cells
`within one clock cycle.
`Ex. 1001, 8:4–17.
`The Asserted Grounds
`Petitioner challenges claims 1–30 of the ’226 patent on the following
`grounds (Pet. 2):
`
`Claims Challenged
`
`1–6
`
`35
`U.S.C. §
`1031
`
`References
`
`Zavracky,2 Chiricescu,3
`
`
`1 The Leahy-Smith America Invents Act (“AIA”), Pub. L. No. 112-29, 125
`Stat. 284, 287–88 (2011), amended 35 U.S.C. § 103. For purposes of
`institution, the ’226 patent contains a claim with an effective filing date before
`March 16, 2013 (the effective date of the relevant amendment), so the pre-AIA
`version of § 103 applies.
`2 Zavracky et al., US 5,656,548, issued Aug. 12, 1997. Ex. 1003.
`3 Silviu M. S. A. Chiricescu and M. Michael Vai, A Three-Dimensional FPGA
`with an Integrated Memory for In-Application Reconfiguration Data,
`Proceedings of the 1998 IEEE International Symposium on Circuits and
`6
`
`
`
`
`
`
`IPR2021-00738
`Patent 6,781,226 B2
`
`
`Claims Challenged
`
`7–12
`
`13–30
`
`35
`U.S.C. §
`
`103
`
`103
`
`References
`
`Akasaka4
`
`Zavracky, Chiricescu,
`Akasaka, Satoh5
`Zavracky, Chiricescu,
`Akasaka, Trimberger6
`
`Petitioner contends that each of the asserted references is prior art to each of
`the challenged claims. Pet. 1–2. Petitioner additionally relies on the
`Declaration of Dr. Paul Franzon. (Ex. 1002) in support of its contentions.
`
`II. ANALYSIS
`
`A. Institution of Inter Partes Review
`We instituted an inter partes review in the Xilinx ’226 IPR on all
`
`challenged claims and all asserted grounds of unpatentability. Xilinx ’226
`IPR, Paper 12. Petitioner here challenges the same claims and asserts the
`same grounds of unpatentability as those on which we instituted the Xilinx
`’226 IPR. Pet. 1; Mot. 1 (“The Petition was based on the identical grounds
`that form the basis for the pending inter partes review initiated by Xilinx,
`Inc., (‘Xilinx’) concerning the same patent, Case No. IPR2020-01571 (the
`
`
`Systems, May 1998, ISBN 0-7803-4455-3/98. Ex. 1004.
`4 Yoichi Akasaka, Three-Dimensional IC Trends, Proceedings of the IEEE,
`Vol. 74, Iss. 12, pp. 1703–1714, Dec. 1986, ISSN 0018-9219. Ex. 1005.
`5 Satoh, PCT App. Pub. No. WO00/62339, published Oct. 19, 2000. Ex. 1008
`(English translation).
`6 Steve Trimberger, Dean Carberry, Anders Johnson, and Jennifer Wong,
`A Time-Multiplexed FPGA, Proceedings of the 1997 IEEE International
`Symposium on Field-Programmable Custom Computing Machines, April
`1997, ISBN 0-8186-8159-4. Ex. 1006.
`7
`
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`
`IPR2021-00738
`Patent 6,781,226 B2
`‘Xilinx ’226 IPR’).” Petitioner also relies on the same declarant as did the
`
`petition in the Xilinx ’226 IPR. Mot. 4 (“The Petition asserts only grounds
`that the Board already instituted in the Xilinx ’226 IPR, supported by the
`same technical expert and the same testimony.”); compare Ex. 1002, with
`Xilinx ’226 IPR, Ex. 1002 (Declarations of Dr. Paul Franzon).
`Because the grounds of unpatentability in the instant Petition are
`identical to those in the Xilinx ’226 IPR, and for the same reasons stated in
`our Decision to Institute in the Xilinx ’226 IPR, we institute inter partes
`review in this proceeding on the grounds presented in the Petition. See
`Xilinx ’226 IPR Paper 20–50 (Analysis of challenges in Petition).
`B. Motion for Joinder
`Joinder in an inter partes review is subject to the provisions of
`35 U.S.C. § 315(c):
`(c) JOINDER.—If the Director institutes an inter partes review, the
`Director, in his or her discretion, may join as a party to that inter partes
`review any person who properly files a petition under section 311 that
`the Director, after receiving a preliminary response under section 313 or
`the expiration of the time for filing such a response, determines warrants
`the institution of an inter partes review under section 314.
`To join Petitioner to the instituted Xilinx ’226 IPR, the Board first
`determines whether the Petition “warrants” institution under § 314, which we
`determined above. See Facebook, Inc. v. Windy City Innovations, LLC, 973
`F.3d 1321, 1332 (Fed. Cir. 2020).
`The Board next determines whether to exercise “discretion to decide
`whether to ‘join as a party’ the joinder applicant,” who is the Petitioner in
`this proceeding. Id. Petitioner timely filed its Motion for Joinder on
`April 5, 2021, which was no later than one month after the institution of the
`Xilinx ’226 IPR on March 5, 2021. 37 C.F.R. § 42.122(b).
`As moving party, Petitioner bears the burden of proving that it is
`
`
`
`8
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`IPR2021-00738
`Patent 6,781,226 B2
`entitled to the requested relief. 37 C.F.R. § 42.20(c). A motion for joinder
`
`should (1) set forth the reasons joinder is appropriate; (2) identify any new
`grounds of unpatentability asserted in the petition; and (3) explain what
`impact (if any) joinder would have on the trial schedule for the existing
`review. See Kyocera Corp. v. SoftView, LLC, IPR2013-00004, Paper 15 at 4
`(PTAB Apr. 24, 2013).
`We determine that Petitioner has met its burden of showing that
`joinder is appropriate because, as set forth above, the Petition (1) is
`substantially identical to the petition in the Xilinx ’226 IPR, (2) contains the
`same grounds based on the same evidence, and (3) relies on the same
`declaration of Paul Franzon, Ph.D. (Ex. 1002). Mot. 1, 3, 4. Petitioner also
`represents that joinder will not impact the Xilinx ’226 IPR schedule. Mot. 1,
`3, 4–5; see, e.g., Mot. 5 (“Without any new issues present, there is no reason
`to delay or alter the trial schedule already present in the Xilinx IPR, and
`Petitioner explicitly consents to the existing trial schedule.”).
`Additionally, Petitioner represents that it is willing to accept a limited,
`“understudy role” to Xilinx (the original petitioner in the Xilinx ’226 IPR)
`such that Petitioner will only assume “an active role in the event Xilinx no
`longer is a party to these proceedings.” Mot. 1. Specifically, Petitioner
`represents that in its understudy role, it agrees that the following conditions
`will apply:
`(a) all filings by Petitioner in the joined proceeding be consolidated with
`the filings of Xilinx, and Xilinx will maintain full control over all such
`filings unless a filing solely concerns issues that do not involve Xilinx;
`
`(b) Petitioner shall not be permitted to raise any new grounds not already
`instituted by the Board, or introduce any argument or discovery not
`already introduced by Xilinx;
`
`(c) Petitioner shall be bound by any agreement between Patent Owner
`and Xilinx concerning discovery and/or depositions; []
`9
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`IPR2021-00738
`Patent 6,781,226 B2
`
`
`(d) Petitioner at deposition shall not receive any direct, cross
`examination or redirect time beyond that permitted for Samsung in this
`proceeding alone under either 37 C.F.R. § 42.53 or any agreement
`between Patent Owner and Xilinx[; and]
`
`(e) [i]f an oral hearing is requested and scheduled, Xilinx in the joined
`proceeding will designate attorney(s) to present a consolidated argument
`at the oral hearing.
`Mot. 6–7.
`Petitioner further represents that Xilinx does not oppose Petitioner’s
`motion to join the Xilinx ’226 IPR. Mot. 1.
`We determined above that the Petition warrants the institution of an
`inter partes review. Under these circumstances, we agree with Petitioner that
`joinder is appropriate and will not unduly impact the ongoing trial in the
`Xilinx ’226 IPR. We limit Petitioner’s participation in the Xilinx ’226 IPR
`proceeding, as follows: (1) Xilinx alone is responsible for all petitioner
`filings in the proceeding until such time that it is no longer an entity in the
`proceeding, and (2) Petitioner is bound by all filings by Xilinx in the
`proceeding, except for (a) filings regarding termination or settlement, and (b)
`filings where Petitioner receives permission to file an independent paper.
`Petitioner must obtain prior Board authorization to file any paper or take any
`action on its own in the proceeding, so long as Xilinx remains as a non-
`terminated petitioner in the proceeding. This arrangement promotes the just
`and efficient administration of the ongoing trial in the Xilinx ’226 IPR, and
`protects the interests of Xilinx as original petitioner in IPR2020-01571 and of
`Patent Owner.
`
`
`
`
`
`10
`
`
`
`
`
`IPR2021-00738
`Patent 6,781,226 B2
`
`
`III. CONCLUSION
`
`For the foregoing reasons, we institute inter partes review of the
`challenged claims of the ’226 patent based on the grounds of unpatentability
`set forth in the Petition. We grant Petitioner’s Motion for Joinder and join
`Petitioner to IPR2020-01571, with the limitations set forth herein.
`
`
`
`IV. ORDER
`
`Accordingly, it is
`ORDERED that pursuant to 35 U.S.C. § 314, inter partes review is
`instituted as to the challenged claims of the ’226 patent with respect to all
`grounds of unpatentability presented in the Petition;
`FURTHER ORDERED that, pursuant to 35 U.S.C. § 315(c) and
`37 C.F.R. § 42.122, Petitioner’s Motion for Joinder is granted, and Petitioner
`is joined as a petitioner in IPR2020-01571, subject to the above- described
`limitations on Petitioner’s participation in that proceeding;
`FURTHER ORDERED that the asserted grounds of unpatentability on
`which the Board instituted inter partes review in IPR2020-01571 are
`unchanged and remain the only instituted grounds;
`FURTHER ORDERED that the Scheduling Order in IPR2020-01571,
`and any modifications thereto, shall govern the schedule of the proceeding;
`FURTHER ORDERED that all further filings are to be made in
`IPR2020-01571;
`FURTHER ORDERED that the case caption in IPR2020-01571 for all
`further submissions shall be modified to add Taiwan Semiconductor
`Manufacturing Co. Ltd. as a named Petitioner, and to indicate by footnote the
`joinder of Petitioner to that proceeding, as indicated in the attached sample
`case caption; and
`
`
`
`11
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`IPR2021-00738
`Patent 6,781,226 B2
`FURTHER ORDERED that a copy of this Decision shall be entered
`
`into the record in IPR2020-01571.
`
`
`
`12
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`IPR2021-00738
`Patent 6,781,226 B2
`
`PETITIONER:
`James M. Glass
`Ziyong Li
`QUINN EMANUEL URQUHART & SULLIVAN LLP
`jimglass@quinnemanuel.com
`seanli@quinnemanuel.com
`
`PATENT OWNER:
`Jonathan S. Caplan
`James Hannah
`Jeffrey H. Price
`KRAMER LEVIN NAFTALIS & FRANKEL LLP
`jcaplan@kramerlevin.com
`jhannah@kramerlevin.com
`jprice@kramerlevin.com
`
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`IPR2021-00738
`Patent 6,781,226 B2
`
`
`Sample Case Caption
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`XILINX, INC. and
`TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.,
`Petitioner,
`
`v.
`
`ARBOR GLOBAL STRATEGIES, LLC,
`Patent Owner.
`
`IPR2020-015711
`Patent 6,781,226 B2
`
`1 Taiwan Semiconductor Manufacturing Co. Ltd. filed a petition in IPR2021-
`00738 and has been joined as a party to this proceeding.
`
`14
`
`
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