`
`IMPINJ, INC.,
`Petitioner
`v.
`NXP B.V.
`NXP B.V.
`Patent Owner
`Patent Owner
`
`
`
`IPR2020-01630
`IPR2020-01630
`U.S. Patent No. 6,680,523
`U.S. Patent No. 6,680,523
`
`NXP Exhibit
`2010
`N X P E xh
`i b i t 2 0 1 0
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`a VE EXHIBIT — umen EV IDE me
`
`
`
`Petitioner Did Not Demonstrate That Any Claim Is Unpatentable
`
`• Impinj failed to provide viable construction for “process control
`module.” P.O. Sur-Reply at 1-8.
`• Impinj failed to show that Yamaguchi anticipates or renders
`obvious any claim of the ’523 patent under NXP’s construction.
`P.O. Resp. at 14-31.
`• Impinj failed to show that Satya anticipates or renders obvious any
`claim of the ’523 patent under NXP’s construction. P.O. Resp. at
`31-51.
`• The Board previously rejected the combination of Yamaguchi and
`Satya, and Impinj has not provided any additional arguments for
`that Ground. P.O. Resp. at 52-54.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`2
`
`
`
`
`
`The ’523 Patent (“Schober”)
`The 523 Patent (“Schober )
`
`DEMONSTRATIVE EXHIBIT - NOT EVIDENCE
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`3
`
`
`
`U.S. Patent No. 6,680,523 (“Schober”)
`
`v2 United States Patent
`Schoberetal.
`
`(10) Patent No:
`(45) Date of Patent:
`
`US 6,680,523 B2
`Jan, 20, 2004
`
`USO06680523B2
`
`a2) United States Patent
`Schober et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,680,523 B2
`Jan. 20, 2004
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(54) SEMICONDUCTOR WAFER WITH PROCESS
`CONTROL MODULES
`
`(EP) woe eeeceeeecceeeeceeeeceeeeeeee enone 01890050
`
`(21) Appl. No.: 10/081,893
`
`(22)
`
`Filed:
`
`Feb. 21, 2002
`
`(65)
`
`Prior Publication Data
`
`US 2002/0117735 Al Aug. 29, 2002
`
`(30)
`
`Foreign Application Priority Data
`
`Feb. 27, 2001
`
`Ex. 1001.
`=eee
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`4
`
`
`
`Figures and Abstract of Schober
`
`Ex. 1001.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`5
`
`
`
`Schober – Claim 1
`
`Ex. 1001 at Figures 1, 2; Claim 1.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`6
`
`
`
`Schober – Claim 2
`
`Ex. 1001 at Figures 1, 2; Claim 2.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`7
`
`
`
`Schober – Claim 3
`
`Ex. 1001 at Figures 1, 2; Claim 3.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`8
`
`
`
`Schober – Claim 4
`
`Ex. 1001 at Figures 1, 2; Claim 4.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`9
`
`
`
`
`
`Claim Construction
`Claim Construction
`
`DEMONSTRATIVE EXHIBIT - NOT EVIDENCE
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`10
`
`
`
`Process Control Module
`
`Patent Owner’s Response at 6.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`11
`
`
`
`Support for Patent Owner’s Construction
`
`• The ’523 patent consistently describes the use of optical lithography for
`generating and testing semiconductor wafers and their process control modules.
`P.O. Resp. at 6.
`• The ’523 specification states that the function of the process control modules is
`to “detect or recognize flaws” during the semiconductor wafer fabrication
`process. P.O. Resp. at 11.
`• The prosecution history of the ’523 patent confirms that “process control
`modules” are tested during wafer fabrication. P.O. Resp. at 11.
`• The word “process” in the term “process control monitors” refers to the
`semiconductor wafer processing. P.O. Resp. at 12.
`• Technical literature at the time of the invention of the ’523 patent discusses use
`of process control as related to the semiconductor wafer fabrication process. P.O.
`Resp. at 13.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`12
`
`
`
`Petitioner Failed to Propose any Alternative Construction
`
`• According to Impinj, “[t]he terms of the claims would be well-understood
`by a POSITA in 2001 and, unless otherwise indicated, the ordinary
`meaning of such terms should be applied.” Pet. at 13.
`
`• According to Impinj, “Patent Owner’s proposed construction is
`inconsistent with the ordinary meaning of PCM.” Pet. Reply at 2.
`
`• According to Impinj, “Neither the specification nor prosecution history
`justify variance from the ordinary meaning.” Pet. Reply at 7.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`13
`
`
`
`Failure of Proof
`
`• It is not enough for Petitioner to show that Patent Owner’s
`construction is allegedly wrong. P.O. Sur-Reply at 5.
`• Petitioner’s burden is to show the unpatentability of the claims by
`a preponderance of evidence. P.O. Sur-Reply at 5.
`• Impinj cannot do that because it did not show how the claims are
`to be construed. P.O. Sur-Reply at 8-9.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`14
`
`
`
`Ground 1: Yamaguchi
`
`Impinj Failed to Show by a Preponderance of Evidence That Claims 1-4 Are
`Anticipated by or Obvious over Yamaguchi
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`15
`
`
`
`U.S. Patent No. 6,492,189 (“Yamaguchi”)
`
`ox United States Patent
`Yamaguchi
`
`io)
`
`(IP) ees eeccecceeeeceeeceeeceeeeeseu eens 11-318330 =ee heORe
`
`METHOD OF ARRANGING EXPOSED
`AREAS INCLUDING A LIMITED NUMBER
`OF TEST ELEMENT GROUP (TEG)
`REGIONS ON A SEMICONDUCTOR WAFER
`
`_eeee
`
`Patent No:
`e of Patent:
`
`US 6,492,189 BL
`Dee. 10, 2002
`
`a2) United States Patent
`Yamaguchi
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,492,189 B1
`Dec. 10, 2002
`
`(21) Appl. No.: 09/696,196
`
`(22)
`SELLY1 (30)
`
`Oct. 26, 2000
`Filed:
`Foreign Application Priority Data
`
`Nov. 9, 1999
`
`Ex. 1003.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`16
`
`
`
`Figure 7 and Abstract of Yamaguchi
`
`Ex. 1003 at Figure 7; Abstract; 6:25-27.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`17
`
`
`
`Yamaguchi – Figure 1
`
`TEG ≠ TEG pattern region
`
`Ex. 1003 at Figure 1; 6:11-12.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`18
`
`
`
`Only A Part Of The TEG Pattern Region Is Available For The TEGs
`
`Patent Owner’s Response at 24 (citing Ex. 1003 at Fig. 2)
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`19
`
`
`
`Yamaguchi Does Not Anticipate or Render Obvious
`Claims 1 -4 of Schober
`• The Board previously agreed that alignment marks of Yamaguchi are not
`“process control modules.” Inst. Decision at 14.
`• TEGs of Yamaguchi are not “process control modules.” P.O. Resp. at 17-19.
`• Yamaguchi does not disclose “each process control module (4) takes the place
`of at least one chip (5)” limitation. P.O. Resp. at 19-30.
`• Yamaguchi does not disclose “the process control modules (4) are situated at
`equal distances from each other with respect to two mutually perpendicular
`coordinate directions (7, 8)” (claim 2). P.O. Resp. at 31.
`• Yamaguchi does not disclose “a process control module (4) is present in each
`exposure field (2)” (claim 3). P.O. Resp. at 31.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`20
`
`
`
`Ground 2: Satya
`
`Impinj Failed to Show by a Preponderance of Evidence That Claims 1-4 Are
`Anticipated by or Obvious over Satya
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`21
`
`
`
`U.S. Patent No. 6,633,174 (“Satya”)
`
`uy United States Patent
`Satya et al.
`
`{ND 000Oa
`oe
`uo Patent No:
`US 6,633,174 BL
`(45) Date o
`Oct. 14, 2003
`
`a2) United States Patent
`Satya etal.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,633,174 Bl
`Oct. 14, 2003
`
`Apr. 18, 2000. =eee
`
`Related U.S. Application Data
`Provisional application No. 60/170,655, filed on Dec. 14,
`1999, and provisional application No. 60/198,464, filed on
`
`STEPPER TYPE TEST STRUCTURES AND
`METHODS FOR INSPECTION OF
`SEMICONDUCTOR INTEGRATED CIRCUITS
`
`Appl. No.: 09/648,093
`
`Filed:
`
`Aug. 25, 2000
`
`Ex. 1004.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`22
`
`
`
`Figure 3 and Abstract of Satya
`
`Ex. 1004 at Figure 3; Abstract.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`23
`
`
`
`Satya – Figures 4A and 4B
`
`Ex. 1004 at Figure 4A, 4B; 3:15-17.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`24
`
`
`
`Schober Describes Process Control Modules In The Corner Or In
`The Center Of The Exposure Field
`
`Patent Owner’s Response at 42 (citing Ex. 1001 at Fig. 2 modified)
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`25
`
`
`
`Satya Does Not Support The Assertion That Figure 4B
`Represents An Exposure Field
`
`Patent Owner’s Response at 49 (citing Ex. 1004 at Fig. 4B modified)
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`26
`
`
`
`Satya Does Not Anticipate or Render Obvious
`Claims 1 -4 of Schober
`• Test structures or test die of Satya are not the “process control modules.”
`Paper 20 at 32-38.
`
`• Satya does not disclose “process control modules.” Paper 20 at 38-39.
`
`• Satya does not disclose “the given areas are formed by the exposure fields
`(2).” Paper 20 at 39-45.
`
`• Satya does not disclose “exposure fields.” Paper 20 at 45-51.
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`27
`
`
`
`Ground 3: Combination of
`Yamaguchi and Satya
`
`Impinj Failed to Show by a Preponderance of Evidence That Claims 1-4 Are
`Anticipated by or Obvious over Yamaguchi and Satya
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`28
`
`
`
`Petitioner failed to meet its burden under Graham and
`KSR to support the legal conclusion of obviousness
`• According to the Board, “Patent Owner challenges this ground as lacking
`explanation of how and why a person of ordinary skill in the art would have
`combined the various elements of Yamaguchi and Satya. … We agree with
`Patent Owner.” Inst. Decision at 23.
`• The Board further “determine[d] that Petitioner has not demonstrated a
`reasonable likelihood of prevailing of showing that claims 1−4 would have
`been obvious over a combination of Yamaguchi and Satya.” Inst. Decision at
`24.
`• Petitioner's Reply included no further discussion of this Ground
`
`D E M O N S T R A T I V E E X H I B I T – N O T E V I D E N C E
`
`29
`
`
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