United States Patent (19)
`Nistler et al.
`
`54 USEABLE DROP-INSTRATEGY FOR
`ScoSé.LYSIS OF
`
`75 Inventors: John L. Nistler, Martindale, Tex.;
`Charles E. May, Gresham, Oreg;
`Kenneth J. Morrissey, Austin, Tex.
`73 Assignee: Advanced Micro Devices, Inc.,
`Sunnyvale, Calif.
`
`21 Appl. No.: 09/224,971
`22 Filed:
`Jan. 4, 1999
`6
`51) Int. Cl. ..................................................... H01L23/58
`52 U.S. Cl. ............................. 257/48; 257/786; 257/206
`58 Field of Search .............................. 257/48, 202, 204,
`257/206, 210, 786, 723, 724
`
`56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,467,400 8/1984 Stopper.
`4,479,088 10/1984 Stopper.
`4,517,659 5/1985 Chamberlain.
`4,920,454 4/1990 Stopper et al.
`SE 3.1994 Tazunoki et al. .
`2- - -a-
`f1995 Devereaux et al. .
`5,514,884 5/1996 Hively et al..
`5,648,661
`7/1997 Rostoker et al..
`5,654,588 8/1997 Dasse et al..
`
`
`
`USOO5990488A
`Patent Number:
`11
`(45) Date of Patent:
`
`5,990,488
`Nov. 23, 1999
`
`OTHER PUBLICATIONS
`Stanley Wolf and Richard N. Tauber; Silicon Processing for
`the VLSI Era, vol. 3. The Submicron MOSFET, pp.
`325-329; 1995.
`Primary Examiner. Sheila V. Clark
`Attorney, Agent, or Firm Timothy M. Honeycutt
`57
`ABSTRACT
`A Semiconductor wafer incorporating proceSS control moni
`tors and a method of incorporating the same are provided. In
`one aspect, the Semiconductor wafer has a plurality of fields
`formed in a pattern thereon that is Subdivided into n Zones
`and has a center point. The Semiconductor wafer is provided
`with a plurality of integrated circuits each of which is
`positioned in one of the plurality of fields. The semicon
`ductor wafer also includes a plurality of diagnostic inte
`grated circuits dispersed in a pattern. The pattern is Such that
`each of the plurality of diagnostic integrated circuits is
`positioned in one of the plurality fields, one of the plurality
`of diagnostic integrated circuits is positioned in each of the
`in Zones, and a circle of radius R from the center point will
`interSect at least one of the plurality of diagnostic integrated
`circuits where R is greater than or equal to the distance
`between the center point and the innermost of the plurality
`of diagnostic integrated circuits and less than or equal to the
`distance between the center point and the outermost of the
`plurality of diagnostic integrated circuits.
`
`21 Claims, 3 Drawing Sheets
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`U.S. Patent
`
`Nov. 23, 1999
`
`Sheet 1 of 3
`
`5.990,488
`
`14
`
`FIG, 1
`(PKIOR Art)
`
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`(prior Art)
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`U.S. Patent
`
`
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`U.S. Patent
`
`Nov. 23, 1999
`
`Sheet 3 of 3
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`5.990,488
`
`-84
`
`6OG
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`
`
`
`
`
`
`FIG. 5
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`1
`USEABLE DROP-IN STRATEGY FOR
`CORRECTELECTRICAL ANALYSIS OF
`SEMCONDUCTOR DEVICES
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`This invention relates generally to Semiconductor
`processing, and more particularly to Structure and method
`for implementing diagnostic integrated circuits on a Semi
`conductor wafer.
`2. Description of the Related Art
`Testing has been an integral component of Semiconductor
`processing Since the development of the earliest germanium
`based bipolar integrated circuits. The need for testing then
`and now stems from both engineering and economic con
`siderations. Circuit designers must be able to Verify that
`circuits designed on paper and Simulated on computer, work
`as intended when implemented in actual Silicon. Similarly,
`proceSS engineers must be able to track the behavior of the
`multitude of individual process StepS used to fabricate a
`given integrated circuit. From an economic Standpoint, it is
`critical for Semiconductor manufacturers to be able to
`quickly pinpoint the origin of unacceptable yields So that the
`circuit design or the fabrication process may be altered as
`necessary without needlessly wasting lots of wafers that may
`cost Several hundred thousand dollars or more.
`Electrical and process verification testing of most inte
`grated circuits is provided by test Structures that are incor
`porated into a Semiconductor wafer during the process of
`fabricating the various operational integrated circuits (e.g.,
`microprocessors, random access memories, etc.) thereon.
`The test structures are designed to provide electrical verifi
`cation test data on various components of the operational
`integrated circuits as well as verification of many of the
`myriad of process Steps performed during the fabrication of
`the operational integrated circuits. In modem test Structures,
`well over a hundred or more different types of parameters
`are routinely captured by the test Structures.
`Early test Structures consisted of individual die commonly
`known as process control monitors (“PCM") that were
`placed in various die locations acroSS the face of a given
`wafer and fabricated in concert with the Surrounding opera
`tional integrated circuits. This type of test Structure prevailed
`throughout the period of Semiconductor manufacturer when
`1x reticles were used for direct print or contact printing or
`projection Scanning of Semiconductor devices. Early in the
`last decade, the Semiconductor industry transitioned away
`from 1x reticle processing in favor of lithographic Stepping.
`AS a consequence, PCMS as test Structures were largely
`abandoned in favor of scribe line monitors ("SLM”).
`There are Several disadvantages associated with conven
`tional structures and methods for implementing PCMs and
`SLMs. In the conventional design and fabrication of PCMs,
`little attention has been paid to the tailoring of the configu
`ration of a given PCM relative to Surrounding operational
`integrated circuits or the particular dispersal of PCMS acroSS
`the face of a given wafer. Manufacturing experience has
`demonstrated that the differences in the Structural densities
`of the PCM and the surrounding operational integrated
`circuits can significantly degrade the yield of those opera
`tional integrated circuits that do Surround a particular PCM.
`The differential structural density between a given PCM and
`the operational integrated circuits that Surround it impacts
`the behavior of various etch and polish Steps that are
`performed on the wafer. A given conventional PCM typi
`cally has a much lower Structural density, that is, number
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`and/or size of physical Structures, e.g. gates, metallization
`lines, isolation Structures, etc. per unit area than the Sur
`rounding operational integrated circuits, which typically
`have many more circuit devices and Structures per unit area.
`AS a result, etchants and polish Solvents may be more
`aggressively consumed by the leSS Structurally dense areas
`in the PCM than in the Surrounding operational integrated
`circuits, resulting in inadequate etching and/or polishing of
`certain Structures in the operational integrated circuits. The
`problem of differential structural density is further com
`pounded by the fact that the die borders for conventional
`PCMs are routinely much larger than the die borders for the
`Surrounding operational integrated circuits.
`Conventional SLMs do not present the same types of
`yield problems associated with conventional PCMs.
`However, conventional SLMs often cannot provide suffi
`cient electrical data. The problem is primarily one of pack
`ing density. SLMS are, as the name implies, fabricated in the
`Scribe lines. Space is accordingly limited. AS die sizes have
`increased to accommodate more complex circuits, the num
`ber of different test parameters and thus SLMs that are
`required has increased proportionally. However, it is fre
`quently difficult to pack the requisite number of SLMs into
`the confined Spaces of the Scribe lines. Thus, compromises
`in the amount of date gathered must be made.
`Another short coming common to both conventional
`PCM and SLM techniques is the propensity to inadequately
`capture data on certain types of process variations that can
`propagate at various locations on a given wafer. ProceSS
`variations can occur during many of the Scores of proceSS
`Steps performed on a wafer during integrated circuit manu
`facture. Many of these are due to the dynamics of heat
`transfer across a flat disk. For example, during the formation
`of a thermal oxide layer on a given wafer, a band or ring of
`the thermal oxide may develop with a significant variation
`from the anticipated nominal thickness. The band itself may
`have a uniform thickness that deviates from the anticipated
`nominal thickness of the rest of the film or may exhibit a
`gradient. In either event, if the band of variable thickness
`does not form over one of the appropriate test Structures
`fabricated on the wafer, the extent and impact of the area of
`process variation may not be adequately characterized So
`that its origin may be determined and appropriate modifi
`cations to the proceSS flow may be made to eliminate it.
`Some conventional process flows avoid the problem of
`degraded yield due to the impact of PCM fabrication on
`adjacent operational integrated circuits by utilizing dedi
`cated test wafers upon which only test Structures are fabri
`cated. While this technique avoids the aforementioned yield
`problems, data acquired from dedicated test waferS does not
`necessarily correlate well with the behavior of the electrical
`circuits and the processes used to form them on actual
`production wafers.
`The present invention is directed to overcoming or reduc
`ing the effects of one or more of the foregoing disadvan
`tageS.
`
`SUMMARY OF THE INVENTION
`In accordance with one aspect of the present invention, a
`semiconductor wafer that has a plurality of fields formed in
`a pattern thereon that is Subdivided into n Zones and has a
`center point is provided. The Semiconductor wafer includes
`a plurality of integrated circuits each of which is positioned
`in one of the plurality of fields. The semiconductor wafer
`also includes a plurality of diagnostic integrated circuits
`dispersed in a pattern. The pattern is Such that each of the
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`plurality of diagnostic integrated circuits is positioned in one
`of the plurality fields, one of the plurality of diagnostic
`integrated circuits is positioned in each of the n Zones, and
`a circle of radius R from the center point will interSect at
`least one of the plurality of diagnostic integrated circuits
`where R is greater than or equal to the distance between the
`center point and the innermost of the plurality of diagnostic
`integrated circuits and less than or equal to the distance
`between the center point and the Outermost of the plurality
`of diagnostic integrated circuits.
`In accordance with another aspect of the present
`invention, a Semiconductor wafer is provided that includes
`a plurality of interSecting Scribe lines that define a plurality
`of fields on the semiconductor wafer. A plurality of inte
`grated circuits is provided where each of the plurality of
`integrated circuits being positioned in one of the plurality of
`fields. A plurality of diagnostic integrated circuits is also
`provided. Each of the plurality of diagnostic integrated
`circuits is positioned in one of the plurality of fields and
`surrounded by a border that has a plurality of inactivated
`circuit devices that have Substantially the same layout as a
`corresponding plurality of active circuit devices in one of the
`plurality of integrated circuits.
`In accordance with another aspect of the present
`invention, a Semiconductor wafer that has a plurality of
`fields formed in a pattern thereon that is subdivided into
`Seven Zones and has a center point is provided. The Semi
`conductor wafer includes a plurality of integrated circuits.
`Each of the plurality of integrated circuits is positioned in
`one of the plurality of fields. A plurality of diagnostic
`integrated circuits is also included. Each of the plurality of
`diagnostic integrated circuits is positioned in one of the
`plurality of fields and Surrounded by a border. The border
`has a plurality of inactivated circuit devices having Substan
`tially the same layout as a corresponding plurality of active
`circuit devices in one of the plurality of integrated circuits.
`The plurality of diagnostic integrated circuits is dispersed in
`a pattern Such that one of the pluralities of diagnostic
`integrated circuits is positioned in each of the Seven Zones,
`and a circle of radius R from the center point will interSect
`at least one of the pluralities of diagnostic integrated circuits
`where R is greater than or equal to the distance between the
`center point and the innermost of the plurality of diagnostic
`integrated circuits and less than or equal to the distance
`between the center point and the Outermost of the plurality
`of diagnostic integrated circuits.
`In accordance with another aspect of the present
`invention, a method of fabricating a diagnostic integrated
`circuit on a Semiconductor wafer that has a plurality of fields
`patterned thereon with a center point is provided. The
`method includes the Steps forming an integrated circuit in
`one of the plurality of fields and a diagnostic integrated
`circuit in another of the plurality of fields positioned adja
`cent to the integrated circuit. The diagnostic integrated
`circuit has a border that has a plurality of inactivated circuit
`devices having Substantially the Same layout as a corre
`sponding plurality of active circuit devices in one of the
`plurality of integrated circuits.
`In accordance with another aspect of the present
`invention, a method of fabricating a plurality of diagnostic
`integrated circuits on a Semiconductor wafer that have a
`plurality of fields patterned thereon with a center point is
`provided. The method includes the steps of Subdividing the
`pattern of fields into n Zones and forming a plurality of
`integrated circuits, each of which is positioned in one of the
`plurality of fields. A plurality of diagnostic integrated cir
`cuits are formed. Each of the plurality of diagnostic inte
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`grated circuits is positioned in one of the plurality of fields
`and is Surrounded by a border having a plurality of inacti
`Vated circuit devices that has Substantially the same layout
`as a corresponding plurality of active circuit devices in one
`of the plurality of integrated circuits. The plurality of
`diagnostic integrated circuits are dispersed in a pattern
`whereby one of the plurality of diagnostic integrated circuits
`is positioned in each of the n Zones, and a circle of radius R
`from the center point will interSect at least one of the
`plurality of diagnostic integrated circuits where R is greater
`than or equal to the distance between the center point and the
`innermost of the plurality of diagnostic integrated circuits
`and less than or equal to the distance between the center
`point and the outermost of the plurality of diagnostic inte
`grated circuits.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The foregoing and other advantages of the invention will
`become apparent upon reading the following detailed
`description and upon reference to the drawings in which:
`FIG. 1 is a plan view of an exemplary conventional
`Semiconductor wafer;
`FIG. 2 is a highly magnified plan view of side-by-side
`fields of the semiconductor wafer depicted in FIG. 1 show
`ing pairs of operational integrated circuits and typical con
`ventional PCMs and SLMs;
`FIG. 3 is a plan view of an exemplary embodiment of a
`Semiconductor wafer incorporating a Selected portion of the
`fields patterned thereon dedicated to diagnostic integrated
`circuits and dispersed in a preselected pattern in accordance
`with the present invention;
`FIG. 4 is a highly magnified plan view of two side-by-side
`fields depicted in FIG. 3; and
`FIG. 5 is a plan view like FIG. 3, but highly simplified to
`reveal the dispersal pattern of the fields dedicated to diag
`nostic integrated circuit implementation in accordance with
`the present invention.
`
`DETAILED DESCRIPTION OF SPECIFIC
`EMBODIMENTS
`In the drawings described below, reference numerals are
`generally repeated where identical elements appear in more
`than one figure. Turning now to the drawings, FIGS. 1 and
`Show, respectively, a plan view of an exemplary conven
`tional Semiconductor wafer 10, and a highly magnified plan
`of a selected portion of the wafer 10 depicted in FIG. 1.
`FIGS. 1 and 2 are provided to illustrate two common types
`of conventional test devices used for electrical and process
`verification of semiconductor wafers. The wafer 10 includes
`a primary fiat 12 and a crown 14 positioned in opposition to
`the flat 12. A plurality of interSecting horizontal and vertical
`scribe lines 16 and 18 delineate and define a plurality of
`fields, three of which are designated 20a, 20b and 20c. The
`structure of the fields 20a, 20b and 20 in general may be
`understood by referring now also to FIG.2, which is a highly
`magnified plan view of the fields 20a and 20b. Two opera
`tional die 22 are positioned in the field 20a. Two test die 24
`are positioned in the field 20b. The operational die 22
`contain respective pluralities of circuit devices that are
`shown schematically and designated 26. The test die 24
`contain respective pluralities of circuit devices, which are
`Schematically represented and designated 28. Note that the
`Structural density, that is, the number of Structural features,
`Such as gates, metal lines, etc. per unit area is much greater
`for the die 22 than for the test die 24. This is a common
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`outcome in conventional fabrication of test die Since modem
`integrated circuits frequently contain millions of individual
`circuit devices whereas process control monitors or test die
`frequently contain Substantially fewer circuit devices as
`these types of test circuits require fewer devices to imple
`ment their particular logic functions.
`A pair of exemplary conventional Scribe line monitors
`(“SLMs”)30 and 32 are also depicted in FIG. 2. The SLMs
`30 and 32 are typically discrete devices that are fabricated in
`the scribe lines 16 and/or 18 during the fabrication of the die
`22 and/or the test die 28. SLMs, such as those depicted, are
`much more frequently incorporated into modern Semicon
`ductor wafers than the test die 24. A typical conventional
`wafer may contain hundreds or thousands of such SLMs.
`FIGS. 1 and 2 illustrate Some of the difficulties associated
`with conventional methods and devices for obtaining elec
`trical performance and process Verification data from a given
`wafer. AS noted above, process variations are an inevitable
`outcome of the multitudes of different material growth,
`deposition, removal and heating Steps that go into the
`fabrication of integrated circuits on a wafer. Two exemplary
`types Stemming from the dynamics of transferring heat to
`the wafer 10 will now be described. The shaded area 34 on
`the wafer 10 extending from the crown 14 downward to a
`point above the approximate center of the wafer 10 repre
`Sents an area of the wafer 10 that experienced a thickneSS
`gradient in the thickness of a particular layer formed on the
`wafer 10 during the processing of the various die 22 and test
`die 24 thereon. The shaded area 34 may represent, for
`example, a portion of a thermally grown oxide layer. The
`formation of the area of thickness variation 34 is the result
`of uneven heating of the wafer 10 during thermal processing.
`In almost all conventional thermal processes, wafers are
`inserted into heating chamber, Such as a rapid thermal anneal
`(“RTA') chamber or diffusion tube furnace, crown first, that
`is, by inserting the wafer 10 with the crown 14 entering the
`furnace first. As a result, the portion of the wafer 10 at and
`near the crown 14 is Subjected to high temperature for a
`Slightly longer period of time than the portions of the wafer
`10 nearer the primary flat 12. Although the entire wafer 10
`quickly assumes a relatively uniform temperature, the con
`vective and radiative heat transfer from the furnace to the
`wafer 10 is not fast enough to compensate for the initial and
`slightly longer heating of the portion of the wafer 10 near the
`crown 14. As a result, the area 34 will have a slightly larger
`thickness than the portion of the thermally grown oxide
`outside the area 34. The thickness of the area 34 will be
`directionally dependent, that is, thickest at the crown 14 and
`decreasing to a nominal thickness at the border 36 between
`the affected area 34 and the remainder of the wafer 10.
`Another phenomenon that may occur is the establishment
`of a ring or band 38 in a film formed on the wafer 10. The
`film may be the aforementioned thermal oxide or another
`type of material. The ring 38 constitutes an area of the film
`that deviates in properties from the expected norm for the
`film. The deviation along the width of the ring 38 may be
`uniform or directional dependent. The establishment of the
`ring 38 is a product of the physics of conductive heat transfer
`acroSS a flat disc in the presence of the relatively ubiquitous
`application of convective and radiative heat transfer in a
`typical RTA or furnace process. The width and position of
`the band 38 depend upon a large number of factors, Such as
`the type of thermal process involved, and the composition of
`the wafer 10, to name just a few. The band 38 may or may
`not impact the ultimate yield of the wafer 10.
`From a quality control Standpoint, it is highly desirable to
`be able to accurately determine the extent and effect of the
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`areas of Significant proceSS Variation, Such as the area 34 and
`the band 38. Note, however, that the test die 24 in the field
`20b are not positioned within either of the areas of process
`variation 34 or 38. Accordingly, those test structures 24 will
`not generate test data on the areas of process variation 34
`and 38. Indeed, the effect of the band 38 may go completely
`undetected unless the band 38 happens to form over one of
`the test structures 24 on the wafer 10. In conventional
`fabrication, this occurrence may be largely a matter of
`chance. Similarly, if no test Structures 24 are implemented in
`any of the fields positioned within the area of process
`variation 34, the effect of the area of process variation 34
`may not be adequately interpreted and a remedy, if called
`for, may be difficult to ascertain.
`Two other problems stem from the conventional method
`of fabricating PCMs, such as the test die 24, that can
`Significantly impact the yield of die that Surround the test die
`24, Such as the die 22. AS noted above, the Structural
`densities of the die 22 are significantly greater than the
`structural densities of the test die 24. As a result, the field
`20b may absorb much more of the various processing
`materials that are exposed to the wafer 10 during a given
`processing Step, Such as etchants, chemical-mechanical
`polishing (“CMP") solvents or the like. As a result, various
`layerS on the actual operational die 22 may be either
`inadequately formed or inadequately removed due to the
`excessive consumption of etchants, Solvents, etc. by the
`much high structural density test die 24. The problem is most
`acute near the Outer edges of the operational die adjacent the
`test die 24. Presently, little effort is made in conventional
`processing to layout and dimension test die So that the
`Structural densities of test die match the Structural densities
`of Surrounding operational die.
`An exemplary Structure and method for incorporating
`drop-in PCMs into a semiconductor wafer may be under
`stood by referring now to FIGS. 3, 4 and 5. As described in
`detail below, the apparatus and method in accordance with
`the present invention alleviate the difficulty of accurately
`obtaining diagnostic data for wafers exhibiting areas of
`Significant process variation as shown in FIGS. 1 and 2, as
`well as the yield problems associated with the conventional
`fabrication of PCMs. FIG. 3 depicts a plan view of an
`exemplary semiconductor wafer 40 that is provided with a
`primary flat 42 and an oppositely disposed crown 44. The
`wafer 40 may be composed of a variety of semiconductor
`materials, Such as Silicon, germanium or the like.
`Alternatively, the wafer 40 may be a silicon-on insulator,
`Such as Silicon-on-Sapphire or the like. In the embodiment
`illustrated, the wafer 40 is a composite structure of a base
`Substrate of lightly doped Silicon and an overlying blanket
`epitaxially grown Silicon layer. To facilitate the illustration
`of various structures on the wafer 40, an x-y axis 46 is shown
`with a x-axis 48 and a y-axis 50. A first plurality of scribe
`lines 52 and a second plurality of scribe lines 54 intersecting
`the first plurality of scribe lines 52, are patterned in the
`surface of the wafer 40 using well-known techniques for
`establishing scribe lines. The scribe lines 52 are disposed in
`a generally parallel relation to the X-axis 48 and the Scribe
`lines 54 are positioned in a generally parallel relation to the
`y-axis 50. The intersecting pluralities of scribe lines 52 and
`54 delineate and define a plurality of fields 56. Non
`orthogonal intersection of the scribe lines 52 and 54 is
`possible.
`Four of the fields, designated 58a, 58b, 58c and 58d are
`Set aside for the implementation of alignment markers to
`facilitate the alignment of various optical equipment used to
`process the wafer 40. Eight of the fields designated 60a, 60b,
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`60c, 60d, 60e, 60?, 60g and 60h are selected for the imple
`mentation of diagnostic integrated circuits to be formed
`thereon. The remaining fields, designated 56, are Set aside
`for the implementation of operational integrated circuits.
`The detailed structure of the field 60a and an adjacent
`field 56 may be understood by referring now to FIG. 4,
`which is a highly magnified plan view of the fields 56 and
`60a. The structures of the fields 60a and 56 shown in FIG.
`4 are respectively illustrative of the fields 56 and the fields
`60b, 60c, 60d, 60e, 60?, 60g and 60h. Two integrated circuits
`62 are implemented in the field 56. Each of the integrated
`circuits 62 includes a large number of individual circuit
`devices that are depicted Schematically and designated 63.
`The integrated circuits 62 may be virtually any type of
`integrated circuit fabricated in Semiconductor processing,
`Such as, for example, microprocessors, memory circuits, or
`codecs, to name just a few. Two diagnostic integrated
`circuits 64 are implemented in the field 60a. Each of the
`diagnostic integrated circuits 64 includes a plurality of
`circuit devices that are Schematically represented and des
`ignated 65. The diagnostic integrated circuits 64 are advan
`tageously implemented as PCMs that are fabricated in
`concert with the processing to fabricate the integrated cir
`cuits 62. The Selection of Specific types of circuits for
`implementation in the diagnostic integrated circuits 64 is
`largely a matter of design discretion. For example, the
`diagnostic integrated circuits 64 may include an SRAM
`module, an electroStatic discharge test circuit, capacitors and
`resistors, transistor Structures and various Sense amplifiers.
`The skilled artisan will appreciate that the number of inte
`grated circuits, operational or diagnostic, implemented on a
`given field is largely a matter of design discretion. For
`example, a single integrated circuit may be implemented per
`field or a plurality of integrated circuits as desired.
`The aforementioned problems of low yields due to the
`differences in Structural density are alleviated in the Struc
`ture of the present invention by fabricating the diagnostic
`integrated circuits 64 with Structural densities that are
`approximately equal to the Structural density of each of the
`integrated circuits 62. Achieving parity between the Struc
`tural densities of the integrated circuits 62 and the adjacent
`diagnostic integrated circuits 64 is a relatively Straightfor
`ward matter where the diagnostic integrated circuits 64 will
`have approximately the Same number of circuit devices as
`the integrated circuits 62. However, where the diagnostic
`integrated circuits 62 will not necessarily be fabricated with
`the same number or configuration of circuit devices as the
`integrated circuits 62, parity in Structural density may still be
`achieved by fabricating inactive circuit structures into the
`diagnostic integrated circuits 64 that, while not necessarily
`providing electronic function in the finished diagnostic
`integrated circuits 64, will nevertheless provide for a more
`balanced reaction between various etchants, Solvents, etc.
`and the various films, layerS and Structures that are Simul
`taneously processed on the integrated circuits 62 and the
`adjacent diagnostic integrated circuits 64.
`The latter of the two aforementioned techniques is illus
`trated in FIG. 4. Each of the diagnostic integrated circuits 64
`is surrounded by a die border 66 that consists of a duplica
`tion of the circuit devices implemented in the portion 67 of
`the integrated circuit 62 that is positioned outside the dashed
`rectangle 68. The layout of the die borders 66 is determined
`by taking the layout of one of the integrated circuits 62 and
`digitally blanking out the portion 69 of the circuit devices
`thereof positioned inside the dashed rectangle 68 using a
`layout tool. Any partial polygons, dangling interconnects or
`other partial Structures of the portion 67 remaining after the
`
`45
`
`50
`
`55
`
`60
`
`65
`
`8
`portion 69 is digitally blanked out are then cleaned up, that
`is, tied off or otherwise eliminated digitally using the layout
`tool. The goal of the cleanup is to avoid any Structures that
`could short or otherwise affect the performance of the
`diagnostic integrated circuits 64. After the digital cleanup
`step, the layout data for the portion 67 is then added to the
`layout data for each of the diagnostic integrated circuits 64.
`When the layout data for the diagnostic integrated circuits
`64 is transferred to reticles and ultimately to silicon, the
`layout data for the portion 67 will be implemented as the die
`borders 66. The diagnostic integrated circuits 64 are,
`themselves, implemented in the Spaces within the die bor
`derS 66. In this way, the Structural densities of the diagnostic
`integrated circuits 64, particularly in the die borders 66, will
`closely approximate the Structural densities of the Surround
`ing integrated circuits 62.
`The width, W., of the die borders 66 is selected to ensure
`Sufficient parity in the Structural densities of adjacent inte
`grated circuits, particularly near the various Scribe lines,
`such as the lines 52 and 54. Appropriate values for W will
`depend on a number of factors, Such as the types, sizes, and
`shapes of the operational and diagnostic integrated circuits
`and Scribe lines, and the minimum geometry of the prevail
`ing lithographic patterning technology.
`In order to ensure that the effects of proceSS Variations,
`such as those depicted in FIG. 1, are detected by the
`diagnostic integrated circuits 64, the diagnostic integrated
`circuits 64 and their corresponding fields 60a, 60b, 60c, 60d,
`60e, 60?, 60g and 60h are dispersed in a pattern as shown in
`FIG. 3. The pattern is selected by first subdividing the
`plurality of fields 56, 58a, 58b, 58c and 58d and 60a, 60b,
`60c, 60d, 60e, 60?, 60g and 60h into n zones where n is an
`integer. The zones, designated 70, 72, 74,76, 78, 80 and 82,
`may be best seen by referring now also to FIG. 5, which is
`a plan vi