(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2006/0161452 A1
`(43) Pub. Date:
`Jul. 20, 2006
`Hess
`
`US 2006O161452A1
`
`(54)
`
`(75)
`
`(73)
`(21)
`(22)
`
`(63)
`
`(60)
`
`COMPUTER-IMPLEMENTED METHODS,
`PROCESSORS, AND SYSTEMS FOR
`CREATING AWAFER FABRICATION
`PROCESS
`
`Inventor: Carl Hess, Los Altos, CA (US)
`Correspondence Address:
`DAFFER MCDANIEL, LLP
`P.O. BOX 684908
`AUSTIN, TX 78768 (US)
`Assignee: KLA-Tencor Technologies Corp.
`
`Appl. No.:
`
`11/374,710
`
`Filed:
`
`Mar. 14, 2006
`
`Related U.S. Application Data
`Continuation-in-part of application No. 11/048,630,
`filed on Jan. 31, 2005.
`Provisional application No. 60/540,031, filed on Jan.
`29, 2004.
`
`Publication Classification
`
`(51) Int. Cl.
`G06Q 99/00
`G07G I/00
`G06F 7/30
`
`(2006.01)
`(2006.01)
`(2006.01)
`
`(52) U.S. Cl. ................................................... 705/1: 705/10
`
`(57)
`
`ABSTRACT
`
`Computer-implemented methods, processors, and systems
`for creating a wafer fabrication process are provided. One
`computer-implemented method includes determining indi
`vidual error budgets for different parameters of the wafer
`fabrication process based on an overall error budget for the
`wafer fabrication process and simulated images that illus
`trate how reticle design data will be printed on a wafer at
`different values of the different parameters. The method also
`includes creating the wafer fabrication process based on the
`overall error budget and the individual error budgets.
`
`10
`Design
`Circuit -
`
`Verify
`Design
`
`
`
`14
`
`
`
`20
`
`--> AddRETs
`
`22
`
`Verify
`
`24
`
`Fai
`
`Pass
`
`3
`Scrap Mask,
`Respin
`
`No
`
`46
`
`Repairable
`
`Yes
`
`Wafers
`
`
`
`42
`
`Pass
`
`Release to
`Production
`
`48
`
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`

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`Patent Application Publication Jul. 20, 2006 Sheet 1 of 11
`
`US 2006/O161452 A1
`
`Design
`
`1O
`
`Make
`Mask
`
`28
`
`Verify
`Design
`
`12
`
`Verify
`
`30
`
`Repair
`
`36
`
`Yes
`.
`(e. Repairable?
`
`b
`
`
`
`
`
`
`
`N
`O
`
`
`
`8 3
`Scrap Mask,
`Respin
`
`NO
`
`
`
`4
`
`1.
`Repairable
`
`Yes
`
`Release to
`Production
`
`48
`
`(e) 14
`
`Pass
`
`Layout
`
`16
`
`Verify
`Layout
`
`18
`
`(e) 20
`
`Pass
`
`Add RETS
`
`22
`
`Verify
`Decoration
`
`24
`
`26
`Pass
`
`Fig. 1
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`Patent Application Publication Jul. 20, 2006 Sheet 2 of 11
`
`US 2006/O161452 A1
`
`Make
`Mask
`
`Verify
`Mask
`
`28
`
`30
`
`
`
`PaSS
`
`Print
`Wafers
`
`40
`
`Verify
`Wafers
`
`Repair
`Mask
`
`36
`
`eS Y
`
`3.
`
`Repairable?
`
`NO
`
`38
`8
`Scrap Mask,
`Respin
`
`
`
`
`
`NO
`
`Repairable?
`
`4
`
`Yes
`
`Pass
`
`Release to
`Production
`
`48
`
`Design
`Circuit
`
`Verify
`Design
`
`PaSS
`
`LayOut
`Circuit
`
`Verify
`LayOut
`
`10
`
`12
`
`- 14
`
`16
`
`18
`
`2O
`
`PaSS
`
`Add RETS
`
`22
`
`
`
`Verify
`Decoration,
`VPWO
`
`50
`
`Fig. 2
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`Patent Application Publication Jul. 20, 2006 Sheet 3 of 11
`
`US 2006/O161452 A1
`
`Synthesis
`54
`
`
`
`
`
`
`
`Histo
`ry
`64
`
`Creation of Reticle
`Design Data
`62
`
`
`
`
`
`Charact
`eristics
`56
`
`
`
`Logical
`Verification
`66
`
`Critical Paths 58
`
`Critical Features
`68
`
`Calibration
`Data
`72
`
`
`
`-
`OPC DeCoration
`70
`
`Physical
`Verification
`74
`
`Critical OPC 76
`
`EPE Tolerance
`78
`
`v. O
`
`Smart VPWO 82
`Critical OPC 84.
`
`Calibration
`Data
`88
`
`Calibrated
`Metrology
`Tools
`106
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Mask
`Verification
`90
`
`Smart inspect 92
`Critical Mask
`Data 94
`
`Smart VPWO 98
`Critica OPC 100
`
`Mask Making
`86
`
`VPWO2
`96
`
`
`
`Wafer Fabrication
`102
`
`Wafer
`Verification
`104
`
`Smart Sampling
`108
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`APC 11 O
`
`Fig. 3
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`Patent Application Publication Jul. 20, 2006 Sheet 4 of 11
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`US 2006/O161452 A1
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`Patent Application Publication Jul. 20, 2006 Sheet 5 of 11
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`US 2006/0161452 A1
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`Patent Application Publication Jul. 20, 2006 Sheet 6 of 11
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`US 2006/O161452 A1
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`
`
`
`
`
`
`
`
`0 | 7 || 0 || 7 || 0 || 7 || 0 || 7
`
`
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`Patent Application Publication Jul. 20, 2006 Sheet 7 of 11
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`US 2006/O161452 A1
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`
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`Patent Application Publication Jul. 20, 2006 Sheet 8 of 11
`
`US 2006/O161452 A1
`
`System Design and Verification
`132
`
`Logic Design and Verification
`136
`
`
`
`
`
`Physical Design and Verification
`138
`
`Mask Data Preparation
`140
`
`
`
`
`
`Geometry
`Data
`144
`
`VPWO
`146
`
`Mayile
`
`Mask Metrology
`150
`
`Mask Inspection
`152
`
`Print Mask. On Wafer
`154
`
`Wafer Metrology
`156
`
`Wafer Inspection
`158
`
`Fig. 9
`
`
`
`
`
`
`
`
`
`g
`
`Lithography
`Model
`142
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`Patent Application Publication Jul. 20, 2006 Sheet 9 of 11
`
`US 2006/0161452 A1
`
`
`
`Reticle Design
`RET Decoration
`160
`
`Fab Model
`Data
`164
`
`Lithography
`Data
`166
`
`
`
`
`
`RET
`Decoration
`174
`
`Data
`Fracture
`176
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Mask Layer
`Data
`172
`
`Mask Writer
`Model
`184
`
`Scanner
`Model
`186
`
`
`
`
`
`
`
`Resist Model
`188
`
`Etch MOde
`200
`
`
`
`
`
`Mask
`Writer Data
`178
`
`VPWO Module
`18O
`
`
`
`
`
`Reference
`Simulated Image
`194
`Input
`A
`Database ar 196
`Second Simulated -
`Images
`192
`
`182
`
`Different
`Values
`190
`
`
`
`
`
`
`
`
`
`
`
`TO
`
`e
`Ps
`
`Fig. 11
`
`Actions
`204
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`Patent Application Publication Jul. 20, 2006 Sheet 10 of 11
`
`US 2006/O161452 A1
`
`Mask Layer Database
`205
`
`VPWO
`2O6
`
`VPWO
`208
`
`RET DeCoration
`210
`
`Reticle Layout
`212
`
`Data Fracture
`214
`
`Write Mask
`
`Inspect Mask
`220
`
`Receive Mask
`224
`
`Print Wafers
`228
`
`
`
`Etch Wafers
`232
`
`Fig. 12
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`Patent Application Publication Jul. 20, 2006 Sheet 11 of 11
`
`US 2006/0161452 A1
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`
`
`Processor
`236
`
`Simulation engine
`240
`
`Fig. 13
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`US 2006/016.1452 A1
`
`Jul. 20, 2006
`
`COMPUTER-IMPLEMENTED METHODS,
`PROCESSORS, AND SYSTEMS FOR CREATING A
`WAFER FABRICATION PROCESS
`
`PRIORITY CLAIM
`0001. This application is a continuation-in-part of U.S.
`patent application Ser. No. 11/048,630 entitled “Computer
`Implemented Methods for Detecting Defects in Reticle
`Design Data.” filed Jan. 31, 2005, which claims priority to
`U.S. Provisional Application No. 60/540,031 entitled
`“Method and System of Qualifying Integrated Circuit
`Design for Manufacturability and Application to Improving
`Critical Dimension Control in Integrated Circuit Manufac
`turing, filed Jan. 29, 2004.
`
`BACKGROUND OF THE INVENTION
`0002) 1. Field of the Invention
`0003. The present invention generally relates to com
`puter-implemented methods for detecting defects in reticle
`design data. Certain embodiments relate to a computer
`implemented method that includes detecting defects in
`reticle design data using simulated images that illustrate how
`a reticle will be printed on a wafer at different values of one
`or more parameters of a wafer printing process.
`0004 2. Description of the Related Art
`0005 The following descriptions and examples are not
`admitted to be prior art by virtue of their inclusion within
`this section.
`0006 Fabricating semiconductor devices such as logic
`and memory devices typically includes processing a Sub
`strate Such as a semiconductor wafer using a number of
`semiconductor fabrication processes to form various fea
`tures and multiple levels of the semiconductor devices. For
`example, lithography is a semiconductor fabrication process
`that involves transferring a pattern from a reticle to a resist
`arranged on a semiconductor wafer. Additional examples of
`semiconductor fabrication processes include, but are not
`limited to, chemical-mechanical polishing, etch, deposition,
`and ion implantation. Multiple semiconductor devices may
`be fabricated in an arrangement on a semiconductor wafer
`and then separated into individual semiconductor devices.
`0007 Lithography is typically one of the most important
`processes in integrated circuit manufacturing since this is the
`process in which features are patterned on the wafer. The
`pattern printed in a resist by lithography is then utilized as
`a masking layer to transfer the pattern to additional layers on
`the wafer in Subsequent processing steps. Therefore, the
`pattern that is formed on the wafer during lithography
`directly affects the features of the integrated circuits that are
`formed on the wafer. Consequently, defects that are formed
`on a wafer during lithography may be particularly problem
`atic for the integrated circuit manufacturing process. One of
`the many ways in which defects may be formed on the
`patterned wafer during lithography is by transfer of defects
`that are present on the reticle to the wafer. Therefore,
`detection and correction of defects on the reticle such as
`unwanted particulate or other matter is performed rather
`stringently to prevent as many defects on the reticle from
`being transferred to the wafer during lithography.
`0008 However, as the dimensions of integrated circuits
`decrease and the patterns being transferred from the reticle
`
`to the wafer become more complex, defects or marginalities
`in the features formed on the reticle become increasingly
`important. In particular, if the pattern is not formed accu
`rately on the reticle. Such discrepancies increasingly produce
`defects on the wafer as the dimensions of the pattern
`decrease and the complexity of the pattern increases. In
`addition, marginalities in the reticle design may cause the
`design to print incorrectly on the wafer. Therefore, signifi
`cant efforts have been devoted to methods and systems that
`can be used to detect problems in the pattern on the reticle
`or in the design that will cause problems on the wafer. These
`efforts are relatively complex and difficult due, at least in
`part, to the fact that not all discrepancies or marginalities in
`the pattern formed on the reticle (as compared to the ideal
`pattern) will cause errors on the wafer that will adversely
`affect the integrated circuit. In other words, some error in the
`pattern formed on the reticle may not produce defects on the
`wafer at all or may produce defects on the wafer that will not
`reduce the performance characteristics of the integrated
`circuit. Therefore, one challenge of many in developing
`adequate methods and systems for qualifying a reticle pat
`tern is to discriminate between pattern defects or margin
`alities that “matter” and those that do not.
`0009. One way to check a reticle pattern before the reticle
`is fabricated is design rule checking (DRC). However,
`conventional DRC operates only at the nominal process
`conditions, or at most, at a limited number of process
`conditions and/or at a limited number of points within the
`device. Other software based methods for detecting design
`pattern defects prior to fabrication of the reticle have been
`proposed, and one such method is described in U.S. Patent
`Application Publication No. 2003/0119216A1 by Weed,
`which is incorporated by reference as if fully set forth
`herein. However, this method is designed to determine only
`the best focus and exposure settings and not to explore the
`full range of the process window conditions available for
`each design. Another method described in U.S. Pat. No.
`6,373.975 to Bula et al., which is incorporated by reference
`as if fully set forth herein, runs simulations only to test for
`specific design rule violations and does not compare full
`chip simulated images to a reference to detect arbitrary
`defects.
`0010. Therefore, such software methods have several
`disadvantages. In particular, these Software methods do not
`examine the full range of process window conditions
`thereby failing to detect process window marginalities and
`missing potential defects. In addition, these methods do not
`determine the exact focus and exposure conditions under
`which defects will occur thereby preventing the complete
`optimization of the design. The lack of complete process
`window information also limits the ability to implement
`advanced process control techniques for critical dimension
`control across all critical features on the device.
`0011. Accordingly, it would be desirable to develop
`methods and systems that can detect reticle design defects or
`marginalities within an entire chip and across a range of
`process conditions such as focus and exposure before the
`reticle is manufactured to reduce the cost of fabricating a
`reticle that is qualified for use in integrated circuit manu
`facturing and to reduce the time involved in fabricating a
`reticle that passes qualification for integrated circuit manu
`facturing.
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`US 2006/016.1452 A1
`
`Jul. 20, 2006
`
`SUMMARY OF THE INVENTION
`0012. The following description of various embodiments
`of computer-implemented methods for detecting defects in
`reticle design data is not to be construed in any way as
`limiting the Subject matter of the appended claims. The
`methods described herein are generally referred to as virtual
`process window qualification (vPWQ) methods.
`0013 An embodiment of the invention relates to a com
`puter-implemented method for detecting defects in reticle
`design data. The method includes generating a first simu
`lated image illustrating how the reticle design data will be
`printed on a reticle using a reticle manufacturing process.
`The method also includes generating second simulated
`images using the first simulated image. The second simu
`lated images illustrate how the reticle will be printed on a
`wafer at different values of one or more parameters of a
`wafer printing process. Therefore, the method includes
`performing a simulation in a two step approach: first,
`simulating from design to reticle (i.e., simulation of the
`mask making process); then, simulating the reticle to wafer
`pattern transfer (i.e., simulation of the wafer manufacturing
`process). In addition, the method includes detecting defects
`in the reticle design data using the second simulated images.
`0014. In one embodiment, the first and second simulated
`images include simulated images of a complete chip defined
`by the reticle design data. In some embodiments, the dif
`ferent values span a predetermined process window for the
`one or more parameters of the wafer printing process.
`Therefore, the method may include simulation of the full
`chip across the full process window to determine regions of
`the device that will fail first as the process conditions (such
`as focus and exposure) vary. In another embodiment, the
`reticle design data includes reticle design data modified by
`resolution enhancement technology (RET) feature data.
`0015. In additional embodiments, the method includes
`determining a process window for the wafer printing process
`based on results of the detecting step. In another embodi
`ment, the method includes determining which of the differ
`ent values at which at least one of the defects appears in the
`second simulated images. In a further embodiment, the
`method includes determining a region in the reticle design
`data in which the defects appear at the different values that
`are closer to nominal values for the one or more parameters
`of the wafer printing process than the different values at
`which the defects appear in other regions in the reticle
`design data.
`0016.
`In one embodiment, the detecting step includes
`comparing the second simulated images to a reference
`image. In this manner, the method may involve identification
`of “defective' regions in the reticle design data by compari
`son to a reference image. The reference image may include
`an additional simulated image illustrating how the reticle
`will be printed on the wafer at nominal values of the one or
`more parameters of the wafer printing process. In another
`such embodiment, the reference image illustrates how the
`reticle design data would ideally be printed on the wafer. In
`other embodiments, the detecting step includes comparing
`one of the second simulated images to additional simulated
`images that illustrate how the reticle will be printed on the
`wafer at the different values that are closer to nominal values
`of the one or more parameters of the wafer printing process
`than the different values corresponding to the one second
`simulated image.
`
`0017. In some embodiments, the method may include
`generating additional simulated images illustrating how the
`reticle design data will be printed on the reticle at different
`values of one or more parameters of the reticle manufactur
`ing process. One Such embodiment includes selecting the
`different values of the one or more parameters of the reticle
`manufacturing process that produce a minimum number of
`design pattern defects on the reticle. As such, the method
`may include selecting the most appropriate mask making
`process for the reticle design data. In another embodiment,
`the method includes altering the reticle design databased on
`results of the detecting step. The altering step may include
`altering RET feature data of the reticle design data. In this
`manner, the method allows for optimal selection of resolu
`tion enhancements, optical proximity correction (OPC)
`rules, design layout, etc.
`0018. In one embodiment, the method may include gen
`erating an inspection process for the reticle based on results
`of the detecting step. In one Such embodiment, the method
`may include linking vPWO data to reticle inspection to drive
`selective sensitivity of the inspector. In an additional
`embodiment, the method may include generating an inspec
`tion process for the wafer based on results of the detecting
`step. In one such embodiment, the method may include
`linking vPWQ data to wafer inspection to drive selective
`sensitivity of the inspector. In a different embodiment, the
`method may include fabricating the reticle Subsequent to the
`detecting step, inspecting the reticle, and generating an
`inspection process for the wafer based on results of the
`detecting step and the inspecting step. In this manner, the
`method may include linking the combination of VPWQ and
`reticle inspection data to wafer inspection to drive selective
`sensitivity of the wafer inspector. In another embodiment,
`the method may include fabricating the reticle Subsequent to
`the detecting step, inspecting the reticle, and generating an
`inspection process for the wafer based on results of the
`detecting step, results of the inspecting step, critical feature
`data generated by a designer of the reticle design data, or
`Some combination thereof. As such, the methods may
`include linking the combination of VPWQ, reticle inspec
`tion, and/or critical features identified by the designer to
`drive wafer inspection sensitivity, metrology sample plans
`and critical dimension (CD) control systems for optimal
`yield.
`0019. In a further embodiment, the method may include
`identifying first regions in the reticle design data that have
`a greater probability of being printed defectively than sec
`ond regions in the reticle design data and generating a
`process control method for wafers that will be printed with
`the reticle based on results of the identifying step. In one
`such embodiment, the method may include linking vPWQ to
`wafer CD metrology tools to drive the optimum sampling
`plan and to detect the earliest possible signs of process
`failure in critical regions identified by VPWQ. In yet another
`embodiment, the method may include identifying first
`regions in the reticle design data that have a greater prob
`ability of being printed defectively than second regions in
`the reticle design data and altering the reticle design data
`based on the identifying step. In this manner, the method
`may include feedback of VPWQ data to the designer and/or
`design process to enable optimization of device electrical
`parameters in the regions identified by VPWQ as most
`limited in terms of process window tolerance. Each of the
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`US 2006/016.1452 A1
`
`Jul. 20, 2006
`
`embodiments of the method described above may include
`any other step(s) described herein.
`0020. Another embodiment relates to a simulation engine
`configured to generate a first simulated image illustrating
`how the reticle design data will be printed on a reticle using
`a reticle manufacturing process. The simulation engine is
`also configured to generate second simulated images using
`the first simulated image. The second simulated images
`illustrate how the reticle will be printed on a wafer at
`different values of one or more parameters of a wafer
`printing process. The second simulated images can be used
`to detect defects in the reticle design data. The simulation
`engine may be further configured as described herein.
`0021. An additional embodiment relates to a system
`configured to detect defects in reticle design data. The
`system includes a simulation engine configured to generate
`a first simulated image illustrating how the reticle design
`data will be printed on a reticle using a reticle manufacturing
`process. The simulation engine is also configured to generate
`second simulated images using the first simulated image.
`The second simulated images illustrate how the reticle will
`be printed on a wafer at different values of one or more
`parameters of a wafer printing process. The system also
`includes a processor configured to detect defects in the
`reticle design data using the second simulated images. The
`system may be further configured as described herein.
`0022. Another embodiment relates to a different method
`for detecting defects in reticle design data. This method
`includes generating a first simulated image illustrating how
`the reticle design data will be printed on a reticle using a
`reticle manufacturing process. The method also includes
`generating second simulated images using the first simulated
`image. The second simulated images illustrate how the
`reticle will be printed on a wafer at different values of one
`or more parameters of a wafer printing process. In addition,
`the method includes determining a rate of change in a
`characteristic of the second simulated images as a function
`of the different values. This method further includes detect
`ing defects in the reticle design data based on the rate of
`change. In one embodiment, the detecting step may include
`using the rate of change in combination with the second
`simulated images to detect the defects in the reticle design
`data. Each of the embodiments of this method may also
`include any other step(s) described herein.
`0023. An additional embodiment relates to a method for
`detecting defects in reticle design data printed on a reticle.
`This method includes printing images of the reticle on a
`wafer at different values of one or more parameters of a
`wafer printing process. The method also includes determin
`ing a rate of change in a characteristic of the images as a
`function of the different values. In addition, the method
`includes detecting defects in the reticle design databased on
`the rate of change. This method may also include any other
`step(s) described herein.
`0024. A further embodiment relates to a computer-imple
`mented method for creating a wafer fabrication process. The
`method includes determining individual error budgets for
`different parameters of the wafer fabrication process based
`on an overall error budget for the wafer fabrication process
`and simulated images that illustrate how reticle design data
`will be printed on a wafer at different values of the different
`
`parameters. The method also includes creating the wafer
`fabrication process based on the overall error budget and the
`individual error budgets.
`0025. In one embodiment, the wafer fabrication process
`includes a lithography process. In another embodiment, the
`wafer fabrication process includes an etch process. In an
`additional embodiment, the wafer fabrication process
`includes a device design process, a reticle manufacturing
`process, and a lithography process. In some embodiments,
`the wafer fabrication process includes a device design
`process, a reticle manufacturing process, a lithography pro
`cess, and an etch process.
`0026.
`In one embodiment, creating the wafer fabrication
`process includes selecting operating set points and levels of
`control for the different parameters based on the overall error
`budget and the individual error budgets. In some embodi
`ments, creating the wafer fabrication process includes modi
`fying predetermined operating set points for the different
`parameters based on the overall error budget and the indi
`vidual error budgets. In another embodiment, creating the
`wafer fabrication process includes selecting operating set
`points and levels of control for the different parameters
`based on the overall error budget and how variations in the
`individual error budgets affect how the reticle design data
`will be printed on the wafer.
`0027. In an additional embodiment, the individual error
`budget for one of the different parameters is determined as
`a function of the individual error budget for another of the
`different parameters. In some embodiments, creating the
`wafer fabrication process includes selecting operating set
`points and levels of control for at least two of the different
`parameters based on the overall error budget and a function
`describing an interrelated effect of the individual error
`budgets for the at least two of the different parameters on
`how the reticle design data will be printed on the wafer.
`0028. In a further embodiment, creating the wafer fabri
`cation process includes selecting operating set points and
`levels of control for the different parameters based on the
`overall error budget, the individual error budgets, and con
`trollability of the different parameters. In another embodi
`ment, creating the wafer fabrication process includes select
`ing operating set points and levels of control for the different
`parameters based on the overall error budget, the individual
`error budgets, and cost of implementing the levels of con
`trol.
`0029. In one embodiment, the different parameters
`include all parameters of the wafer fabrication process that
`can alter how the reticle design data will be printed on the
`wafer. In another embodiment, the method includes gener
`ating the simulated images by generating a first simulated
`image illustrating how the reticle design data will be printed
`on a reticle using a reticle manufacturing process and
`generating the simulated images using the first simulated
`image. In an additional embodiment, the different values
`span a predetermined process window for the different
`parameters. In a further embodiment, the method includes
`detecting defects in the simulated images. In one Such
`embodiment, determining the individual error budgets
`includes determining the individual error budgets based on
`the overall error budget and the defects in the simulated
`images.
`0030. In some embodiments, the different parameters
`include different characteristics of the reticle design data. In
`
`NXP Ex. 2009
`Impinj, Inc. v. NXP B.V. - IPR2020-01630
`Page 15 of 36
`
`

`

`US 2006/016.1452 A1
`
`Jul. 20, 2006
`
`one Such embodiment, the method includes creating a design
`process for the reticle design databased on the overall error
`budget and the individual error budgets for the different
`parameters. In another such embodiment, the method
`includes altering the reticle design databased on the overall
`error budget and the individual error budgets for the different
`parameters. Each of the embodiments of the method
`described above may include any other step(s) of any other
`method(s) described herein.
`0.031) Another embodiment relates to a processor config
`ured to perform a method for creating a wafer fabrication
`process. The method includes determining individual error
`budgets for different parameters of the wafer fabrication
`process based on an overall error budget for the wafer
`fabrication process and simulated images that illustrate how
`reticle design data will be printed on a wafer at different
`values of the different parameters. The method also includes
`creating the wafer fabrication process based on the overall
`error budget and the individual error budgets. The processor
`may be further configured as described herein.
`0032. An additional embodiment relates to a system
`configured to create a wafer fabrication process. The system
`includes a simulation engine configured to generate simu
`lated images illustrating how reticle design data will be
`printed on a wafer at different values of different parameters
`of the wafer fabrication process. The system also includes a
`processor configured to determine individual error budgets
`for the different parameters based on an overall error budget
`for the wafer fabrication process and the simulated images.
`The processor is also configured to create the wafer fabri
`cation process based on the overall error budget and the
`individual error budgets. The system may be further con
`figured as described herein.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0033. Further advantages of the present invention may
`become apparent to those skilled in the art with the benefit
`of the following detailed description of the preferred
`embodiments and upon reference to the accompanying
`drawings in which:
`0034 FIG. 1 is a flow chart illustrating a method for
`qualifying a reticle for production in integrated circuit
`manufacturing;
`0035 FIG. 2 is a flow chart illustrating one embodiment
`of a computer-implemented method for detecting defects in
`reticle design data;
`0.036
`FIG. 3 is a flow chart illustrating one embodiment
`of a method for data flow between a computer-implemented
`method for detecting defects in reticle design data and other
`process steps:
`0037 FIG. 4 is a schematic diagram illustrating one
`example of different areas in reticle design data having
`different levels and types of criticality;
`0038 FIG. 5 is a schematic diagram illustrating one
`example of different values of parameters of a wafer printing
`process for which simulated images can be generated, which
`can be used to detect defects in reticle design data;
`0.039
`FIG. 6 is a schematic diagram illustrating one
`embodiment of different values of parameters of a wafer
`
`printing process for which simulated images can be gener
`ated, which can be used to detect defects in reticle design
`data;
`0040 FIG. 7 is a schematic diagram illustrating one
`arrangement of dies printed on a wafer at different values of
`parameters of a wafer printing process that can be used to
`detect defects in reticle design data;
`0041
`FIG. 8 is a schematic diagram illustrating one
`embodiment of an arrangement of dies simulated or printed
`on a wafer at different values of parameters of a wafer
`printing process that can be used to detect defects in reticle
`design data:
`0.042 FIGS. 9-12 are flow charts illustrating various
`embodiments of a computer-implemented method for
`detecting defects in reticle design data; and
`0043 FIG. 13 is a block diagram illustrating one
`embodiment of a processor configured to perform a method
`for creating a wafer fabrication process and one embodiment
`of a system configured to create a wafer fabrication process.
`0044) While the invention is susceptible to various modi
`fications and alternative forms, specific embodiments
`thereof are shown by way of example in the drawings and
`may herein be described in detail. The drawings may not be
`to scale. It should be understood, however, that the drawings
`and detailed description thereto are not intended to limit the
`invention to the particular form disclosed, but on the con
`trary, the intention is to cover all modifications, equivalents
`and alternatives falling within the spirit and scope of the
`present invention as defined by the appended claims.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`0045. As used herein, the term “wafer generally refers to
`a Substrate formed of a semiconductor or non-semiconductor
`material. Examples of Such a semiconductor or non-semi
`conducto