Patent No. 7,274,321
`Petition For Inter Partes Review
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`XILINX, INC. and XILINX ASIA PACIFIC PTE. LTD.
`Petitioner,
`v.
`ANALOG DEVICES, INC.
`Patent Owner.
`
`Patent No. 7,274,321
`
`_______________
`Inter Partes Review No. IPR2021-00294
`____________________________________________________________
`
`DECLARATION OF DR. MARK N. HORENSTEIN
`
`
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1002 Page 1
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`Inter Partes Review of USP 7,274,321
`TABLE OF CONTENTS
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`Page
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`V.
`
`
`INTRODUCTION .......................................................................................... 1
`I.
`EXPERIENCE AND QUALIFICATIONS .................................................... 1
`II.
`III. DOCUMENTS CONSIDERED ..................................................................... 3
`IV. BACKGROUND OF THE TECHNOLOGY ................................................. 3
`A. Overview of Analog-to-Digital Converters ......................................... 3
`B. Overview of Flash-Only ADCs .......................................................... 11
`C. Overview of Pipelined ADCs ............................................................. 14
`D. Overview of Switched Capacitor Array Successive
`Approximation ADCs ........................................................................ 17
`SUMMARY OF THE ’321 PATENT .......................................................... 21
`A.
`Filing Date and Priority Dates ............................................................ 21
`B.
`Specification ....................................................................................... 21
`C.
`Claims ................................................................................................. 31
`VI. CLAIM CONSTRUCTION ......................................................................... 32
`A.
`“operating in parallel” ........................................................................ 33
`B.
`“second converter core” ..................................................................... 33
`VII. RELEVANT LEGAL STANDARDS .......................................................... 34
`A. Anticipation ........................................................................................ 34
`B. Obviousness ........................................................................................ 35
`VIII. LEVEL OF ORDINARY SKILL IN THE ART FOR THE ’321
`PATENT ....................................................................................................... 37
`IX. PRIOR ART .................................................................................................. 38
`X. ANALYSIS AND OPINIONS ..................................................................... 39
`A.
`Claims 1, 2, 5, 6, 8, and 13–16 are obvious in view of Dabbagh-
`Sadeghipour and Fetterman ................................................................ 39
`1.
`Summary of Dabbagh-Sadeghipour ......................................... 39
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`
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`-i-
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`TABLE OF CONTENTS
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`2.
`3.
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`4.
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`b.
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`c.
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`d.
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`e.
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`f.
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`Summary of Fetterman ............................................................ 40
`Claim 1 ..................................................................................... 47
`a.
`Preamble: “A[n] analog to digital converter,
`comprising:” .................................................................. 47
`1[a]: “an input for receiving an input signal to be
`digitised;” ....................................................................... 48
`1[b]: “a first converter core for performing a first
`part of an analog to digital conversion,” ....................... 50
`1[c]: “said first converter core comprising at least
`three switched capacitor analog to digital
`conversion engines operating in parallel and in a
`co-operative manner and” .............................................. 52
`1[d]: “for outputting a first digital result and an
`analog representation of the first digital result;” ........... 58
`1[e]: “a first residue generator for generating a
`first residue as a difference between the input
`signal and the analog representation of the first
`digital result;” ................................................................ 60
`1[f]: “a second converter core for performing a
`second part of the analog to digital conversion by
`converting the first residue;” ......................................... 62
`1[g]: “wherein the analog to digital further
`comprises a controller for controlling the operation
`of the engines such that the engines co-operate to
`perform a successive approximation search, and” ........ 64
`1[h]: “wherein the first converter core is further
`operable to act as the first residue generator.” .............. 66
`Claim 2: “An analog to digital converter as claimed in
`claim 1, wherein at least one of the converter cores can
`determine a plurality of bits during a single trial step
`within that converter core.” ...................................................... 67
`
`g.
`
`h.
`
`i.
`
`-ii-
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`TABLE OF CONTENTS
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`Claim 5: “An analog to digital converter as claimed in
`claim 1, further comprising a first amplifier for
`amplifying the first residue.” ................................................... 68
`Claim 6: “An analog to digital converter as claimed in
`claim 5, in which the amplifier applies a known gain.” .......... 70
`Claim 8: “An analog to digital converter as claimed in
`claim 1, in which the second conversion core comprises a
`plurality of analog to digital conversion engines
`operating in parallel in a co-operative manner.” ..................... 71
`Claim 13: “An analog to digital converter as claimed in
`claim 1 wherein, for a first bit trial, only 1 bit is
`determined by the first converter core.” .................................. 73
`Claim 14 ................................................................................... 75
`a.
`Preamble: “A method of converting an analog
`signal into a digitised value, comprising the steps
`of:” ................................................................................. 75
`14[a]: “receiving an input signal to be digitised,
`using a first converter core to perform a first part
`of an analog to digital conversion and outputting
`the result of a first digital result;” .................................. 75
`14[b]: “forming a residue as a difference between
`the input signal and the first digital result;” .................. 76
`14[c]: “using a second converter core to perform a
`second part of an analog to digital conversion by
`converting the first residue; and” .................................. 77
`14[d]: “wherein the first conversion core
`comprises at least three switched capacitor
`successive approximation conversion engines
`operable to determine two bits per bit trial, and
`wherein the first trial only trials one bit.” ...................... 77
`10. Claim 15 ................................................................................... 78
`
`b.
`
`c.
`
`d.
`
`e.
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`5.
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`6.
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`7.
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`8.
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`9.
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`-iii-
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`TABLE OF CONTENTS
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`a.
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`b.
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`c.
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`d.
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`e.
`f.
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`g.
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`Preamble: “A method of converting an analog
`value into a digitised equivalent, the method
`comprising the steps of:” ............................................... 78
`15[a]: “i. sampling the analog value into a
`plurality of first stage conversion engines;” .................. 78
`15[b]: “ii. operating the first stage conversion
`engines in a co-operative manner to perform a
`successive approximation conversion where at
`least two bits can be determined during a single
`trial step;” ....................................................................... 80
`15[c]: “iii. digitising a first plurality of bits to
`form a first digital representation, and forming a
`residue between the analog equivalent of the first
`digital representation and the analog value;” ................ 80
`15[d]: “iv. amplifying the residue;” ............................. 82
`15[e]: “v. sampling the residue into a plurality of
`second stage conversion engines;” ................................ 82
`15[f]: “vi. operating the second stage conversion
`engines in a co-operative manner to perform a
`successive approximation conversion where at
`least two bits can be determined during a single
`trial step so as to determine a second digital
`representation; and” ....................................................... 83
`15[g]: “vii. using the first and second digital
`representations to produce a digital output value.” ....... 85
`11. Claim 16 ................................................................................... 87
`a.
`Preamble: “An analog to digital converter
`comprising:” .................................................................. 87
`
`h.
`
`-iv-
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`B.
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`b.
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`c.
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`d.
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`16[a]: “a first stage having a plurality of
`conversion engines adapted to operate in a
`co-operative manner such that they perform a
`successive approximation search” ................................. 87
`16[b]: “where two bits are determined during a
`trial step and” ................................................................. 88
`16[c]: “where the first stage acts to form a first
`digital word representing a first portion of an
`analog signal;” ............................................................... 88
`16[d]: “an amplification stage for receiving an
`analog signal from the first stage representing a
`difference between the analog signal and an analog
`representation of the digitised first portion of the
`analog signal;” ............................................................... 89
`16[e]: “a second stage having a plurality of
`conversion engines adapted to operate in a
`co-operative manner such that they perform a
`successive approximation search where two bits
`are determined during a trial step and the second
`stage forms a second digital word; and” ........................ 90
`16[f]: “a combiner for combining the first and
`second digital words to produce an output word.” ........ 90
`Claims 3 and 18 are obvious in view of Dabbagh-Sadeghipour,
`Fetterman, and Hester ........................................................................ 92
`1.
`Summary of Hester .................................................................. 92
`2.
`Claim 3: “An analog to digital converter as claimed in
`claim 1, in which each conversion engine includes
`redundant bits and a controller associated with the
`conversion engine converts the result from the
`conversion engine into a binary word.” ................................... 93
`
`e.
`
`f.
`
`g.
`
`-v-
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`TABLE OF CONTENTS
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`Page
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`C.
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`3.
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`b.
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`c.
`
`d.
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`Claim 18: “An analog to digital converter as claimed in
`claim 16, where each conversion engine is a switched
`capacitor conversion engine having redundant bits.” .............. 96
`Claims 1, 2, 5, 6, 8, and 13-16 are obvious in view of Guillen
`and Cai ................................................................................................ 97
`1.
`Summary of Guillen ................................................................. 97
`2.
`Summary of Cai ..................................................................... 108
`3.
`Claim 1 ................................................................................... 113
`a.
`Preamble: “A[n] analog to digital converter,
`comprising:” ................................................................ 113
`1[a]: “an input for receiving an input signal to be
`digitised;” ..................................................................... 114
`1[b]: “a first converter core for performing a first
`part of an analog to digital conversion,” ..................... 115
`1[c]: “said first converter core comprising at least
`three switched capacitor analog to digital
`conversion engines operating in parallel and in a
`co-operative manner and” ............................................ 116
`1[d]: “for outputting a first digital result and an
`analog representation of the first digital result;” ......... 124
`1[e]: “a first residue generator for generating a
`first residue as a difference between the input
`signal and the analog representation of the first
`digital result;” .............................................................. 125
`1[f]: “a second converter core for performing a
`second part of the analog to digital conversion by
`converting the first residue;” ....................................... 127
`
`e.
`
`f.
`
`g.
`
`-vi-
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`
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`TABLE OF CONTENTS
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`Page
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`4.
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`5.
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`6.
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`7.
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`8.
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`9.
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`h.
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`i.
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`1[g]: “wherein the analog to digital further
`comprises a controller for controlling the operation
`of the engines such that the engines co-operate to
`perform a successive approximation search, and” ...... 129
`1[h]: “wherein the first converter core is further
`operable to act as the first residue generator.” ............ 130
`Claim 2: “An analog to digital converter as claimed in
`claim 1, wherein at least one of the converter cores can
`determine a plurality of bits during a single trial step
`within that converter core.” .................................................... 131
`Claim 5: “An analog to digital converter as claimed in
`claim 1, further comprising a first amplifier for
`amplifying the first residue.” ................................................. 132
`Claim 6: “An analog to digital converter as claimed in
`claim 5, in which the amplifier applies a known gain.” ........ 135
`Claim 8: “An analog to digital converter as claimed in
`claim 1, in which the second conversion core comprises a
`plurality of analog to digital conversion engines
`operating in parallel in a co-operative manner.” ................... 136
`Claim 13: “An analog to digital converter as claimed in
`claim 1 wherein, for a first bit trial, only 1 bit is
`determined by the first converter core.” ................................ 137
`Claim 14 ................................................................................. 138
`a.
`Preamble: “A method of converting an analog
`signal into a digitised value, comprising the steps
`of:” ............................................................................... 138
`14[a]: “receiving an input signal to be digitised,
`using a first converter core to perform a first part
`of an analog to digital conversion and outputting
`the result of a first digital result;” ................................ 138
`
`b.
`
`-vii-
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`TABLE OF CONTENTS
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`c.
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`d.
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`e.
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`b.
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`c.
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`14[b]: “forming a residue as a difference between
`the input signal and the first digital result;” ................ 139
`14[c]: “using a second converter core to perform a
`second part of an analog to digital conversion by
`converting the first residue; and” ................................ 140
`14[d]: “wherein the first conversion core
`comprises at least three switched capacitor
`successive approximation conversion engines
`operable to determine two bits per bit trial, and
`wherein the first trial only trials one bit.” .................... 140
`10. Claim 15 ................................................................................. 141
`a.
`Preamble: “A method of converting an analog
`value into a digitised equivalent, the method
`comprising the steps of:” ............................................. 141
`15[a]: “i. sampling the analog value into a
`plurality of first stage conversion engines;” ................ 141
`15[b]: “ii. operating the first stage conversion
`engines in a co-operative manner to perform a
`successive approximation conversion where at
`least two bits can be determined during a single
`trial step;” ..................................................................... 142
`15[c]: “iii. digitising a first plurality of bits to
`form a first digital representation, and forming a
`residue between the analog equivalent of the first
`digital representation and the analog value;” .............. 142
`15[d]: “iv. amplifying the residue;” ........................... 143
`15[e]: “v. sampling the residue into a plurality of
`second stage conversion engines;” .............................. 143
`
`d.
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`e.
`f.
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`-viii-
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`TABLE OF CONTENTS
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`g.
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`h.
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`15[f]: “vi. operating the second stage conversion
`engines in a co-operative manner to perform a
`successive approximation conversion where at
`least two bits can be determined during a single
`trial step so as to determine a second digital
`representation; and” ..................................................... 144
`15[g]: “vii. using the first and second digital
`representations to produce a digital output value.” ..... 145
`11. Claim 16 ................................................................................. 147
`a.
`Preamble: “An analog to digital converter
`comprising:” ................................................................ 147
`16[a]: “a first stage having a plurality of
`conversion engines adapted to operate in a
`co-operative manner such that they perform a
`successive approximation search” ............................... 147
`16[b]: “where two bits are determined during a
`trial step and” ............................................................... 147
`16[c]: “where the first stage acts to form a first
`digital word representing a first portion of an
`analog signal;” ............................................................. 148
`16[d]: “an amplification stage for receiving an
`analog signal from the first stage representing a
`difference between the analog signal and an analog
`representation of the digitised first portion of the
`analog signal;” ............................................................. 148
`16[e]: “a second stage having a plurality of
`conversion engines adapted to operate in a
`co-operative manner such that they perform a
`successive approximation search where two bits
`are determined during a trial step and the second
`stage forms a second digital word; and” ...................... 149
`
`b.
`
`c.
`
`d.
`
`e.
`
`f.
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`-ix-
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`TABLE OF CONTENTS
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`g.
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`2.
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`D.
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`16[f]: “a combiner for combining the first and
`second digital words to produce an output word.” ...... 150
`Claims 3 and 18 are obvious in view of Guillen, Cai, and Hester ... 150
`1.
`Claim 3: “An analog to digital converter as claimed in
`claim 1, in which each conversion engine includes
`redundant bits and a controller associated with the
`conversion engine converts the result from the
`conversion engine into a binary word.” ................................. 150
`Claim 18: “An analog to digital converter as claimed in
`claim 16, where each conversion engine is a switched
`capacitor conversion engine having redundant bits.” ............ 152
`XI. CONCLUSION ........................................................................................... 152
`
`
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`-x-
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`APPENDIX LIST FOR DECLARATION OF DR. MARK HORENTSEIN
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`
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`Appendix Description
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`Appendix
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`Curriculum Vitae
`
`List of Materials Considered
`
`
`
`A
`
`B
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`-xi-
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`I.
`INTRODUCTION
`1. My name is Dr. Mark N. Horenstein. I have been retained as an
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`
`
`expert witness on behalf of Petitioner Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd.
`
`(“Xilinx”) to provide expert opinions on the patentability of United States Patent
`
`No. 7,274,321 (“the ’321 patent”).
`
`2.
`
`I am being compensated at my normal rate, plus reimbursement for
`
`expenses, for my analysis. My compensation does not depend on the content of
`
`my opinions or the outcome of this proceeding.
`
`II. EXPERIENCE AND QUALIFICATIONS
`3.
`In formulating my opinions, I have relied upon my knowledge,
`
`training, and experience in the relevant art. My qualifications are stated more fully
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`in my curriculum vitae, which has been provided as Appendix A. Here, I provide a
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`brief summary of my qualifications.
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`4. My education includes a Ph.D. in Electrical Engineering from the
`
`Massachusetts Institute of Technology (MIT), which I earned in 1978. I also have
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`an M.S. degree in Electrical Engineering from the University of California at
`
`Berkeley (1975) and an S.B. degree in Electrical Engineering from MIT (1973).
`
`5.
`
`I am a Life Fellow of the Institute of Electrical and Electronic
`
`Engineers (IEEE). I have been a Registered Professional Engineer (Electrical) in
`
`1
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`the Commonwealth of Massachusetts. I hold certification from the National
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`
`
`Association of Radio and Telecommunications Engineers.
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`6.
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`I am the author of two textbooks, including Microelectronic Circuits
`
`and Devices, 1st and 2nd Eds. (Prentice-Hall 1996) and Design Concepts for
`
`Engineers, 1st through 5th Eds. (Pearson Education 2016). I have authored book
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`chapters in two reference books related to electromagnetics. I have authored or
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`co-authored over 60 journal articles on a variety of topics in my fields of expertise,
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`and approximately 100 conference papers. I have advised several Ph.D. students
`
`performing research in my fields of expertise; these students have gone on to hold
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`various positions in industry and academia. I am a named inventor on five patents
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`related to my areas of expertise.
`
`7. My course teaching repertoire involves about 10 different courses,
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`each of which I have taught numerous times over the past 40 years to over 4,000
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`undergraduate and graduate students. The subject matter of these courses, among
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`other areas, includes analog and digital electronics at both the introductory and
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`advanced levels. The majority of the courses that I have taught over the past 15
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`years have been in the areas of circuits, electronics, and analog and digital design.
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`8. My analyses set forth in this declaration are informed by my
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`experience in the field of electrical engineering, including analog circuitry and
`
`2
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`analog-to-digital converters (ADCs). Based on my above-described experience, I
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`
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`believe that I am considered to be an expert in the field.
`
`III. DOCUMENTS CONSIDERED
`9.
`In preparing this Declaration, I have reviewed the ’321 patent and its
`
`file history. I also have considered each of the documents cited in this Declaration,
`
`and the documents specifically identified in Appendix B. In formulating my
`
`opinions, I have further relied on my extensive experience in the relevant fields.
`
`IV. BACKGROUND OF THE TECHNOLOGY
`A. Overview of Analog-to-Digital Converters
`10.
`In the field of electric signal processing, information can be
`
`represented in one of two forms. An analog signal, usually in the form of a
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`voltage, is one that varies continuously over a range defined by designated
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`minimum and maximum values. For example, an analog signal could be a voltage,
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`obtained from a sensor, that varies over the designated range of 0 V to 5V,
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`representing a temperature range of, say, 0F to 98F. In the digital domain, the
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`same range of temperatures could be represented by binary (base-2) numbers
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`spanning the range from 000 0000 to 110 0010 (decimal values of 0 and 98,
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`respectively1). Each instance of a 0 or 1 in the string is called a “bit,” and the
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`binary number can vary, but only in increments of one bit, over the complete
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`1 Spaces have been added in these numbers for readability purposes only.
`3
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`range. The left-most binary digit carries the most weight and is thus called the
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`
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`most significant bit (MSB). The right-most binary digit carries the least weight
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`and is called the least significant bit (LSB). In digital systems, a voltage is used to
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`electronically represent a given bit, where (as an example) 5 V represents the
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`binary digit 1, and 0 V represents the binary digit 0. Voltage values lying between
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`0 V and 5V have no meaning in such a digital system and are indeterminate. Only
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`high (5V) and low (0V) values of the voltage, representing the binary digitals 1 and
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`0, respectively, have meaning.
`
`11. Using the example above of a sensor that produces a voltage
`
`representing temperature, the analog output of the sensor can be converted into its
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`equivalent digital form by ADC. An ADC is generally fabricated as a single
`
`integrated circuit on a small semiconductor (e.g., silicon) chip, and such circuits
`
`are widely available commercially.
`
`12. An ADC is commonly used in electronic systems to convert an analog
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`signal into a digital signal, where the latter takes the form of a “digital code” or
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`“digital word” comprising a set of binary bits. It is typical for the analog input to
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`an ADC to vary over time, hence the ADC takes periodic samples of the analog
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`signal for conversion into its digital equivalent at the moment of sampling. The
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`resulting digital word representing the sampled analog signal is then generally
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`4
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`passed to another digital circuit, such as a microcontroller or other computational
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`
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`device, for evaluation and processing.
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`13. The analog-to-digital conversion process generally involves two steps.
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`In the first step, the analog signal is sampled by an appropriate sampling circuit.
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`The sampling generally takes place periodically, hence the analog signal is
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`sampled at a chosen sampling rate, sometimes referred to as the “clock rate.” In
`
`the second step, the sampled analog signal is quantized into discrete quantization
`
`levels to generate the digital signal. The number of quantization levels depends on
`
`the bit resolution of the converter. The term “resolution” in this context refers to
`
`the analog voltage increment represented by a one-bit change in the lowest order
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`digital bit. The later, as noted above, occupies the right-most place in the digital
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`word (i.e., the LSB).
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`14. Sampling rate and bit resolution are important metrics for
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`characterizing an ADC. In many applications, an ADC with a high sampling rate
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`is desired. High sampling rates are needed for high-speed applications where the
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`analog signal being sampled varies rapidly over time. Such rapidly-changing
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`signals are known to have a large bandwidth in the frequency spectrum. The term
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`“frequency spectrum” refers to the aggregate of all the frequency components that
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`together make up the complete signal. High sampling rates are needed to
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`accommodate the quantization of analog signals over large bandwidths. In the
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`field of signal processing, the highest frequency component of the signal that can
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`
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`be converted is equal to half the frequency of the sampling rate. This parameter is
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`commonly known as the Nyquist sampling rate.
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`15. One area of technology in which high-speed ADCs are commonly
`
`found is in wireless communications. In such systems, a high-speed ADC is used
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`to sample a radio frequency (RF) input to a radio receiver. The availability of
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`high-speed ADCs permits RF signals to be sampled directly for further processing.
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`Earlier ADC alternatives having slower sampling rates and smaller bandwidth
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`requirements that the information carried by the incoming RF signal needed to first
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`be translated to lower frequencies in analog form, with the analog-to-digital
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`conversion occurring only after the analog frequency translation. The latter
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`process required additional power-consuming analog circuitry and yielded only
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`modest bandwidth-conversion capability. These earlier approaches to ADCs were
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`thus much slower than more modern direct-conversion ADCs. As a person of
`
`ordinary skill in the art (POSITA) would know, direct RF sampling receivers based
`
`on high-speed ADCs have much higher bandwidth compared to their older
`
`frequency-translation counterparts. The capability of quantizing wideband signals
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`with more modern ADCs also allows for increased data throughput.
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`16. While advantages can be realized by a high sampling-rate ADC
`
`enabling signal processing at much larger bandwidths, it is also important for such
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`Inter Partes Review of USP 7,274,321
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`an ADC to maintain sufficient conversion accuracy. The latter is related to the
`
`
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`ADC’s bit resolution. That is, the digital word coming out of the ADC must be an
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`accurate representation of the sampled analog signal. As noted above, the
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`conversion accuracy is related to the ADC’s bit resolution. The latter refers to the
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`smallest increment of analog signal represented by the LSB of the converted digital
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`signal.
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`17. Referring to our previous example, but in simpler form, suppose that
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`the analog voltage span from 0 V to 5 V was represented by just three digital bits
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`from 000 (the number zero in decimal) to 111 (the number eight in decimal). Such
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`a coarse quantization would result in just eight possible levels of quantization, each
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`corresponding to an increment of one-eighth of 5 V, or 0.625 V. Such a coarsely
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`quantized ADC would have a very low conversion accuracy. In contrast, if the
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`same 0 V to 5 V analog voltage range were quantized using twelve digital bits,
`
`spanning the range from 0000 0000 0000 (zero in decimal) to 1111 1111 1111 (the
`
`number 4096 in decimal), the system would have 4096 levels of quantization,
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`wherein each corresponded to 1/4096 of 5 V, or 0.00122 V. Such an ADC would
`
`have a much better conversion accuracy because a change in the LSB would
`
`represent a much smaller voltage increment than an ADC based on only three bits.
`
`In general, the higher the bit resolution, the better the conversion accuracy.
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`
`18. An ADC can be implemented in several different ways, and there are
`
`
`
`benefits associated with each implementation. The architecture of an ADC
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`generally depends on the tolerance for implementation complexity as dictated by
`
`the target specification. Such complexity involves factors such as sampling rate,
`
`bit resolution, and other important parameters. In general, the more demanding the
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`target specification, the more costly and complex the required circuitry.
`
`19. At the time of the filing of the ’321 patent application, there were at
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`least three well-known and commonly-adopted architectures for analog-to-digital
`
`conversion. These architectures were known as: (1) flash, (2) pipelined, and (3)
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`successive-approximation register (SAR). These three design choices persist to the
`
`present time. Choosing among these different architectures invol