IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010
`
`2647
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`An 18 b 12.5 MS/s ADC With 93 dB SNR
`
`Christopher Peter Hurrell, Colin Lyden, David Laing, Derek Hummerston, and Mark Vickery
`
`Abstract—This paper presents a precision 18-bit 12.5 MS/s ADC
`that was designed primarily for digital X-ray imaging systems.
`This ADC was intended to have a faster output data rate than the
`precision successive approximation ADCs normally chosen for
`these systems but with similar DC accuracy and dynamic range.
`The chosen architecture consists of a pipeline of two multi-bit
`successive approximation converters. The first successive approx-
`imation ADC generates an initial coarse conversion result. The
`DACs within this converter are then used to generate a residue
`which is amplified by a residue amplifier before being converted
`by a second successive approximation ADC. Four comparators
`within each ADC allow 2 bits to be determined each bit trial.
`Capacitor mismatch errors are digitally corrected with error coef-
`ficients stored in non-volatile memory. Dither is used to reduce the
`effect of errors in the flash ADC within the second ADC. The ADC
`was implemented on 0.25 m CMOS process with PIP capacitors
`and achieves a SNR of 93 dB with a 50 kHz input tone. INL and
`2 2 LSB and
`0 3 LSB respectively. Power
`DNL are within
`consumption is 105 mW, excluding LVDS interface power.
`Index Terms—ADC, calibration, dither, flash, pipeline, succes-
`sive approximation.
`
`I. INTRODUCTION
`
`D IGITAL X-ray image capture is increasingly being chosen
`
`for medical diagnostics over traditional X-ray film as it
`provides the potential benefits of reduced patient exposure, dig-
`ital enhancement of the image, faster patient throughput and
`lower image archiving costs. In digital X-ray systems each pixel
`in a photodiode array is processed by a charge integrator, the
`outputs of which are multiplexed to a number of ADCs. These
`ADCs need to have both a high dynamic range, typically better
`than 90 dB and excellent linearity. The dynamic range require-
`ment is due in part to the phenomenon that the number of X-ray
`photons reaching the sensor decreases exponentially with the
`distance that the X-rays pass through the patient: just 20 mm of
`soft body tissue can be enough to reduce the number of trans-
`mitted X-rays by half (6 dB). The need for high linearity is
`due to the way that different areas of the photo-diode array
`are processed by different ADCs. To avoid visible artifacts at
`the boundaries between these areas, all the ADCs need to have
`matching linearity. This is best ensured by placing a tight lin-
`earity requirement on each ADC, with linearity better than 15
`ppm being generally specified.
`
`Manuscript received April 13, 2010; revised July 02, 2010; accepted August
`02, 2010. Date of publication November 09, 2010; date of current version De-
`cember 03, 2010. This paper was approved by Guest Editor Boris Murmann.
`C. P. Hurrell, D. Laing, D. Hummerston, and M. Vickery are with Analog
`Devices, Rothwell House, Newbury Berkshire RG14 1BX, U.K. (e-mail: peter.
`hurrell@analog.com).
`C. Lyden is with Analog Devices, Airport Business Park, Cork, Ireland.
`Color versions of one or more of the figures in this paper are available online
`at http://ieeexplore.ieee.org.
`Digital Object Identifier 10.1109/JSSC.2010.2075310
`
`Pipeline converters are generally optimized for high SFDR.
`High SFDR can be more readily achieved with a relatively
`small input signal, typically no more than 2 V pk-pk differen-
`tial, where the input switches and driving circuits are operating
`in a more linear region. Few pipeline converters achieve better
`than 80 dB SNR or DR for this reason. Capacitor matching
`errors along with residue amplifier (RA) gain, settling and
`linearity errors can be significant sources of ADC linearity
`error. Digital calibration of capacitor errors and dither have
`been used in [1] to achieve linearity of 22.9 ppm which is close
`to the linearity requirement for this application. Delta-sigma
`ADCs do exhibit sufficiently high dynamic range and excellent
`linearity, however, the digital filters needed to remove their
`quantization noise have settling times that are too long to give
`acceptable channel switching rates. The required dynamic
`range and linearity requirements are met by a number of com-
`mercially available 16-bit successive approximation register
`(SAR) ADCs at reasonable conversion rates.
`To increase SAR ADC conversion rates, efforts have been
`made to decrease the bit trial time, of which the DAC settling
`time is usually the largest component.
`DAC
`bit weights [2] or additional redundant bits [3] within the DAC
`have allowed errors made by strobing the comparator latch be-
`fore the DAC has fully settled to be corrected. This built in toler-
`ance to incomplete DAC settling has allowed the time allocated
`to DAC settling to be reduced.
`Further improvements in SAR conversion rate have been
`achieved by determining 2 or more bits per bit trial by either
`using multiple DACs and comparators [4] or a single DAC and
`a low resolution flash ADC [5]. The 6-bit ADC described in [4]
`uses 3 DACs and 3 comparators to generate and test the 3 levels
`required to determine 2 bits each bit trial. However, different
`comparator offset errors contribute directly to the non-linearity
`of the SAR ADC and as a result this approach has been limited
`to low to medium resolution ADCs. In [6] an RA is used to
`attenuate the linearity errors of a 4-bit flash ADC. A single DAC
`is used to generate a residue that is amplified by a RA before
`being converted by this flash ADC. The linearity errors of the
`flash ADC are attenuated by the RA gain (when referred to the
`input of the ADC) and this then allows a higher resolution to be
`achieved, in this case 14-bits. One drawback of this approach
`is that the RA is within the successive approximation loop and
`must be allowed to settle to sufficient accuracy each bit trial.
`This paper describes an 18-bit ADC that uses a RA to amplify
`a single residue generated by DACs within a primary SAR ADC.
`This amplified residue is then sampled and converted by a sec-
`ondary SAR ADC. The results from the 2 ADCs are combined
`to produce a final result. The primary ADC uses 4 comparators
`and the secondary ADC that converts the RA output uses a 4
`level flash ADC to allow 2 bits to be determined during each
`(but the last) bit trial. The settling delay associated with the RA
`
`0018-9200/$26.00 © 2010 IEEE
`
`IPR2021-00294
`Xilinx, Inc. v. Analog Devices, Inc.
`Analog 2006
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`occurs just once per conversion rather than during each bit trial
`as in [6]. The gain of the RA is set high enough to ensure that
`the linearity errors of the flash within the secondary ADC, when
`referred to the ADC input, are typically less than 1 LSB at the
`18-bit level. This architecture is similar to the pipeline of con-
`ventional successive approximation converters described in [7]
`except in this work 2 bits are determined during all but the last
`bit trial.
`Section II starts by describing why SAR ADCs exhibit high
`accuracy and low power but are relatively slow. Multi-bit bit
`trials, redundancy and pipelining techniques are then discussed
`that can be used to increase the speed of SAR ADCs. Section III
`describes the architecture of the ADC and Section IV describes
`the implementation of the individual circuit blocks. Section V
`presents the measurement results and Section VI concludes the
`paper.
`
`II. BACKGROUND INFORMATION
`
`Fig. 1. Conversion cycle for 4-b ADC with 2 bits determined each bit trial.
`
`A. Successive Approximation Converters
`
`Traditional SAR ADCs are known to be linear and power
`efficient but, due to the serial way in which each bit is deter-
`mined, are not architected for high throughput rate. Their lin-
`earity arises from the way that the comparator is used to simply
`determine the sign of the DAC output relative to the input. As
`long as the comparator does not exhibit hysteresis or any other
`memory effects and the DAC is given sufficient time to fully
`settle, the DC linearity of the converter is determined solely by
`the linearity of the DAC. This contrasts with pipeline converters
`where the linearity and gain error of the RA, particularly in the
`first MDAC stage, also contribute to the non-linearity of the con-
`verter.
`The high power efficiency that has been achieved with SAR
`ADCs is mainly due to the lack of any feedback amplifiers
`within the architecture. In low resolution converters the com-
`parator regenerative latch typically takes no quiescent power.
`In medium and high precision converters the latch is preceded
`by one or more preamps that reduce the input referred offset and
`noise of the latch [8]. However these preamps do not operate in
`feedback, as the precise gain of the preamp does not need to
`be controlled and as a result they can be implemented in a very
`simple and power efficient manner.
`
`Fig. 2. Code transitions for 4-b ADC with offset applied to centre comparator.
`
`in the overall transfer function, different comparator offsets in
`a multi-bit SAR ADC now directly degrade the linearity of the
`converter.
`
`C. Redundancy
`
`B. Multi-Bit Successive Approximation ADCs
`
`Unlike pipelined converters, traditional SAR ADCs only de-
`termine one bit per quantizing time step. By using multiple
`comparators, more than one bit can be determined at each trial
`step. Fig. 1 shows an example of a conversion cycle for a 4-bit
`SAR converter where 2 bits are determined during each of the
`2 bit trials. Three DACs and three comparators can be used to
`generate and test the 3 different test levels. Fig. 2 shows the
`code transitions for the same converter with an offset added to
`the comparator that tests the centre level of each search space
`during both bit trials. This offset has the effect of producing un-
`even code widths in the ADC transfer function. Unlike a tradi-
`tional SAR ADC, where comparator offset only gives an offset
`
`To allow correct conversion with incomplete DAC settling, it
`or with non-con-
`is known to use a DAC with a
`stant radix, by including extra redundant bits. Fig. 3 shows an
`example conversion cycle of the 4-bit converter of Fig. 1 adapted
`to provide extra range during the second bit trial Trial2, by
`adding a redundant level D0r. The input is at a voltage equiva-
`lent to 4.25 LSB. To allow correction of settling errors of either
`sign, all the test thresholds during the last bit trial have been
`shifted down by half a LSB. The DAC that generates the 0100
`when the comparator is
`test level during Trial1 is still above
`strobed and so this level is incorrectly rejected. During Trial2,
`the extra range provided by the redundant bit D0r allows this
`being correct to within
`error to be recovered: The result of
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`HURRELL et al.: AN 18 b 12.5 MS/s ADC WITH 93 dB SNR
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`Fig. 3. Conversion cycle with redundant test level added during Trial2.
`
`the resolution of the converter. Without redundancy, just D1 and
`D0 would be kept, giving a result of 3 which is incorrect.
`
`D. Pipeline of Successive Approximation ADCs
`Multi-bit bit trials can be used throughout a conversion as
`long as the offsets in the comparators (and between the different
`DACs generating the different test levels) are small relative to
`the LSB size of the converter. For this work, the converter has
`an 8.2 V peak to peak input; these comparators would need to
`be designed to have offsets less than 31 V.
`An alternative to making the comparator offsets smaller is
`to use an amplifier to increase the size of the signal presented
`to the comparators during a second part of the conversion. This
`can be achieved, without saturating the outputs of this amplifier,
`by presenting the amplifier with a small residue, equal to an
`accurate difference between the input and a coarse estimate of
`the input, determined during the first part of the conversion. The
`LSB size of the ADC, referred to the output of this RA, is now
`increased by the RA gain. The comparators in a multi-bit SAR
`ADC, used to convert the output of the RA, can now have offsets
`that are larger by a factor equal to the gain of the RA. With
`sufficient gain in the RA, multi-bit bit trials can then be used
`in both the first converter that generates the coarse estimate of
`the input required to generate the residue, and also in the second
`converter that converters the output of the RA.
`
`III. ADC ARCHITECTURE
`The architecture of this 18-bit pipelined multi-bit SAR ADC
`is shown in Fig. 4. ADC1 generates a coarse 10-bit estimate of
`the input over 5 bit trials and generates a small residue using the
`same sampling DACs used to perform this initial conversion.
`.
`The closed loop RA amplifies this residue by a factor of
`ADC2 samples and converts the output of the RA, generating
`a 9-bit result (with one bit of overlap across the RA output)
`over 5 bit trials. To correct for capacitor bit weight errors, the
`outputs from ADC1 and ADC2 are digitally corrected during
`the conversion, using error coefficients measured at final test
`and stored in non-volatile memory. The corrected outputs from
`
`Fig. 4. Block diagram of the 18-bit pipelined SAR converter (actual implemen-
`tation is differential).
`
`both ADCs are then merged and clipped to provide a final result.
`Dither is used within ADC2 to reduce the magnitude of DNL
`errors caused by offsets in the ADC2 comparators.
`Once ADC2 has sampled the RA output, the ADC1 sampling
`DACs are switched back to the ADC input to start acquiring the
`next input sample. The time constant of these DACs is just 1.7
`ns which is short enough to allow the input to be sufficiently
`acquired by the end of the ADC2 conversion. As a result, im-
`mediately after ADC2 has completed the current conversion,
`ADC1 sample switches can be opened and a new ADC1 conver-
`sion started. This contrasts with a traditional SAR ADC where
`a signal acquire phase is required between the end of one con-
`version and the start of the next.
`
`IV. CIRCUIT DETAILS
`
`A. ADC1
`A block diagram of ADC1 is shown in Fig. 5. The input
`voltage is sampled on to 4 identical sampling DACs (each with
`a capacitance of 6.25 pF) each with its own comparator. To min-
`imize distortion at higher input frequencies, the gates of the left
`hand side sampling switches are bootstrapped to the input [9],
`[10]. The 4 SARs differ and are designed to allow each of the 4
`DACs to be set to 4 different, but equally spaced levels during
`each ADC1 bit trial. While only 3 test levels are required to
`determine 2 bits, the 4th level provides redundancy, allowing
`some recovery from errors made in previous bit trials, such as
`errors due to incomplete DAC settling. The result from each bit
`trial, as indicated by the comparator outputs, is used to set the 2
`bits (plus the redundant bit) under test to the same state in all 4
`ADCs.
`Fig. 6 shows the DAC switch settings for the first bit trial.
`The different switch setting for the top 2 bits C16 and C17 in
`the lower 3 DACs allow the input to be tested against the (1/4),
`(1/2), and (3/4) full-scale levels as shown in Fig. 8. The top
`DAC is not used for the first bit trial. If, as in this example,
`the input lies between (1/2) and (3/4) full scale the C17 MSB
`and C16
`capacitor (driven terminal) will be switched to
`for the second bit trial, as shown in
`will be switched to
`Fig. 7. Capacitors C15, C14 and C14r will also now be set to
`4 different states within the 4 different DACs and along with
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`Fig. 5. Block diagram of ADC1 (actual implementation is differential).
`
`Fig. 7. Example DAC settings for ADC1 second bit trial.
`
`Fig. 6. DAC settings for ADC1 first bit trial.
`
`Fig. 8. Example ADC1 test levels for first 2 bit trials.
`
`, allow
`to
`the negative shift provided by switching
`the input to be tested against the new test levels also shown in
`is required to create
`Fig. 8. The negative shift provided by
`a bipolar correction range.
`For the third bit trial (not shown) C15 and C14 will be
`and C14r to
`. After the 5th bit trial,
`switched to
`when 10 bits will have been determined, the ADC1 smallest
`capacitors associated with the 5th bit trial are also set to the
`same state and the resulting identical residues from all 4 DACs
`are connected via the S1 switches to the input of the RA. Since
`all four sampling DACS are switched to the RA, the sampled
`thermal noise corresponds to the total capacitance of all four
`sampling DACs.
`One of the key architectural decisions was how many bits
`to do in ADC1. Fewer bits allow the offset specification for
`the ADC1 comparators to be relaxed. More bits give a smaller
`ADC1 residue which allows a higher RA gain and therefore a
`larger ADC2 LSB size. A larger ADC2 LSB size then relaxes
`
`the offset and noise requirements for the ADC2 comparators.
`The decision to do 10 bits within ADC1 was predicted to give
`the lowest power solution.
`
`B. Residue Amplifier
`A simplified schematic of the RA is shown in Fig. 9. The
`RA has a high closed loop gain of
`, set by the ratio of the
`total capacitance of all the sampling capacitors in the 4 ADC1
`DACs (256 unit capacitors) to that of the feedback capacitor C1
`(6 unit capacitors). This gain was the largest achievable with unit
`sized feedback capacitors that did not saturate the RA output
`stage. The corresponding feedback factor is small and is approx-
`imately equal to the reciprocal of the gain. To help compensate
`for this low feedback factor, the open loop gain of the RA is
`increased by preceding the transconductance amplifier with a
`preamp set to a gain of 20. The resulting open loop bandwidth is
`sufficient to provide full settling of the RA within 18 ns. The sta-
`bility of the amplifier is very sensitive to the gain of the preamp.
`Increasing the preamp gain reduces the frequency of the main
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`HURRELL et al.: AN 18 b 12.5 MS/s ADC WITH 93 dB SNR
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`Fig. 9. Residue Amplifier simplified schematic.
`
`non-dominant pole at the output of the first stage and at the same
`time increases the open loop bandwidth. Beyond a gain of 20,
`the reduction in stability starts to cause an increase in simulated
`settling time.
`Auto-zeroing is used to reduce offset and 1/f noise. During
`an auto-zero phase, switches S1 and S2 connect the input to a
`common mode voltage and switches S3 and S4 short the out-
`puts of the transconductance amplifier to its inputs. Opening
`these switches at the end of the auto-zero phase captures both
`the output referred offset of the preamp and the input referred
`offset of the transconductance amplifier on the inter-stage ca-
`pacitors C1 and C2.
`The RA nonlinearity and gain error are new error sources that
`do not exist in a traditional SAR ADC. However, since a full
`ten bits are determined within ADC1, the full scale range at
`the RA output is only 9 bits (allowing 1 bit of overlap across
`the RA). This considerably eases the gain and linearity require-
`ments of this amplifier. The closed loop gain of the RA is fac-
`tory trimmed. To ensure that this gain remains sufficiently stable
`with temperature, gain boosted cascodes have been used within
`the transconductance amplifier.
`In a traditional SAR ADC, the dominant noise sources are the
`comparator preamp and the input sampling DAC kT/C sampling
`noise. In this architecture the input sampling DAC noise contri-
`LSB rms remains the same but the other dominant
`bution
`LSB rms: As with a more con-
`noise source is now the RA
`ventional pipeline architecture the comparators only need pro-
`vide coarse results.
`
`Fig. 10. ADC2 block diagram (actual implementation is differential).
`
`as the DACs within ADC1. C1 along with associated switches
`S1–S2 is used to sample the input. During conversion the sam-
`pled value is capacitively combined with the output of the suc-
`cessive approximation DAC by capacitors C1 and C2 to pro-
`duce a signal proportional to
`at the input to the
`flash ADC. The ratio of 8:1 between C1 and C2 is required to
`match the LSB size of the successive approximation DAC to the
`LSB size at the output of the RA. The flash ADC result is used
`to the
`to set the Successive Approximation DAC output
`new trial value for the next bit trial. In a traditional SAR ADC,
`the resolution of each subsequent trial increases by a factor of
`2. Since 2 bits are being determined each trial, the resolution
`must increase by a factor of 4. To achieve this increase in reso-
`lution, the reference DAC output (after an initial full scale step
`for the first bit trial) decreases by a factor of 4 each subsequent
`trial. Four differently weighted capacitive summing networks
`are used to combine the outputs of the 2 DACs. The output of
`each summer is sensed by a comparator. At the flash ADC code
`transitions, the differential voltage at one of the 4 comparator
`inputs will be zero. The following relationships apply at these 4
`code transitions:
`
`C. ADC2
`
`Fig. 10 shows a simplified block diagram of ADC2 which
`converts the output of the RA. This architecture minimizes the
`loading on the RA by using a single capacitor C1 to sample the
`output of the RA. The loading on RA is further reduced by using
`a small value for C1. This can be tolerated since kT/C noise sam-
`pled on to this capacitor (and other ADC2 capacitors), when re-
`ferred to the ADC input, is divided by the gain of the RA. The
`architecture is based on [11] and uses just 2 DACs: a SAR DAC
`) converges on
`through the con-
`whose output (scaled by
`version; and a Reference DAC that provides the reference for a
`4 level flash ADC. Both DACs use the same reference voltage
`
`The architecture therefore allows the ‘error’ voltage
`, representing the difference between the new trial
`value (scaled) and Vin, to be tested against 4 equally spaced test
`levels. While only 3 levels are required to determine 2 bits, the
`fourth level, as in ADC1, provides some redundancy.
`
`D. Dither
`
`While offsets in the ADC2 auto-zeroed comparators were
`predicted to be at about the sub LSB level, these offsets will
`still cause uneven code transitions and degraded DNL. To avoid
`this degradation in DNL, dithering has been used within ADC2.
`Dithering randomly shifts the ADC transfer function from one
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010
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`Fig. 11. Die photograph.
`
`conversion to the next so that the offset of a particular com-
`parator will, over a number of conversions, affect all code tran-
`sitions equally [12]. The dither value is generated by a 5-bit
`pseudorandom binary sequence generator and is applied to a
`sub-DAC of the SAR DAC within ADC2. To avoid the dither
`perturbation used to shift the ADC2 transfer function directly
`degrading SNR, the dither value added to the sub-DAC is sub-
`tracted from the digitally corrected result, prior to clipping to
`produce the final result. A gain error in this sub-DAC will result
`in a mismatch between the dither added in the analog domain
`and the dither subsequently subtracted in the digital domain.
`This mismatch creates an error known as dither leakage which
`degrades SNR. Since the dither full scale range is just 31 LSB
`the gain accuracy of the sub-DAC resulting from raw capacitor
`matching is sufficient to avoid any significant dither leakage and
`consequent reduction in SNR. The effect of dithering on DNL
`is described in the Measurement Results section.
`
`Fig. 12. Measured INL and DNL at 12.5 MS/s with dither turned both on and
`off.
`
`V. MEASUREMENT RESULTS
`
`Fig. 13. Measured FFT with ADC sampling a 50 kHz input at 12.5 MS/s.
`
`The 18-bit pipeline ADC, consisting of a pipeline of 2
`multi-bit SAR ADCs, was implemented on a 0.25 CMOS
`process using PIP capacitors and both 2.5 V and 5 V PMOS
`and NMOS devices on a single monolithic die. The 5 V devices
`were used mainly in the input circuits and for the DAC switches
`and associated drivers to withstand voltages between 0 V and
`4.1 V in normal operation. Power consumption is 105 mW,
`excluding LVDS interface power. A photograph of the die
`is shown in Fig. 11. The die measures 3 mm by 2 mm. All
`reported measurements were made with the ADC signal inputs
`each driven by an external op-amp configured as a unity gain
`follower.
`Histogram testing with a 15 Hz sinusoidal input was used
`to measure INL and DNL with an average of 250 hits per
`code. INL and DNL with and without dithering are shown in
`LSB and DNL is
`Fig. 12. Without dithering INL is
`LSB. With dithering INL is improved to
`and more significantly, DNL is improved to
`LSB.
`Fig. 13 shows an FFT for the ADC operating at 12.5 MS/s
`with a 50 kHz input tone. SNR is 93 dB SFDR is 104 dB. Fig. 14
`
`Fig. 14. Measured SNR, SNDR and SFDR at 12.5 MS/s vs input frequency.
`
`shows SNR, SNDR and SFDR over a range of input signal fre-
`quencies. The ADC achieves an SNR of 93 dB at 50 kHz but
`this degrades to 91 dB at 1 MHz and 81 dB at 9.8 MHz.
`A figure of merit (FOM) allowing a fair comparison of the
`power (P) efficiency with which bandwidth (BW) and dynamic
`
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`HURRELL et al.: AN 18 b 12.5 MS/s ADC WITH 93 dB SNR
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`2653
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`Mueck, A. Ahmad, N. Srikanth, F. Ahmad, E. Byrne, R. Mau-
`rino, C. Price, C. Mcintosh, J. Gorbold, D. Robertson, and N.
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`[13] R. Schreier and G. C. Temes, Understanding Delta Sigma Data Con-
`verters. New York: Wiley-Interscience, 2005.
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`able: http://www.stanford.edu/~murmann/adcsurvey.html
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`modulator using class-C inverter,” in IEEE ISSCC Dig. Tech. Papers,
`Feb. 2008, pp. 490–630.
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`time ADC  modulator,” in IEEE ISSCC Dig. Tech. Papers, Feb.
`2010, pp. 298–299.
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`Abaskharoun, and D. Ribner, “A 100 mW 10 MHz-BW CT 
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`
`Christopher Peter Hurrell received the B.Eng.
`degree from Durham University, Durham, U.K., in
`1981.
`Since 1988 he has been a Design Engineer at
`Analog Devices, Newbury Berkshire, U.K., with
`particular interests in precision SAR converters and
`wideband delta sigma converters.
`
`Fig. 15. FOM of ADCs presented at ISSCC from data in [14].
`
`range (DR) are achieved is proposed and justified in [13]. The
`FOM is defined as
`
`For Nyquist rate converters, BW is half the sample rate. A
`scatter plot of FOM vs. bandwidth of ADCs presented at
`ISSCC from 1997 to 2010 is shown in Fig. 15, [14]. This ADC
`achieves the highest FOM for a converter with a BW greater
`than 2.2 MHz.
`
`VI. CONCLUSION
`
`An 18-bit 12.5 MS/s converter consisting of a pipeline of two
`multi-bit SAR ADCs has been presented. The ADC achieves a
`SNR of 93 dB with a 50 kHz input signal and INL and DNL
`LSB and
`LSB respectively. These per-
`better than
`formance metrics are similar to those of commercially available
`precision SAR ADCs operating at less than one third the output
`data rate of this converter. The good DC linearity achieved with
`this converter is believed to be due, at least in part, to the rela-
`tively small RA full-scale range of 9 bits. This small full-scale
`range avoids gain stability and linearity errors of the RA trans-
`lating into significant ADC linearity errors. Dither has been
`shown to be highly effective in reducing DNL errors created
`by offsets in the flash ADC used within the second SAR ADC.
`SFDR degrades faster with input frequency than was predicted
`by simulation, but is comparable with many other precision
`SAR ADCs. The key performance metrics of SNR and INL, re-
`quired for digital X-ray systems, are achieved with some margin
`at a conversion rate of 12.5 MS/s.
`
`ACKNOWLEDGMENT
`
`The authors would like to thank M. Lloyd for his excellent
`layout work and D. Hanlon who provided the efficient test so-
`lution. They would also like to acknowledge the valuable input
`and support from many within the Analog Devices ADC com-
`munity and in particular, M. Coln, G. Carreau, B. Amazeen, M.
`
`

`

`2654
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010
`
`Colin Lyden works for Analog Devices, Cork, Ire-
`land, where he is Director of Technology for Con-
`verters. Prior to joining Analog in 1999, he was CAD
`Director in Ireland’s National Microelectronics Re-
`search Centre.
`Mr. Lyden was recognized as an Analog Devices
`Fellow in 2007.
`
`Derek Hummerston graduated from Imperial Col-
`lege, London, U.K., in 1996 with an M.Eng. in elec-
`trical and electronic engineering.
`Since graduation he has been working for Analog
`Devices, Newbury, U.K., designing CMOS A/D con-
`verters for motor control, wireless infrastructure and
`medical applications.
`
`David Laing received the B.A. degree in indus-
`trial design,
`the HNC degree in electrical and
`electronic engineering, and the M.Sc. degree in mi-
`croelectronics systems design in 1990 from Brunel
`University, Middlesex, U.K.
`Currently, he is a Staff Engineer with the ADC De-
`sign Group, Analog Devices Newbury. He previously
`worked in system level EDA with Mentor Graphics
`and television systems development with Philips.
`
`Mark Vickery received the B.Eng. degree in engi-
`neering in 1988 from Oxford Polytechnic, Oxford,
`U.K.
`He has worked in cellular communications and in
`electro-optics before joining Analog Devices, New-
`bury, U.K., in 1995 where he is involved in the devel-
`opment of breakthrough analog-to-digital core tech-
`nologies. His primary interest is in the design and im-
`plementation of precision test platforms.
`
`