2040
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003
`
`A 12-bit 75-MS/s Pipelined ADC Using Open-Loop
`Residue Amplification
`
`Boris Murmann, Student Member, IEEE, and Bernhard E. Boser, Fellow, IEEE
`
`Abstract—Precision amplifiers dominate the power dissipation
`in most high-speed pipelined analog-to-digital converters (ADCs).
`We propose a digital background calibration technique as an en-
`abling element to replace precision amplifiers by simple power-
`efficient open-loop stages. In the multibit first stage of a 12-bit
`75-MSamples/s proof-of-concept prototype, we achieve more than
`60% residue amplifier power savings over a conventional imple-
`mentation. The ADC has been fabricated in a 0.35- m double-poly
`quadruple-metal CMOS technology and achieves typical differen-
`tial and integral nonlinearity within 0.5 LSB and 0.9 LSB, respec-
`tively. At Nyquist input frequencies, the measured signal-to-noise
`74 dB. The IC
`ratio is 67 dB and the total harmonic distortion is
`consumes 290 mW at 3 V and occupies 7.9 mm2.
`Index Terms—Analog-to-digital conversion, adaptive systems,
`calibration, CMOS analog integrated circuits,
`linearization
`techniques, parameter estimation.
`
`I. INTRODUCTION
`
`T HE pipelined analog-to-digital converter
`
`in
`(ADC)
`switched-capacitor CMOS technology is a popular ar-
`chitecture for high-speed data conversion in communication
`systems,
`imaging, ultrasound front-ends, and many other
`applications. Fuelled by aggressive device scaling in modern
`integrated circuit technology, practically attainable operating
`speeds of this converter have increased by almost two orders
`of magnitude in the last 15 years [1], [2]. In addition to the
`ever-growing demands in conversion bandwidth, low power
`dissipation, and compatibility with deep-submicron technology
`have emerged as important metrics in state-of-the-art designs.
`For the most part, this trend is explained by the increasing de-
`mand for portability, as well as recent efforts in system-on-chip
`(SoC) integration. In SoC implementations, data converters
`are embedded on the same chip with powerful fine-line digital
`signal processing, resulting in a limited budget for their total
`heat and power dissipation.
`Among the key building blocks in pipelined ADCs are the
`residue amplifiers that interface successive converter stages. Es-
`pecially in the converter front-end, these gain elements have
`to meet very stringent speed, noise, and linearity requirements
`and tend to dominate overall power dissipation. To address this
`issue, a variety of techniques have been developed to minimize
`amplifier power in pipelined ADCs. Among them, stage scaling
`[3], [4], optimization of the per-stage resolution [5]–[7], and
`
`Manuscript received April 13, 2003; revised July 6, 2003. This work was
`supported by Analog Devices and UC MICRO under Grant 01-006.
`The authors are with the Berkeley Sensor and Actuator Center, University
`of California, Berkeley 94720 USA (e-mail: bmurmann@eecs.berkeley.edu;
`boser@eecs.berkeley.edu).
`Digital Object Identifier 10.1109/JSSC.2003.819167
`
`amplifier sharing techniques [8], [9] are commonly used. In
`addition to their dominance in power consumption, it has also
`been recognized that residue amplifiers are most susceptible to
`complications that arise from continuing integrated circuit tech-
`nology scaling [10], [11]. For implementations in future deep-
`submicron processes, it is often predicted that limited supply
`headroom and low intrinsic device gain may lead to a relative
`power increase in such noise-limited precision analog circuit
`blocks [12], [13].
`This work explores an alternative to the residue amplifica-
`tion approach used in conventional pipelined ADCs. We pro-
`pose a digital background calibration technique as an enabling
`element to replace precision amplifiers by simple power-effi-
`cient open-loop stages. In the proposed implementation, a dig-
`ital postprocessor continuously estimates and removes errors
`from the imprecise and nonlinear open-loop gain. In fine-line
`technologies, this translation of the analog precision problem
`into the digital domain results in significant overall power sav-
`ings and may help overcome future scaling limitations. As an
`additional benefit, the use of simplified amplifiers may also
`help to increase the maximum conversion speed for a given
`technology.
`In this paper, we describe the implementation and measure-
`ment results of a 12-bit 75-MSamples/s pipelined ADC that uses
`open-loop residue amplification in its multibit first stage [14].
`In order to facilitate and expedite the evaluation of the pro-
`posed open-loop approach, we based our design on an existing
`commercially available pipelined ADC in 0.35- m CMOS tech-
`nology [15]. In Section II, we briefly review the architecture
`of this proof-of-concept prototype. Section III highlights the
`key differences between conventional pipeline stages and the
`open-loop approach proposed herein. In Section IV, we establish
`a first-order model for errors in the open-loop pipeline stage, fol-
`lowed by a methodology for their digital compensation in Sec-
`tion V. Section VI describes the digital background calibration
`technique that is used to continuously estimate and track the re-
`quired compensation parameters. Finally, Sections VII and VIII
`elaborate on implementation details and measured results.
`
`II. ADC ARCHITECTURE
`Fig. 1 shows a block diagram of the experimental converter,
`which closely resembles the architecture of the original design
`before reuse [15]. The pipeline core of this converter is parti-
`tioned into a multibit first stage with an effective resolution of
`three bits, followed by eight stages, each resolving one bit effec-
`tively, and finally, a 3-bit flash sub-ADC. Out of the 14 bits of
`raw data, the two least significant digits are used for calibration
`
`0018-9200/03$17.00 © 2003 IEEE
`
`Authorized licensed use limited to: OREGON STATE UNIV. Downloaded on March 12,2021 at 19:44:11 UTC from IEEE Xplore. Restrictions apply.
`
`IPR2021-00294
`Xilinx, Inc. v. Analog Devices, Inc.
`Analog 2009
`
`

`

`MURMANN AND BOSER: 12-BIT 75-MS/s PIPELINED ADC USING OPEN-LOOP RESIDUE AMPLIFICATION
`
`2041
`
`Fig. 1. ADC block diagram.
`
`Fig. 2. Conventional pipeline stage.
`
`purposes only and are truncated in the final conversion result.
`Stages 3–9 are implemented with 0.5 bit redundancy as stan-
`dard 1.5-bit stages. As explained in Section V, the second stage
`of this design was modified to use one full bit of redundancy.
`Compared to [15], the key modifications in the context of
`this work are the replacement of the stage-1 precision ampli-
`fier with an open-loop topology, and the addition of an off-chip
`digital postprocessor to correct for resulting conversion errors.
`Conceptually, the proposed scheme can be extended to multiple
`open-loop stages in the converter front-end. For simplicity and
`improved transparency, only the first and most critical converter
`stage is converted to open-loop amplification in this demonstra-
`tion vehicle.
`
`III. PIPELINE STAGE RESIDUE AMPLIFICATION
`A. Conventional Approach
`Fig. 2 shows a conceptual single-ended block diagram of
`the first pipeline stage in the original state-of-the-art reference
`design [15]. This circuit consists of a flash-type sub-ADC, a
`capacitive charge redistribution network, and a high-perfor-
`mance operational
`transconductance amplifier (OTA). The
`circuit operates in two main clock phases. During the sampling
`phase, the stage input signal
`is acquired. In a second phase,
`a residual charge packet, controlled by the local conversion
`result
`, is redistributed onto the feedback capacitor
`to
`produce the amplified stage residuum
`. In this conventional
`scheme, the use of electronic feedback around the OTA results
`in a precise and drift insensitive stage transfer function. As in
`many other electronic systems, feedback in this circuit serves
`two main purposes: 1) to mitigate the impact of device nonlin-
`earities in the OTA; and 2) to desensitize the overall transfer
`
`Fig. 3. Proposed open-loop pipeline stage.
`
`function to changes in ambient operating conditions, such as
`temperature. The cost of these desirable features is an excessive
`OTA voltage gain requirement. Since the effectiveness of feed-
`back is proportional to the system’s loop gain, high precision
`necessitates the use of complex high-gain OTA topologies. As
`is typical in high-resolution pipelined ADC front-ends, [15]
`uses a two-stage gain-boosted amplifier with an open-loop gain
`100 dB to meet the stringent design requirements. In fine-line
`technology with low intrinsic device gain and limited supply
`headroom, such amplifiers are hard to implement and tend to
`be power inefficient.
`
`B. Proposed Open-Loop Circuit
`Recently,
`the benefits of using open-loop structures in
`high-speed pipelined ADCs have been recognized and demon-
`strated. The 8-bit ADCs reported in [16] and [17] use open-loop
`current-mode residue amplification to achieve excellent power
`efficiency at high conversion speeds. In this work, we use
`a voltage-mode topology in conjunction with appropriate
`calibration techniques to push the applicability of open-loop
`structures into the 12-bit domain. Fig. 3 shows a conceptual
`schematic diagram of the proposed stage implementation.
`Except for the charge redistribution phase, the operation of
`this circuit is similar to the conventional topology described
`above. Unlike in the closed-loop implementation, the residual
`charge packet on the capacitive array is not redistributed onto
`a feedback capacitor, but remains in place to produce a small
`voltage at node
`. This residuum is fed into a resistively
`loaded differential pair to produce the desired full-swing
`residue voltage
`. In this modified circuit, the high gain
`requirement
`in the transconductor is dropped, resulting in
`a simple power-efficient amplifier topology with improved
`deep-submicron compatibility. These advantages, however,
`come at the price of several new nonidealities in the stage
`transfer function that have not been addressed in previous
`work. With particular focus on the implementation in stage 1
`of our design, the remainder of this paper will focus on the
`analysis of these errors, their digital domain compensation, and
`experimental verification of the approach.
`
`IV. ERROR MODEL FOR OPEN-LOOP FIRST STAGE
`With sufficient loop gain in the conventional implementation
`of Fig. 2, deviations of the stage transfer function from ide-
`ality are mostly due to capacitor mismatch and offset errors in
`the coarse sub-ADC. With the introduction of the simplified
`
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`

`2042
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003
`
`Fig. 4. Model for nonlinearity analysis.
`
`open-loop amplifier of Fig. 3, several additional error sources
`must be considered. Fig. 4 depicts an appropriate model for
`further analysis. Here, the capacitor array is replaced with its
`Thévenin equivalent, consisting of the total array capacitance
`and an equivalent voltage source
`that represents the
`local stage residuum before amplification. Ideally, the transfer
`to the output
`should be linear with a pre-
`function from
`, where
`is the effective stage resolution, taking
`cise gain of
`on a value of three in our particular implementation. In the cir-
`cuit of Fig. 4, the transfer function is neither linear nor precisely
`defined. The linear gain term from source to output is set by the
`and the
`amount of parasitic capacitive attenuation at node
`product, which typically cannot be accurately con-
`trolled. Furthermore, the amplification is nonlinear, primarily
`,
`due to three effects: 1) voltage dependence of the capacitor
`which represents the differential pair input load and parasitic
`junction capacitors; 2) nonlinearity in the resistive load; and 3)
`gain compression and mismatch in the differential pair. With re-
`spect to the tolerable errors in the first pipeline stage of this de-
`sign, none of the above nonlinearities are negligible. However,
`for a practical and optimized implementation, it is reasonable
`to assume that the differential pair dominates the overall cas-
`and
`. In this analysis, we
`cade nonlinearity that links
`therefore focus on this particular error component, noting that
`some of the distortion is actually caused by other nonidealities.
`Assuming an ideal square law transistor model and memoryless
`rela-
`nonlinearities, one can express the differential pair –
`tionship, graphically illustrated at the bottom of Fig. 4, through
`a power series of the form [18]
`
`(1)
`
`are the differential pair output and tail cur-
`and
`where
`is the quiescent point gate overdrive
`rent, respectively,
`is the current factor mismatch be-
`, and
`tween the two transistors. It should be noted that the expres-
`sion given in (1) overestimates distortion for short channel tran-
`
`Fig. 5. Differential pair nonlinearity error.
`
`sistors with velocity saturation. In principle, velocity saturated
`transistors can be modeled as resistively degenerated square law
`devices [19], which leads to a reduction in the expected nonlin-
`earity. However, for the qualitative arguments made in this sec-
`tion, (1) can be regarded as a sufficiently accurate conservative
`expression.
`Based on the derived nonlinearity model, we now investigate
`, which in turn
`on a reasonable choice for the gate overdrive
`for the differen-
`dictates the minimum required tail current
`tial pair. Fig. 5 shows the relative peak magnitude of the non-
`. In this graph, it is as-
`linear terms in (1) as a function of
`sumed that the peak-to-peak input voltage of the transconductor
`is 250 mV. This approximate value is dictated by the
`at node
`of 2 V,
`implementation, with a desired full-scale swing at
`an approximate stage gain of 8, and only a small amount of ca-
`pacitive attenuation from . For the second-order term in the
`%.
`diagram we assume a transistor matching of
`Shown as a horizontal line is the tolerable stage-1 residue error.
`feeds into a back-end with 9-bit effective resolution,
`Since
`an upper bound for the error is given by 1/2 LSB at the 9-bit level
`or approximately 0.1%.
`results
`As is apparent from the graph, choosing a large
`in small nonlinearity errors. However, in order to maintain con-
`in the differential pair,
`stant transconductance
`any increase in gate overdrive must be proportionally compen-
`sated by additional tail current. As a compromise, the goal in
`only reasonably large to yield
`this work was to choose
`a compact low-order model for stage nonlinearities. As illus-
`trated in Fig. 5, this is accomplished by choosing the gate over-
`drive voltage larger than 250 mV. Beyond this value, both the
`second- and fifth-order error contributions become negligible
`compared to the available error budget. For all practical values
`, however, cubic distortion is unavoidable and must be
`of
`compensated in the digital domain. With these considerations,
`Fig. 6 summarizes the overall model for the open-loop converter
`stage of this design. In addition to the discussed third-order non-
`linearity and the uncertainty in the linear gain term , offset
`errors in the amplifier and sub-ADC are added for complete-
`ness. Also present are capacitor matching errors, which result
`in nonideal sub-DAC levels. However, as in the implementation
`of [15], these errors did not exceed their tolerable budget and
`were not addressed in this work.
`
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`

`

`MURMANN AND BOSER: 12-BIT 75-MS/s PIPELINED ADC USING OPEN-LOOP RESIDUE AMPLIFICATION
`
`2043
`
`Fig. 6. Open-loop pipeline stage model with error sources.
`
`Fig. 7. Amplifier model with: (a) input referred nonlinearity, (b) output
`referred nonlinearity.
`
`V. DIGITAL DOMAIN ERROR COMPENSATION
`Based on the model established in the previous section,
`we now describe the digital domain correction mechanism
`for the stage-1 nonidealities under consideration, which are
`shown as shaded blocks in Fig. 6. Compensation techniques
`for the sub-ADC decision errors, amplifier offset, and linear
`gain error have been described in numerous publications. In
`and
`in stage 1,
`order to tolerate the additive errors
`we use a full bit of comparator redundancy in the succeeding
`second stage. Similar to the approach in [20], we thereby
`achieve overranging tolerance, allowing the stage-1 residue to
`exceed its full-scale boundaries. The linear stage gain error
`is addressed by digitally modifying the weight of sub-ADC
`decisions, as described in [21]. For this correction, a single
`parameter that captures the deviation of the actual gain from its
`ideal value must be known. In the remainder of this paper, we
`.
`will refer to this quantity as calibration parameter
`In addition to the existing correction techniques quoted
`above, we have developed a digital compensation scheme for
`the third-order nonlinear residue error caused by gain compres-
`sion in the open-loop amplifier. In Fig. 7(a), this nonideality is
`. Alternatively,
`modeled as a function of the amplifier input
`as illustrated in Fig. 7(b), the error can be modeled as a function
`. Through inversion of the overall cubic
`of the residuum
`(gain compression), the
`amplifier polynomial with
`following expression for the equivalent output referred error
`function in Fig. 7(b) can be found:
`
`with a single parameter
`
`(2)
`
`(3)
`
`Since the back-end stages of the converter produce a quan-
`, the error can be compen-
`tized digital representation of
`sated by operating on the digital back-end code, as shown in
`Fig. 8. This correction mechanism is accurate provided that the
`in Fig. 8) is small. This term can
`back-end conversion error (
`be decomposed into three components: 1) quantization error;
`2) a static input-referred offset; and 3) linear and nonlinear or
`code-dependent errors. In a practical functioning converter, the
`third component must inherently be kept small, either by design
`or some form of calibration. The static offset error component is
`
`Fig. 8. Digital nonlinearity compensation.
`
`tolerable in a conventional converter, usually due to the presence
`of comparator redundancy and digital correction arithmetic. For
`the converter described here, it can be shown that several tens
`of millivolts in back-end offset can be tolerated before the pro-
`posed code domain linearization becomes inaccurate. This re-
`quirement is easily met in the actual implementation of the pro-
`totype. As a last nonideality to be considered, the inherent quan-
`tization error of the back-end would limit the correction steps
`to 1-LSB increments. To overcome this problem, our converter
`uses two redundant back-end bits to provide for additional de-
`cision levels, resulting in sub-LSB nonlinearity correction.
`In a practical implementation of the nonlinearity correction
`scheme depicted in Fig. 8, the required two-dimensional cor-
`can be precomputed and stored in a
`rection function
`ROM lookup table. Since the expression of (2) describes smooth
`continuously varying data, incremental lookup or compression
`techniques [22] can be used to minimize the required memory
`size.
`Since the proposed converter uses open-loop amplification,
`any drift of errors is not attenuated by feedback. Consequently,
`and must not
`both of the required calibration parameters
`only be precisely determined, but also track variations caused by
`changing ambient conditions during converter operation. The
`digital background calibration algorithm described in the next
`section was designed to meet these requirements.
`
`VI. DIGITAL BACKGROUND CALIBRATION TECHNIQUE
`Background calibration of monolithic ADCs has been a pop-
`ular research topic since the mid-1990s [23]. In previous work,
`it was often argued that the key advantage of a continuous cali-
`bration mechanism is its transparency to the user, who no longer
`needs to schedule calibration cycles that would interrupt normal
`ADC operation. In the proposed converter, the calibration coef-
`ficients relate to temperature-sensitive open-loop amplifier co-
`efficients that may drift substantially in short time intervals and
`strictly dictate the implementation of a continuously tracking
`compensation approach.
`
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003
`
`Fig. 9. Pipeline stage with two-residue transfer characteristics.
`
`Fig. 10. Segment detail.
`
`A particularly interesting property of the technique de-
`scribed herein is that it does not require the generation of an
`analog domain test signal, unlike other background calibration
`approaches. Instead, the calibration is based on evaluation of
`signal statistics, similar to the technique described in [24].
`Conceptually, the estimation uses the fundamental property
`that perfectly linear systems at most scale, but never distort
`a signal’s amplitude distribution. Deviations from this ideal
`case can be used to obtain information about the presence and
`magnitude of any nonlinearity. In some sense, the (arbitrary)
`input amplitude distribution of the converter assumes the role
`of the calibration test signal.
`In this section, we describe the basic elements of the proposed
`calibration technique, followed by an overview of the complete
`digital postprocessing scheme and a brief discussion of its fun-
`damental properties and limitations.
`
`A. Two-Residue Characteristics
`One key ingredient in the proposed background calibration
`technique is the addition of a second, redundant residue mode as
`shown in Fig. 9. Through the addition of a simple digital logic
`block and one bit of extra resolution in the stage’s sub-ADC
`and sub-DAC, the open-loop converter stage can switch be-
`tween two distinct overlapping residue transfer functions. In
`principle, the two residues of Fig. 9 can be used interchange-
`ably and would yield identical conversion results in the case
`of ideal stage operation. The power penalty for the additional
`transfer function is low, since the redundant comparators needed
`in the sub-flash-ADC typically consume only a small fraction
`of the total stage power [4]. The redundant states needed in the
`sub-DAC can be generated at even lower cost by simply splitting
`up its unit elements. In designs with small unit capacitors, this
`may adversely affect the sub-DAC element matching. In the de-
`sign presented here, the minimum capacitor size used still met
`the precision requirements.
`
`B. Parameter Estimation From Residue Distances
`Fig. 10 shows a single enlarged segment of the overlapping
`gain compressive stage transfer characteristic. Also shown are
`and
`for two input voltages near
`the residue differences
`the center and edge of the segment, respectively. The digital
`linearity correction in the converter back-end operates on both
`
`. Perfect adjustment of
`residues, controlled by parameter
`maps both residues onto straight lines. In this case, the differ-
`ence between the two residues is constant and independent of
`. On the
`measurement location, consequently yielding
`indicates incom-
`contrary, a measurement of, e.g.,
`plete nonlinearity error cancellation. Based on this argument, it
`is conceptually possible to construct a recursive algorithm that
`by repeatedly mea-
`converges to the optimum solution for
`and
`.
`suring the two residue differences
`is found, and assuming ideal
`After the optimum value for
`sub-DAC operation, it can be seen from Fig. 10 that both
`and
`take on precisely 1/2 of the transition height of the lin-
`earized residue. Therefore, the distance estimates directly relate
`for linear gain error cor-
`to the required correction parameter
`rection, as described in [21].
`
`C. Statistics-Based Distance Estimation
`If it were possible to process constant input voltages using
`both characteristics, the distances could be directly determined
`from the individual back-end conversion results. In this work,
`we have developed a statistics based estimation technique that
`avoids the need for constant inputs and, therefore, allows cal-
`ibration in the background during normal converter operation.
`Fig. 11 illustrates the general concepts of the approach for the
`simplified case of a single residue segment and estimation of
`only. As a further simplification in this discussion, we assume
`that the input signal to the segment is a stationary and “white”
`discrete time random process, whose samples are described by
`a well behaved but otherwise arbitrary probability density func-
`tion (PDF).
`The distance estimation process is based on evaluating cu-
`mulative histograms of the digital back-end conversion results
`in Fig. 8). Fig. 11(a) introduces the basic concept of
`(
`a cumulative histogram. In this simple example, we consider
`only one of the two residue curves and one histogram bin at
`a particular code location . The cumulative histogram count
`is found by counting the number of samples seen
`in the back-end that are less than or equal to the reference code
`. Hence, the expected value of will be proportional to the
`total number of samples processed times the hatched area un-
`derneath the PDF, which represents the probability of an input
`.
`sample being below the code threshold
`
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`

`MURMANN AND BOSER: 12-BIT 75-MS/s PIPELINED ADC USING OPEN-LOOP RESIDUE AMPLIFICATION
`
`2045
`
`Fig. 12. Postprocessor block diagram.
`
`creasingly large sample sizes, the estimate approaches the true
`is approximately inversely propor-
`value. The variance of
`tional to the total number of samples processed until counter
`evaluation.
`
`D. Complete Algorithm
`Combining the concepts discussed in the previous sections,
`Fig. 12 shows a block diagram of the complete digital postpro-
`cessing system. The procedure described above is duplicated
`, located close to the residue
`to produce a second estimate
`transitions as depicted in Fig. 10. For the estimation process,
`the back-end data from all residue segments is combined. No
`distinction is made between the 16 segments; only bottom and
`top segment contributions are processed separately as required
`is fed into an adap-
`by the algorithm. The difference
`tive least mean square (LMS) loop [25], which assumes the task
`. The mean value of
`of finding and tracking the parameter
`is forced to zero through the presence of the accu-
`mulator in this feedback loop, resulting in optimum digital lin-
`is obtained through recursive
`earization. Similarly, parameter
`.
`mean filtering on the estimator
`
`E. Properties and Limitations
`An important property of the calibration technique is that the
`required analog circuit modifications result in only minor over-
`head and introduce no additional accuracy requirements or pre-
`cision elements in the pipeline stage. One key requirement for
`proper operation of the algorithm, however, is that the nonlin-
`earity coefficients in each segment must be identical. Mathemat-
`ically, the stage transfer function must be described by a family
`of power series of the form
`
`(4)
`
`is the local conversion result, and
`In this expression,
`represents the DAC-code-dependent position of
`axis of Fig. 9. Equation
`each transfer segment along the
`(4) simply restates an assumption made in the block diagram
`of Fig. 9: The sub-DAC must operate on the stage input in a
`purely additive manner (ideal summing block). Nonlinearity
`is only present in the stage gain element. Analysis shows that
`this requirement is met in the implementation of this design
`
`Fig. 11. Statistics-based distance estimation. (a) Cumulative count from one
`segment. (b) Random split. (c) Distance estimate from closest cumulative count.
`
`Fig. 11(b) illustrates the next fundamental concept of the
`technique. For each input sample to the segment, a binary
`random number generator (RNG) chooses with equal proba-
`bility and independent of the sample value between one of the
`two residue modes. Consider now a second cumulative code
`that is associated with the top residue as shown in
`bin
`Fig. 11(b). For simplicity, assume that the decision level of
`precisely coincides with
`(the decision level of code
`code
`). Due to the RNG modulation, the count
`of Fig. 11(a)
`is now split into two histogram bins. Analysis shows that the
`, but due to randomness in the
`expected value in each bin is
`modulation, particular outcomes will vary and most often not
`split. This fact is illustrated as slightly
`result in a perfect
`imbalanced counts in Fig. 11(b).
`Consider now the setup of Fig. 11(c), in which several ad-
`ditional cumulative code bins have been added around code .
`With the random modulation in progress, and after processing
`a large number of samples, the top bins are evaluated and com-
`. From the closest match, the
`pared to the reference count
`is obtained [in the example of Fig. 11(c),
`distance estimate
`]. It can be shown that
`is an asymptotically
`, i.e., for in-
`unbiased estimate of the true residue distance
`
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`2046
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003
`
`Fig. 13. Stage-1 implementation.
`
`mainly for two reasons: 1) linear capacitors in the switched
`capacitor DAC result in an “ideal” linear summing node; and
`2) one single amplifier is used to produce all residue segments,
`which therefore have identical power series descriptions that
`terms [see (4)].
`differ only in their
`As explained above, the proposed algorithm operates contin-
`uously in the background, without interrupting normal converter
`operation. However, certain restrictions apply to the amplitude
`distribution of the converter input signal for successful cali-
`bration. Through qualitative arguments from the illustration in
`Fig. 11, it can be seen that the algorithm fails if the input signal
`is not sufficiently “busy” around the input voltages at which the
`distance estimates are taken. Inactivity results in a flat cumu-
`lative histogram with indistinguishable bins in the top counter
`array. It can be argued that this property only mildly affects
`the practicality of the approach. First, insufficient amplitude ac-
`tivity can be easily detected, making it possible to avoid miscal-
`ibration due to low-swing quasi-dc input signals. Furthermore,
`the estimation process in this work combines back-end data
`from 16 segments, so that activity spanning only about 1/16th
`of the converter’s full-scale range is sufficient for calibration.
`A more fundamental constraint exists in the tradeoff between
`the accuracy and tracking time constants in the LMS loops.
`Bounds on the tolerable variance in the correction parameters
`and
`, which in turn
`necessitate small loop coefficients
`limits the achievable tracking speed. Assuming busy inputs, our
`system shows time constants of approximately 100–200 ms,
`which is sufficient to track, e.g., ambient temperature variations,
`slow changes in supply voltage, and device aging effects. Mea-
`sures to reduce the sensitivity of the open-loop pipeline stage to
`potentially faster variations are briefly summarized in the next
`section.
`
`VII. CIRCUIT DETAILS
`A. Open-Loop Pipeline Stage
`Fig. 13 shows a schematic of the circuit used in the first stage
`of this converter. As in [15], a 4-bit flash converter is used to
`
`generate the coarse local conversion result. This sub-ADC is
`shared between the two implemented residue modes. A logic
`block, controlled by the random number generator bit RNG,
`assigns even/odd flash transitions to cause the appropriate
`breakpoints in either transfer function mode (Fig. 9). The
`sampling and DAC capacitor network of this circuit is identical
`to the implementation in [15], with the exception that here the
`16 poly–poly capacitors drive a resistively loaded open-loop
`amplifier. Based on the considerations outlined in Section IV,
`the quiescent point gate overdrive of the differential pair was
`chosen slightly larger than 250 mV.
`As a conservative measure, cascode devices were included
`in the amplifier to yield improved power supply rejection. A
`pi-load configuration was chosen to decouple the choice of
`common mode output level from differential gain requirements.
`Replica tail biasing [26] was used to improve the stage’s input
`common-mode rejection ratio.
`Of particular importance in the presented open-loop stage are
`appropriate design techniques for thermal desensitization. Our
`design uses
`replica biasing to reduce the overall sensi-
`tivity to ambient temperature changes. On the layout level, de-
`diffusion load resistors with
`vice interleaving and the use of n
`low thermal resistance aim to mit