Trials@uspto.gov
`571-272-7822
`
`Paper 9
`Date: June 10, 2021
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`XILINX, INC. and XILINX ASIA PACIFIC PTE. LTD.,
`Petitioner,
`v.
`ANALOG DEVICES, INC.,
`Patent Owner.
`
`IPR2021-00294
`Patent 7,274,321 B2
`
`
`
`
`
`
`
`
`
`Before SCOTT A. DANIELS, GEORGIANNA W. BRADEN, and
`JESSICA C. KAISER, Administrative Patent Judges.
`DANIELS, Administrative Patent Judge.
`
`DECISION
`Denying Institution of Inter Partes Review
`35 U.S.C. § 325 and 35 U.S.C. § 314
`
`
`
`
`
`
`
`
`571-272-7822
`
`Paper 9
`Date: June 10, 2021
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`XILINX, INC. and XILINX ASIA PACIFIC PTE. LTD.,
`Petitioner,
`v.
`ANALOG DEVICES, INC.,
`Patent Owner.
`
`IPR2021-00294
`Patent 7,274,321 B2
`
`
`
`
`
`
`
`
`
`Before SCOTT A. DANIELS, GEORGIANNA W. BRADEN, and
`JESSICA C. KAISER, Administrative Patent Judges.
`DANIELS, Administrative Patent Judge.
`
`DECISION
`Denying Institution of Inter Partes Review
`35 U.S.C. § 325 and 35 U.S.C. § 314
`
`
`
`
`
`
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`
`INTRODUCTION
`I.
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. (collectively “Petitioner”
`or “Xilinx”) filed a Petition to institute an inter partes review of claims 1–3,
`5, 6, 8, 13–16, and 18 of U.S. Patent No. 7,274,321 B2 (“the ’321 patent”).
`Paper 2 (“Pet.”). Analog Devices, Inc. (“Patent Owner” or “Analog”) filed a
`Preliminary Response. Paper 8 (“Prelim. Resp.”).
`Under 35 U.S.C. § 314(a), an inter partes review may not be instituted
`“unless . . . there is a reasonable likelihood that the petitioner would prevail
`with respect to at least 1 of the claims challenged in the petition.” For the
`reasons provided below, we deny institution of inter partes review.
`Real Parties in Interest
`A.
`Petitioner states that the real parties-in-interest are Xilinx, Inc. and
`Xilinx Asia Pacific Pte. Ltd. Pet. 107.
`Patent Owner states that Analog Devices, Inc. is the real party-in-
`interest in this proceeding. Paper 5, 2.
`Additional Proceedings
`B.
`The parties indicate that the ’321 patent has been asserted against
`Petitioner in Analog Devices, Inc. v. Xilinx, Inc. and Xilinx Asia Pacific Pte.
`Ltd., Case No. 1:19-cv-02225 in the United States District Court for the
`District of Delaware. Pet. 107; Paper 5, 2. Patent Owner further indicates
`that Petitioner filed petitions for inter partes in the following proceedings:
`
`2
`
`
`
`6,900,750 (“the ’750 patent”)
`
`7,286,075 (“the ’075 patent”)
`
`U.S. Patent No.
`10,250,250 (“the ’250 patent”)
`8,487,659 (“the ’659 patent”)
`7,012,463 (“the ’463 patent”)
`7,719,452 (“the ’452 patent”)
`
`IPR2021-00294
`Patent 7,274,321 B2
`Case No.
`IPR2020-01210
`IPR2020-01219
`IPR2020-01336
`IPR2020-01561
`IPR2020-01483
`IPR2020-01484
`IPR2020-01564
`IPR2020-01559
`Paper 5, 2.
`The ’321 Patent
`C.
`The ’321 patent describes problems and improvements related to
`analog to digital converters (“ADC”). Ex. 1001, Title, Abstract, 1:11–15,
`2:1–19, 2:42–47, 3:8–11. More specifically, the ’321 patent describes a
`pipelined ADC in which the analog to digital conversion is done in first and
`second stages, such that a complete conversion need not be performed
`before starting the next analog to digital conversion. Id. at 3:8–12. For
`example, the ’321 patent describes an ADC with first and second converter
`cores, in which “the second converter core could be finishing an analog to
`digital conversion whilst the first converter core is switched to a tracking
`mode such that it acquires the next analog sample to be converted.” Id.
`at 3:12–16; see id. at 1:6–9.
`Figure 1 of the ’321 patent is reproduced below.
`
`3
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`
`
`Figure 1 depicts a pipelined converter architecture according to an
`embodiment of the ’321 patent. Id. at 7:18–19, 7:36–37. As shown in
`Figure 1, the architecture includes two converter cores 2 and 4 provided in
`series and operating in a collaborative manner. Id. at 7:19–23, 8:9–11.
`Converter cores 2 and 4 are preferably implemented as successive
`approximation (“SAR”) converters, which allows each converter core to be
`relatively accurate without incurring the power and input capacitance costs
`of using a flash converter. Id. at 7:19–23, 30–35.
`In operation, converter cores 2 and 4 are responsive to controllers 12
`and 12a, respectively. Id. at 7:38–40. Controllers 12 and 12a are connected
`to comparators 14 and 14a, respectively, each of which has an input
`connected to converter input 16 or 16a. Id. at 7:39–42. Converter input 16
`and 16a receive a sampled version of the analog signal to be converted from
`a sample and hold circuit. Id. at 7:42–43. Controller 12 or 12a successively
`sets a digital word which is converted by digital to analog converter
`
`4
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`(“DAC”) 10 or 10a. Id. at 7:43–45. The output is compared to the input
`signal by comparator 14 or 14a, such that the bit is kept if the magnitude of
`the signal from the DAC is less than the magnitude of the signal to be
`converted, otherwise the bit is discarded. Id. at 7:47–50.
`Once converter core 2 has digitized its portion of the signal, it sets
`DAC 10 to output the result in analog form to subtracting input 18 of
`summer 20. Id. at 7:55–58. Adding input 22 of summer 20 receives the
`analog signal to be digitized from input 16. Summer 20 forms a residue—
`defined as the difference between the input voltage at input 16 and the
`output voltage from converter core 2—which is held at output 24 and used
`as the input voltage to converter core 4. Id. at 7:58–7:67. Each controller 12
`and 12a sends its digital word on outputs 13 and 13a, respectively to
`combiner 30 which combines the results to produce a single output word 32
`representing a digital version of the analog input signal. Id. at 8:4–8.
`Figure 2 of the ’321 patent, reproduced below, shows how a plurality
`of conversion engines operate collaboratively within one of the converter
`cores shown in Figure 1.
`
`5
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`
`
`Figure 2 depicts a plurality of conversion engines operating collaboratively
`within a SAR converter core according to an embodiment of the ’321 patent.
`Id. at 6:62–65, 8:12–14. As shown in Figure 2, converter core 40 includes
`ADC conversion engines E1–E4, each of which communicates with
`controller 12, which receives an output from a comparator provided
`internally within each of the conversion engines E1–E4. Id. at 8:21–25.
`Each conversion engine E1–E4 is connected via designated control bus b1,
`b2, b3, or b4 to controller 12 for controlling the switches associated with
`each of the capacitors in the respective conversion engine. Id. at 8:25–27.
`Each conversion engine E1–E4 is also connected to analog input 44. Id.
`at 8:28–29.
`
`6
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`Figure 3 depicts a conversion process using either of the converter
`cores according to an embodiment of the ’321 patent.
`
`
`Figure 3 of the ’321 patent depicts a process for performing successive bit
`trials within a converter core for converting an 8 bit word whose value
`corresponds to “00110010.” Id. at 8:33–36; see also id. at 1:34–38. As
`shown in Figure 3, during trial 1: at line E1(l), first converter E1’s two most
`significant bits are set to “10” and the rest to “0”; at line E2(1), converter
`E2’s most significant bits are set to “11” and the rest to “0”; and at line
`E3(1), converter E3 most significant bits are set to “01” and the rest to “0.”
`Id. at 8:44–52. The three converters segment the conversion space into four
`distinct ranges: R0(1) spans the lowermost quarter of the conversion
`space—from “00000000” to “01000000”; R1(1) spans from “01000000” to
`“10000000”; R2(1) spans from “10000000” to “11000000”; and R3(1) spans
`from “11000000” to “11111111”. Id. at 8:53–63. At the end of the first
`trial, the outputs of the comparators are checked and the controller notes that
`the analog input value is less than threshold values E1(1), E2(1) and E3(1)
`
`7
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`and, thus, lies within the range R0(1). Id. at 8:64–67, 9:1–3. The first two
`bits in the trial are, therefore, set to “00” and the trial then progresses to the
`second trial. Id. at 8:67–9:1.
`Trial 2 conducts further investigations only within the range R0(1): at
`line E1(2), the next two bits of converter E1 are set to “10” such that the
`value under test becomes “0010”; at line E2(2), the second conversion
`engine’s next two bits are set to “11” such that it tests the word “0011”; and
`at E3(2), the third conversion engine’s next two bits are set to “01” such that
`it tests the word “0001.” Id. at 9:4–11. Each conversion engine is now
`checking a conversion range—R0(2), R1(2), R2(2), or R3(2)—that is one
`quarter the size of the previous conversion range, R0(1). Id. at 9:14–16.
`Conversion engine E3 is checking conversion range R0(2); range R1(2) is
`defined between the decision thresholds for conversion engines E3 and E1;
`range R2(2) is defined between the decision threshold for conversion
`engines E1 and E2; and range R3(2) is defined between the decision
`threshold for conversion engine E2 and the decision range determined by the
`previous conversion. Id. at 9:16–26. At the end of the second trial, the
`controller determines from the output of each of the conversion engines that
`the analog value was above the values determined by the next two bits for
`each of the engines; so, the third and fourth bits in the trial are set to “11”.
`Id. at 9:26–30.
`Trial 3 occurs only within the decision range R3(2) and, again, the
`three thresholds are set at the quarter, half, and three quarter distances
`between the top and bottom of that decision range. Id. at 9:31–34. As
`shown in Figure 3, each of these thresholds, E1(3), E2(3), and E3(3), is
`above the analog value. Id. at 9:34–38. The controller, therefore, discards
`
`8
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`each of these bits and determines that the word converted so far is “001100”.
`Id. at 9:38–40.
`After trial 3, the ADC converters may switch operational modes and
`move to a second mode where each ADC converter works independently as
`a single SAR converter. Id. at 9:52–57. The final result is determined by
`combining the digital outputs of individual ADCs. Id. at 9:58–59.
`Illustrative Claim
`D.
`As noted previously, Petitioner challenges claims 1–3, 5, 6, 8, 13–16,
`and 18. Of the challenged claims, claims 1, 14, 15, and 16 are independent.
`Each of dependent claims 2, 3, 5, 6, 8, and 13 depend ultimately from
`claim 1; claim 18 depends from claim 16. Claim 1 is reproduced below with
`certain limitations of interest highlighted:1
`1 [pre] A analog to digital converter, comprising:
`1 [a] an input for receiving an input signal to be digitised;
`1 [b] a first converter core for performing a first part of an
`analog to digital conversion,
`1 [c] said first converter core comprising at least three
`switched capacitor analog to digital conversion engines
`operating in parallel and in a co-operative manner and
`1 [d] for outputting a first digital result and an analog
`representation of the first digital result;
`1 [e] a first residue generator for generating a first residue as a
`difference between the input signal and the analog
`representation of the first digital result;
`1 [f] a second converter core for performing a second part of the
`analog to digital conversion by converting the first residue;
`1 [g] wherein the analog to digital further comprises a
`controller for controlling the operation of the engines such that
`
`1 We reference Petitioner’s bracketed labels and breaks in claim 1. See
`Pet. 21–38.
`
`9
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`the engines co-operate to perform a successive approximation
`search, and
`1 [h] wherein the first converter core is further operable to act
`as the first residue generator.
`Ex. 1001, 17:2–22 (emphases added).
`Prior Art and Asserted Challenges
`E.
`Petitioner contends that the challenged claims are unpatentable over
`the following specific challenges. 2
`Claim(s)
`Challenged
`1, 2, 5, 6, 8,
`13–16
`3, 18
`1, 2, 5, 6, 8,
`13–16
`3, 18
`
`Ground
`
`35 U.S.C. §
`
`Reference(s)/Basis
`Dabbagh-Sadeghipour, 3
`Fetterman4
`Dabbagh-Sadeghipour,
`Fetterman, Hester5
`Guillen, 6 Cai7
`Guillen, Cai, Hester
`
`1
`
`2
`
`3
`4
`
`103(a)
`
`103(a)
`
`103(a)
`103(a)
`
`
`
`PRELIMINARY ISSUES
`II.
`A. Discretionary Denial under 35 U.S.C. § 325(d)
`Patent Owner asks that we exercise our discretion under 35 U.S.C.
`§ 325(d) not to institute a trial because the prior art relied upon by
`Petitioner—Dabbagh-Sadeghipour, Fetterman, Guillen, and Cai—is
`
`
`2 Petitioner supports its challenge with the opinion testimony of Dr. Mark N.
`Horenstein (Ex. 1002).
`3 Ex. 1004, Khosrov Dabbagh-Sadeghipour et al., A New Architecture for
`Area and Power Efficient, High Conversion Rate Successive Approximation
`ADCs, 2nd Annual IEEE Northeast Workshop on Circuits and Systems,
`253–256 (2004).
`4 Ex. 1006, US Patent No. 6,404,364 B1 (June 11, 2002).
`5 Ex. 1007, US Patent No. 5,675,340 (Oct. 7, 1997).
`6 Ex. 1008, US Patent No. 3,710,377 (Jan. 9, 1973).
`7 Ex. 1009, US Patent No. 6,879,277 B1 (Apr. 12, 2005).
`
`10
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`cumulative to Bae, Davies, Fossum, or Tai, which were cited or relied upon
`by the Examiner during prosecution of the application that became the ’321
`patent. Prelim. Resp. 3, 21, 26–31, 38, 43–47.
`For the reasons discussed below, we are persuaded to exercise our
`discretion not to institute inter partes review.
`35 U.S.C. § 325(d) states, in relevant part: “In determining whether to
`institute or order a proceeding under this chapter, chapter 30, or chapter 31,
`the Director may take into account whether, and reject the petition or request
`because, the same or substantially the same prior art or arguments previously
`were presented to the Office.” The Board uses a two-part framework for
`evaluating arguments under § 325(d):
`(1) whether the same or substantially the same art
`previously was presented to the Office or whether the same or
`substantially the same arguments previously were presented to
`the Office; and
`(2) if either condition of first part of the framework is
`satisfied, whether the petitioner has demonstrated that the Office
`erred in a manner material to the patentability of challenged
`claims.
`Advanced Bionics, LLC v. MED-EL Elektromedizinische Geräte GmbH,
`IPR2019-01469, Paper 6 at 8 (PTAB Feb. 13, 2020) (precedential). “[T]he
`Becton, Dickinson factors provide useful insight into how to apply the
`framework under 35 U.S.C. § 325(d).” Id. at 9 (footnote omitted). The non-
`exclusive Becton, Dickinson factors are:
`(a) the similarities and material differences between the
`asserted art and the prior art involved during examination;
`(b) the cumulative nature of the asserted art and the prior
`art evaluated during examination;
`
`11
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`(c) the extent to which the asserted art was evaluated
`during examination, including whether the prior art was the basis
`for rejection;
`(d) the extent of the overlap between the arguments made
`during examination and the manner in which Petitioner relies on
`the prior art or Patent Owner distinguishes the prior art;
`(e) whether Petitioner has pointed out sufficiently how the
`Examiner erred in its evaluation of the asserted prior art; and
`(f) the extent to which additional evidence and facts
`presented in the Petition warrant reconsideration of the prior art
`or arguments.
`Becton, Dickinson & Co. v. B. Braun Melsungen AG, IPR2017-01586,
`Paper 8 at 17–18 (PTAB Dec. 15, 2017) (precedential as to § III.C.5, first
`paragraph). Becton, Dickinson factors (a), (b), and (d) relate to the first part
`of the Advanced Bionics framework (whether the same or substantially the
`same art or arguments previously were presented to the Office), and Becton,
`Dickinson factors (c), (e), and (f) relate to the second part of that framework
`(previous Office error). Advanced Bionics, IPR2019-01469, Paper 6 at 9–
`11.
`
`Grounds 1 and 2—Challenges based on Dabbagh-
`1.
`Sadeghipour (Ex. 1004) and Fetterman (Ex. 1006)
`Petitioner argues that claims 1, 2, 5, 6, 8, and 13–16 of the ’321 patent
`would have been obvious over Dabbagh-Sadeghipour and Fetterman and
`that dependent claims 3 and 18 would have been obvious over Dabbagh-
`Sadeghipour, Fetterman, and Hester. Pet. 14–63. Petitioner contends that
`Dabbagh-Sadeghipour was never considered by the examiner and teaches
`ADC engines operating in parallel and in a co-operative manner to “form a
`flash-SAR (i.e., ‘flash-like’) ADC.” Id. at 15.
`
`12
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`As discussed below, and having reviewed the information and
`evidence provided by Petitioner and Patent Owner, including the relevant
`portions of the testimony of Dr. Horenstein (Ex. 1002), we are persuaded, on
`this record, to exercise our discretion under 35 U.S.C. § 325(d) to deny the
`Petition because Dabbagh-Sadeghipour and Fetterman are cumulative to the
`prior art already considered and applied by the Office, and because
`Petitioner has not explained how the Examiner erred in determining the
`patentability of the challenged claims.
`a) Dabbagh-Sadeghipour
`Dabbagh-Sadeghipour describes “[a] new high-speed successive
`approximation Analog-to-Digital Converter architecture.” Ex. 1004, 253.
`Dabbagh-Sadeghipour describes that “[t]wo bits extraction in each clock
`cycle is the key idea to double the conversion speed.” Id. Figure 2 of
`Dabbagh-Sadeghipour is illustrative and is reproduced below.
`
`
`
`13
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`Figure 2 of Dabbagh-Sadeghipour shows a two bits per clock cycle
`extraction architecture. Id. at 254. As shown in Figure 2, the architecture
`contains:
`
`(1) a sample-and-hold circuit for sampling analog input
`voltage Vin;
`(2) three internal digital-to-analog converters (DAC_A,
`DAC_B, and DAC_C) for generating analog voltages Vdac_A,
`Vdac_B, and Vdac_C;
`(3) a flash-like three comparator structure for comparing
`the sampled Vin to Vdac_A, Vdac_B, and Vdac_C, respectively; and
`(4) a Successive Approximation Register (SAR) and
`control logic for receiving comparator outputs, digitally
`encoding them to two binary bits, and feeding the result to the
`internal DACs.
`Id., Fig. 2, see id. at 254, Fig. 3.
`Fetterman
`b)
`Fetterman describes “a multistage converter for converting a sampled
`analog signal to a corresponding digital representation,” in which “each
`stage of the converter receives an analog input signal and produces a partial
`digital output.” Ex. 1006, 2:36–40. Figure 1 of Fetterman is reproduced
`below.
`
`14
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`
`
`Figure 1 of Fetterman depicts an example embodiment of a multistage
`ADC 10. Id. at 3:53–55. Fetterman describes that ADC 10 is an (N+1) bit
`converter, with each of N stages generating two bits of output. Id. at 3:55–
`57. In operation, scaled analog input signal 12 is applied to input 14 of
`sample-and-hold circuit 16, which outputs sampled analog signal 20 to first
`stage 22. Id. at 4:5–7. First stage 22 receives sampled analog signal 20 and
`generates a two bit, first stage digital output 24 representing sampled analog
`signal 20. Id. at 4:7–10. First stage residue 26 is provided as an input to
`second stage 30, which generates a two bit, second state digital output 32
`representative of first stage residue 26. Id. at 4:14–15, 4:17–19. First stage
`residue 26 may be level shifted and increased by a gain factor, resulting in
`second stage residue 34, which is provided as an input to third stage 36. Id.
`at 4:22–25. In addition, dither from dither generator 38 may be applied to
`selected ones or all of the stages of multistage converter 10. Id. at 4:36–30.
`
`15
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`Error corrector circuit 28 receives the outputs from each stage (such as 24
`and 32), corrects errors based on redundant information contained in the
`digital outputs, eliminates the redundancy, and provides multi-bit digital
`output 120. Id. at 4:47–53.
`
`Figure 2 of Fetterman, which is reproduced below, further depicts
`operations during a typical stage of multistage ADC 10.
`
`
`Figure 2 of Fetterman further depicts operations within a typical stage 44
`(for example, first stage 22) of multistage ADC 10. Id. at 4:62–64. As
`shown in Figure 2, analog input signal 54 (for example, sampled analog
`signal 20) is provided to two bit ADC 62, which converts signal 54 to digital
`output 64 (for example, first stage digital output 24). Id. at 4:65–5:1.
`Digital output 64 is provided to error corrector circuit 28 and two-bit
`DAC 46. Id. at 5:1–2. Two bit DAC 46 converts digital output 64 to
`corresponding analog signal 50, which is presented along with analog input
`signal 54 to summing node 52. Id. at 5:3–8. Summing node 52 subtracts
`analog signal 50 from analog input signal 54, thereby removing the portion
`of the signal represented by digital output 64, to provide analog difference
`
`16
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`signal 56, an internal stage residue. Id. at 5:8–12. Analog difference
`signal 56 is provided to simplifier 58, which provides a very accurate gain
`(preferably 2) “to maintain the residue within the linear range of analog
`circuitry in the subsequent stage” and “permit[] the stages to be substantially
`identical.” Id. at 5:15–20. Amplifier 58 may output amplified difference
`signal 60—an analog output that is an amplified (gained-up) version of the
`internal stage residue of stage 44 (for example, first stage residue 26)—to a
`subsequent stage (for example, second stage 30) for further processing. Id.
`at 5:20–23, 5:38–40.
`c) Discretionary Denial Analysis
`Patent Owner argues that “Dabbagh-Sadeghipour uses the same
`multiengine SAR architecture with two-bits per trial as Bae, which was
`discussed at length in the Background section of the ’321 patent and
`separately submitted in an IDS.” Prelim. Resp. 26 (citing Ex. 1003, 77,
`226;8 Ex. 1001, 1:40–2:47). According to Patent Owner, “Bae’s converter is
`identical to Dabbagh-Sadeghipour’s converter in all relevant respects.” Id.
`at 26; see also id. at 27–28 (comparing Figure 2 Dabbagh-Sadeghipour with
`Figure 5 of Bae). We note it is undisputed that Bae was submitted on an
`Information Disclosure Statements during prosecution of the ’321 patent and
`also is described in detail in the Background of the Invention section of
`the ’321 patent. See id.
`Patent Owner also argues that “Fetterman’s teachings of a basic
`pipelined flash ADC are cumulative with numerous references of record,
`including Davies, which was cited by the Examiner in the second Office
`
`
`8 We cite to Petitioner’s page numbers in Exhibit 1003 when referring to the
`prosecution history of the ’321 patent.
`
`17
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`Action.” Prelim. Resp. 28. In particular, Patent Owner submits a side-by-
`side comparison of Figures 1 and 2 of Fetterman and Figure 2 of Davies and
`asserts that “Davies’s pipelined converter is identical to Fetterman’s
`pipelined converter in all relevant respects.” Id. at 28–29; see id. at 29–30.
`Patent Owner argues “there are no material differences between Dabbagh-
`Sadeghipour and Bae or between Fetterman and Davies.” Id. at 30. We
`agree with Patent Owner that “[t]he teachings are cumulative in nature, and
`the Petition relies upon the prior art in the same manner as the prosecution
`history, implicating at least Becton, Dickinson factors (a), (b) and (d).” Id.
`Before discussing the specific factors and framework necessary in
`evaluating discretionary denial under § 325 as to Dabbagh-Sadeghipour and
`Fetterman, some analysis of the prosecution history and the prior art
`previously presented to the Office is in order.
`The Prosecution History and Previously
`d)
`Considered Prior Art to Bae (Ex.1023), Al-Awadhi
`(Ex. 1015), and Davies (Ex. 1016)
`(1) Bae
`Bae diagrammatically depicts digital to analog converters 58–60 and
`respective comparators 55–57, i.e., conversion engines, for converting
`values from respective SAR registers 62, 63, and 64 shown in Figure 5,
`reproduced below. Ex. 1023, 4:38–53.
`
`18
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`
`
`
`
`Figure 5 of Bae, above, illustrates an ADC including first, second, and third,
`(reference numbers 58–59 and 55–57), conversion engines. Ex. 1023, 4:38–
`53. Bae does not discuss or explain the use of such a conversion core in a
`pipelined ADC architecture. See, e.g., Ex. 1002 ¶ 25 (Petitioner’s declarant,
`Dr. Horenstein, stating that similar to Dabbagh-Sadeghipour, “the prior-art
`patent to Bae (U.S. Patent No. 6,239,734) discloses the combination of a
`flash ADC and a SAR ADC (i.e., flash-SAR ADC).”).
`During prosecution of the application which became the ’321 patent,
`the Examiner considered, but did not rely expressly on Bae (U.S. Patent
`No. 6,239,734) for any rejections. 9 Ex. 1003, 77. As noted above, Bae is
`discussed extensively in the Background of the ’321 patent and underlying
`
`
`9 The Examiner initialed the Bae reference entry, as considered on the
`Information Disclosure Statement dated August 10, 2006.
`
`19
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`patent application. 10 See Ex. 1001, 1:40–2:47; see Ex. 1003, 97–98. The
`background discussion about Bae explains that using three successive
`approximation converters, i.e., converter engines in an ADC presents both
`power consumption problems or, if the components are made smaller to
`consume less power, the engines are susceptible to thermal noise and,
`“thermal noise occurring at any one of the successive approximation
`converters can result in that converter giving a false result and will skew the
`entire conversion process.” Ex. 1001, 2:31–34.
`After pointing out several concerns with using Bae’s converter
`engines as an ADC, including thermal noise and potential miss-match errors
`between collaborative conversion engines, the ’321 patent proposes the use
`of two stages, i.e., using a first and second conversion core, where “at least
`one of the first and second converter cores comprises at least three analog to
`digital conversion engines and a controller for controlling the operation of
`the engines such that the engines collaborate to perform a successive
`approximation search.” Id. at 2:66–3:3. According to the ’321 patent, using
`a first and a second conversion cores in conjunction with the three ADC
`conversion engines has “a first advantage that a complete conversion need
`not be performed before starting the next analog to digital conversion,” and
`secondly, “although miss-match between collaborative ADCs may limit the
`number of bits that can be converted in each of the first and second
`converter cores to about 10 bits of resolution, the overall converter may be
`now have a resolution close to 20 bits, the resolution of both converters
`combined.” Id. at 3:10–12, 21–25.
`
`10 For consistency we refer mainly to the ’321 patent, and not the underlying
`U.S. Application No. 11/273,220, both of which contain the same analysis of
`Bae.
`
`20
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`
`(2) Al-Awadhi and Davies
`Besides considering Bae and this background information in the
`application, during prosecution the Examiner expressly rejected some of the
`claims over other prior art, Al-Awadhi. Ex. 1003, 41. The Examiner found
`that Al-Awadhi discloses an ADC conversion core, i.e., stage, including a
`plurality of ADC engines: “Al-Awadhi, in a related field, discloses a
`converting system that comprises a first converter core (118, fig. 1) and a
`second converter core (110, fig. 1) where the second converter comprises a
`plurality of ADC (110a, . . .110k; col. 2, lines 53–55).” Id. Thus, the
`Examiner found that Al-Awadhi taught certain limitations of original claims
`1 and 3, including the limitation that “the first converter core comprises a
`plurality of analog to digital conversion engines operating in parallel in a
`collaborative manner,” recited in original dependent claim 3. Id. at 41–43.
`The Examiner further relied upon Davies for teaching known
`pipelined ADC architecture including determining in the first converter core
`“a first residue as a difference between the input signal and the analog
`representation of the first digital result (note element 16 is a subtraction
`circuit that performs this operation); a second converter core (17, fig. 2) for
`performing a second part of the analog to digital conversion by converting
`the first residue (fig. 2).” Id. at 41.
`(3) Original Dependent Claim 4
`Original dependent claim 4 was dependent on claim 3, which in turn
`was dependent on claim 1. Id. at 59–60. The Examiner did not find that Al-
`Awadhi and Davies disclosed the limitations of original claim 4, which read:
`An analog to digital converter as claimed in claim 3, in which the
`analog to digital conversion engines comprise switched capacitor
`analog to digital converters, and once the first converter core has
`determined the first digital result the switched capacitor analog
`
`21
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`to digital converters of the first converter core are set to the first
`digital result such that the first converter core acts as the first
`residue generator.
`Id. at 60. 11
`To overcome the Examiner’s rejections, Applicant amended the
`original claim 1 to include the limitations of claims 3 and 4 in independent
`claim 1. Ex. 1003, 31.
`Becton Dickinson factors (a), (b), and (c)
`e)
`As discussed above, Becton, Dickinson factors (a), (b), and (d) relate
`to the first part of the Advanced Bionics framework (whether the same or
`substantially the same art or arguments previously were presented to the
`Office).
`Becton, Dickinson factor (a) – the similarities and material
`differences between the asserted art and the prior art involved
`during examination
`Our review of Davies, relied on by the Examiner, and Fetterman, now
`relied on by Petitioner, reveals that they are mostly cumulative as to known
`ADC SAR architecture. Ex. 1003, 41; Pet. 15–21. Davies, for example,
`referring to Figure 2 reproduced below, teaches “a first analogue to digital
`conversion stage (14) for performing a relatively coarse conversion on a
`sample of an analogue input signal,” “a difference circuit (16) for generating
`an analogue difference signal representing the difference between the signal
`held by the sample and hold stage (13),” and “second analogue to digital
`conversion stage (17) for generating a digital output corresponding to the
`difference signal.” Ex. 1016, Abstract. Davies Figure 3 is reproduced
`below.
`
`11 The Examiner objected to claim 4 but indicated it would be allowable if
`rewritten in independent form etc. See Ex. 1003, 43.
`
`22
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`
`
`
`
`Davies Figure 3, above, illustrates a block diagram of a two stage converter.
`Id. at 3:12–13. Davies also explains that “[t]he difference circuit (16)
`arithmetically combines appropriate pairs of the currents from the sample
`and hold and digital to analogue conversion stages to generate a differential
`current pair for input to the second analogue to digital conversion stage.” Id.
`at Abstract.
`Fetterman, similar to Davies, teaches a multi-stage, pipelined ADC
`architecture including first stage 22 generating first stage residue 26
`provided as an input to second stage 30, which generates a two bit, second
`state digital output 32 representative of first stage residue 26. Ex. 1006,
`4:14–15, 4:17–19. While there may be differences in the circuit structures
`between Davies and Fetterman, the respective references were relied upon
`by the Examiner, and now Petitioner, for teaching a pipelined, multi-stage
`ADC generating a difference, i.e., residue, between an input signal and an
`
`23
`
`
`
`IPR2021-00294
`Patent 7,274,321 B2
`analog representation of the first digital conversion, and providing the
`residue to a second conversion stage.
`We also find that there is specific similarity between Bae, Al-Awadhi,
`and Dabbagh-Sadeghipour, particularly as these references relate to the
`“analog to digital conversion engines” recited in claim 1. As discussed
`above, the Examiner relied on Al-Awadhi to teach “a first converter
`core (118, fig. 1) and a second converter core (110, fig. 1) where the second
`converter comprises a plurality of ADC (110a, . . . , 110k; col. 2, lines 53–
`55).” Ex. 1003, 42. The Examiner found specifically that Al-Awadhi’s
`“converter core 110 comprises a plurality of ADCs that determines a
`plurality of bits[] and the analog to digital converter shown in fig. 1 of Al-
`Awadhi which the first converter core (110, fig. 1)
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
