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`11/4/2020
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`A new architecture for area and power efficient, high conversion rate successive approximation ADCs - IEEE Conference Publication
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`Conferences > The 2nd Annual IEEE Northeast...
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`A new architecture for area and power efficient, high conversion
`rate successive approximation ADCs
`Publisher: IEEE
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`K. Dabbagh-Sadeghipour; K. Hadidi; A. Khoei All Authors
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`Abstract
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`Document Sections
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`I.
`
`Introduction
`
`II. The Prorosed SA-
`ADC Architecture
`
`Abstract:A new high-speed successive approximation analog-to-digital converter
`architecture is presented. Two bits extraction in each clock cycle is the key idea to
`double the con...View more
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`III.
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`Implementation
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`IV. Cost Comparison
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`V. Conclusions
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`Abstract:
`A new high-speed successive approximation analog-to-digital converter architecture is
`presented. Two bits extraction in each clock cycle is the key idea to double the
`conversion speed. Generating reference levels for three comparators with only two
`DACs, is another novelty of the new architecture. The simulation results for the
`designed 10-bit ADC show that in same conversion rate, better figure of merit value,
`40% and 7% reduction in chip size and power consumption is achievable over the
`ti
`l S
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`References
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`A low power consumption 10-bit rail-to-rail
`SAR ADC using a C-2C capacitor array
`2008 IEEE International Conference on
`Electron Devices and Solid-State Circuits
`Published: 2008
`
`Low Power Two Stage Dynamic
`Comparator Circuit Design for Analog to
`Digital Converters
`2018 International Conference on
`Computer Communication and Informatics
`(ICCCI)
`Published: 2018
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`11/4/2020
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`A new architecture for area and power efficient, high conversion rate successive approximation ADCs - IEEE Conference Publication
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`Date of Conference: 23-23 June 2004
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`INSPEC Accession Number: 8369639
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`Date Added to IEEE Xplore: 22 November
`2004
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`Print ISBN:0-7803-8322-2
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`DOI: 10.1109/NEWCAS.2004.1359079
`
`Publisher: IEEE
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`Conference Location: Montreal, Quebec,
`Canada, Canada
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` Contents
`
`I. Introduction
`High speed and low power CMOS Analog-to-Digital Converters (ADCs)
`are key components in mixed-signal integrated circuits. Among CMOS
`ADC design techniques, full flash and multi-step flash ADCs are the
`well-known architectures for high-speed analog to digital conversion [1].
`Sign in to Continue Reading
`However, these architectures require large area and power
`consumption. The high-speed and low-power constraints can also be
`met with folding and interpolation techniques. However, it is difficult to
`achieve a high resolution (e.g.
` bit) due to the limitation in folding
`factor [2].
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1005 Page 7
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1005 Page 8
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`Authorized licensed use limited to: IEEE Publications Operations Staff. Downloaded on November 04,2020 at 19 09:56 UTC from IEEE Xplore. Restrictions apply.
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1005 Page 9
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`Authorized licensed use limited to: IEEE Publications Operations Staff. Downloaded on November 04,2020 at 19 09:56 UTC from IEEE Xplore. Restrictions apply.
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1005 Page 10
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