Case 1:19-cv-02225-UNA Document 1 Filed 12/05/19 Page 1 of 40 PageID #: 1
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`IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
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`ANALOG DEVICES, INC.,
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`Plaintiff,
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`v.
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`XILINX, INC.,
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`Defendant.
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`C.A. No. __________________
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`JURY TRIAL DEMANDED
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`COMPLAINT
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`Analog Devices, Inc. (“ADI”), by and through the undersigned counsel, brings this action
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`for patent infringement against defendant Xilinx, Inc. (“Xilinx”).
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`INTRODUCTION
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`1.
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`ADI is the global market leader and innovator in the design and manufacture of
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`high performance analog, mixed signal, and power integrated circuit products. ADI gained this
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`leadership through hard work, a commitment to excellence, and substantial economic
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`investments.
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`2.
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`This case arises out of Xilinx’s recent attempts to incorporate ADI’s patent-
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`protected inventions into Xilinx’s products.
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`PARTIES
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`3.
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`ADI is a Massachusetts corporation with its corporate headquarters located at One
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`Technology Way, Norwood, Massachusetts 02062.
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`4.
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`ADI’s products are embedded inside many different types of electronics devices,
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`and used around the world in diverse industries including, for example, aerospace and defense,
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`computer networking, cellular and wireless infrastructure, automobiles, industrial process and
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`control systems, medical imaging equipment, and consumer portable electronics. As the world’s
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 1
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`leading provider of high-performance data converters, ADI offers both the largest analog-to-
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`digital converter (ADC) portfolio and largest digital-to-analog converter (DAC) portfolio in the
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`industry. Confirming this technical leadership, ADI has been named a Top 100 Global Innovator
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`seven times in the last eight years, and was recently awarded the IEEE Corporate Innovation
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`Award for sustained innovation and leadership in the development of high-performance data
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`converter technology and products. ADI’s award-winning products have been consistently
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`recognized as pushing the boundaries in critical areas including sample rate, dynamic range,
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`power efficiency, and integration.
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`5.
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`Founded in 1965 by Ray Stata and Matthew Lorber, both graduates of the
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`Massachusetts Institute of Technology, ADI has fostered a culture of innovation. Mr. Stata’s
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`visionary leadership transformed ADI from its beginnings as a small Cambridge-based company
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`into a global technology company offering one of the most comprehensive and technologically
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`sophisticated lines of integrated circuits in the world. In 1969, ADI made its first foray into the
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`semiconductor business and rose to the challenge of rivaling larger companies that already had a
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`head start in the newly developing space. ADI has since established itself as a leading supplier
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`of high-performance analog-to-digital converters that emphasize speed and precision.
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`6.
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`On information and belief, defendant Xilinx, Inc. is a Delaware corporation, with
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`a principal business address of 2100 Logic Drive, San Jose, California 95124.
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`JURISDICTION AND VENUE
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`7.
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`This Court has subject matter jurisdiction over this action pursuant to 28 U.S.C.
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`§§ 1331 and 1338.
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`8.
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`This Court has personal jurisdiction over Xilinx. Xilinx is a Delaware
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`corporation and has continuous and systematic business contacts with the State of Delaware.
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`Xilinx, directly and through subsidiaries or intermediaries (including distributors, retailers, and
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`2
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 2
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`others), has purposefully and voluntarily placed its infringing products and services into this
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`District and into the stream of commerce with the intention and expectation that they will be
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`purchased and used by consumers in this District. Xilinx has offered and sold and continues to
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`offer and sell these infringing products and services in this District.
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`9.
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`Venue is proper in this District pursuant to 28 U.S.C. §1400(b) because Xilinx is
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`a Delaware corporation.
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`ADI’s Patented Technologies
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`FACTUAL ALLEGATIONS
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`10.
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`ADI has become the world’s leading provider of data conversion technology
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`through hard work, a commitment to excellence, and substantial economic investments. In the
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`last five years alone, the company has invested more than $5 billion in research and
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`development, much of it focused on ADCs, DACs, and related circuit and system design
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`challenges. This continuing investment in innovation has produced one of the industry’s top
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`patent portfolios, including over 3,200 patents in the United States and many more across the
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`globe.
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`11.
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`12.
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`This complaint focuses on eight important ADI patents relating to ADCs.
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`ADI is the assignee and owner of United States Patent No. 7,719,452 titled
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`“Pipelined Converter Systems With Enhanced Linearity” (the “’452 Patent”). The ’452 Patent
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`was duly and legally issued on May 18, 2010. The patent relates generally to a circuit and
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`technique for enhancing linearity in analog-to-digital converters by injecting dither to sampled
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`signals. A copy of the ʼ452 Patent is attached as Exhibit A.
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`13.
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`ADI is the assignee and owner of United States Patent No. 7,663,518, titled
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`“Dither Technique For Improving Dynamic Non-linearity In An Analog To Digital Converter,
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`And An Analog To Digital Converter Having Improved Dynamic Non-linearity” (the “’518
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`3
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 3
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`Patent”). The ʼ518 patent was duly and legally issued on Feb. 16, 2010. The patent relates
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`generally to a circuit and technique for applying a dither to improve linearity. A copy of the
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`ʼ518 Patent is attached as Exhibit B.
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`14.
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`ADI is the assignee and owner of United States Patent No. 6,900,750 titled
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`“Signal Conditioning System With Adjustable Gain And Offset Mismatches” (the “’750
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`Patent”). The ʼ750 Patent was duly and legally issued on May 31, 2005. The patent relates
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`generally to a circuit and technique for calibrating an offset mismatch in analog-to-digital
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`converters using chopping techniques. A copy of the ʼ750 Patent is attached as Exhibit C.
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`15.
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`ADI is the assignee and owner of United States Patent No. 10,250,250, titled
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`“Bootstrapped Switching Circuit,” (the “’250 Patent”). The ʼ250 Patent was duly and legally
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`issued on April 2, 2019. The patent relates generally to a circuit and technique for quickly
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`activating a switch, such as a front-end sampling switch, by generating a boosted voltage using a
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`positive feedback loop. A copy of the ʼ250 Patent is attached as Exhibit D.
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`16.
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`ADI is the assignee and owner of United States Patent No. 7,274,321, titled
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`“Analog to Digital Converter” (the “’321 Patent”). The ʼ321 Patent was duly and legally issued
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`on September 25, 2007. The patent relates generally to analog-to-digital converters having a
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`pipelined converter architecture. A copy of the ʼ321 Patent is attached as Exhibit E.
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`17.
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`ADI is the assignee and owner of United States Patent No. 7,012,463, titled
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`“Switched Capacitor Circuit with Reduced Common-Mode Variations” (the “’463 Patent”). The
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`ʼ463 Patent was duly and legally issued on March 14, 2006. The patent relates generally to
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`switched capacitor circuits that provide a feedback signal to reduce common-mode variations in
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`an output of a circuit. A copy of the ʼ463 Patent is attached as Exhibit F.
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`4
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 4
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`18.
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`ADI is the assignee and owner of United States Patent No. 8,487,659, titled
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`“Comparator with Adaptive Timing” (the “’659 Patent”). The ʼ659 Patent was duly and legally
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`issued on July 16, 2013. The patent relates generally to timing circuits that compensate for the
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`effects of variations in process, voltages, and temperature. A copy of the ʼ659 Patent is attached
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`as Exhibit G.
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`19.
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`ADI is the assignee and owner of United States Patent No. 7,286,075, titled
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`“Analog to Digital Converter with Dither” (the “’075 Patent”). The ’075 Patent was duly and
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`legally issued on October 23, 2007. The patent relates generally to a circuit and technique for
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`enhancing linearity in analog-to-digital converters by injecting dither to sampled signals. A copy
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`of the ’075 Patent is attached as Exhibit H.
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`Xilinx’s Incorporation of Analog’s Patented Technologies into Xilinx’s RFSoC Products
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`20.
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`Xilinx has been a significant beneficiary of ADI’s substantial and continuing
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`investments in analog-to-digital conversion technology. ADI has worked closely with Xilinx for
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`many years to develop proven solutions tailored to Xilinx’s field-programmable gate array
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`(FPGA) products, including Xilinx’s Kintex 7 and Kintex UltraScale products, its Virtex 7 and
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`Virtex UltraScale products, its Zynq 7 products, and its initial Zynq UltraScale products. See,
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`e.g., https://www.analog.com/en/design-center/reference-designs/hardware-reference-
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`design/fpga-compatible-reference-designs/xilinx-fpga.html#z7.
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`21.
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`Over the course of the parties’ collaboration, ADI has shared with Xilinx, under a
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`non-disclosure agreement, extensive and detailed technical information concerning its many
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`innovations in ADC technology.
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`22.
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`Xilinx has not only benefitted from its partnership with ADI but also has
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`extensively promoted this partnership on Xilinx’s own website. See, e.g.,
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`5
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 5
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`https://www.xilinx.com/alliance/memberlocator/1-8dv3-84.html;
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`https://www.xilinx.com/video/fpga/analog-devices-demo-5gsps-data-acquisition.html. For
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`example, Xilinx’s website touts ADI as a partner that has “provide[d] a rich set of JESD204B
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`references designs and high-speed FMC cards to jump start development.” See
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`https://www.xilinx.com/products/technology/high-speed-serial/jesd2014-reference-designs.html
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`(listing, among others, ADI and its “4-chan, 14-bit, 250 MSPS” analog-to-digital converter).
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`23.
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`At the same time that Xilinx purportedly was working with ADI as an alleged
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`partner to combine ADI’s proprietary ADC technology with Xilinx’s programmable system-on-
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`a-chip (“SoC”) products, however, Xilinx was also separately working to incorporate ADI’s
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`patented technology directly into its new “Integrated Direct-RF Subsystem”:
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`
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`See https://www.xilinx.com/products/technology/rfsampling.html#overview. Contrary to its
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`purported partnership with ADI, Xilinx boasts that its RFSoC product “[e]liminates discrete
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`6
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 6
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`converters” and “[r]emoves power-hungry FPGA-to-Analog interfaces like JESD204.” See, e.g.,
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`https://www.xilinx.com/products/silicon-devices/soc/rfsoc.html.
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`24.
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`Xilinx’s newest Zynq UltraScale products – including at least the Zynq UltraScale
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`+ RFSoC with RF Data Converters and Zynq UltraScale + RFSoC with RF Data Converters and
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`SD-FED Cores (collectively, the “Accused RFSoC Products”) – have extensively incorporated
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`ADI’s proprietary and patented technologies.
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`25.
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`Xilinx promotes the Accused RFSoC Products on its website as aimed at “High
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`End” applications and specifically highlights the integrated “RF Data Converter” as a key
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`feature. See, e.g., https://www.xilinx.com/products/silicon-devices/soc.html.
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`26.
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`Xilinx’s own product literature confirms that its Accused RFSoC products now
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`incorporate “Direct RF sampling” technology – like ADI’s technology:
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`7
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 7
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`See Xilinx White Paper, An Adaptable Direct RF-Sampling Solution, February 20, 2019
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`(available at https://www.xilinx.com/support/documentation/white papers/wp489-rfsampling-
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`solutions.pdf). As Xilinx recognizes in this paper, “Direct RF-sampling” – such as that
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`accomplished in ADI’s RF Sampling ADCs, cited as “Reference 1” to the paper – “enables a
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`new level adaptability by moving much of the RF signal processing into the digital domain.”
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`Xilinx’s stated solution within its RFSoC products is to “integrate” these “RF-sampling data
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`converters” with Xilinx’s own very large-scale integration (“VLSI”) devices.
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`27.
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`Xilinx posts information regarding how its Accused RFSoC Products operate on
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`its website in various places, including but not limited to:
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`https://www.xilinx.com/products/silicon-devices/soc/rfsoc.html#documentation. Xilinx’s
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`RFSoC products are further described in:
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`
`
`
`
`
`
`
`
`
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`“A 13b 4GS/s Digitally Assisted Dynamic 3-Stage Asynchronous Pipelined-SAR
`ADC”, Vaz et al., February 2017 (“Vaz White Paper”) (available at:
`https://www.xilinx.com/support/documentation/product-briefs/rfsoc-ieee-paper.pdf);
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`“Zynq UltraScale+ RFSoC Data Sheet: Overview” (“RFSoC Data Sheet”) (available at:
`https://www.xilinx.com/support/documentation/data sheets/ds889-zynq-usp-rfsoc-
`overview.pdf);
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`“High-speed ADCs for Wireless Base-Stations,” Verbruggen et al., AACD 2019
`(“Verbruggen White Paper”) (attached as Exhibit I).
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`“A 13b 4GS/s Digitally Assisted Dynamic 3-Stage Asynchronous Pipelined-SAR
`ADC,” presented at 2017 IEEE International Solid-State Circuits Conference (“Xilinx
`ISSCC Presentation”);
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`“A 13bit 5GS/s ADC with time-interleaved chopping calibration in 16nm FinFET,” Vaz,
`et al., 2018 VLSI Symposium on VLSI Circuits Digest of Technical Papers, (“Vaz VLSI
`Paper”) (attached as Exhibit J);
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` U.S. Patent No. 10,033,395 to Vaz et al. (the “ʼ395 Patent”) (attached as Exhibit K);
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`28.
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`Xilinx’s reliance on ADI’s patented inventions is pervasive throughout Xilinx’s
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`ADC design for its Accused RFSoC Products, including its most important architectural
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`8
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 8
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`elements. For example, at the front-end of the products, Xilinx’s ADC infringes ADI’s patented
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`inventions relating to a fast front-end sampling switch, which is critically important to the
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`converter’s overall speed. Xilinx’s ADC also infringes ADI’s patented inventions relating to
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`pipelined converter stages that ensure high speed and high resolution conversion. Xilinx’s ADC
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`infringes ADI’s patented inventions relating to dithering and other techniques to improve the
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`accuracy and linearity of the converter as a whole.
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`COUNT I
`(Infringement of U.S. Patent No. 7,719,452)
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`29.
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`ADI incorporates the allegations contained in the preceding paragraphs as if fully
`
`set forth herein.
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`30.
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`Xilinx has infringed and continues to infringe, directly and/or indirectly, literally
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`and/or equivalently, one or more claims of the ʼ452 Patent, including at least claim 1, by making,
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`using, selling, offering for sale in, and/or importing into, the United States certain products with
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`analog-to-digital conversion technology, including at least the Accused RFSoC Products.
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`31.
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`The Accused RFSoC Products include an analog-to-digital converter system to
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`convert an analog input signal to a digital code. For example:
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`9
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 9
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`See, e.g., Verbruggen White Paper, Figs. 4 & 7.
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`32.
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`The Accused RFSoC Products’ analog-to-digital converter system has a sampler
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`to provide samples of said analog input signal. For example, the Accused RFSoC Products’
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`analog-to-digital converter system has a “sampling network” that provides samples of the analog
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`input signal:
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`
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`See, e.g., Verbruggen White Paper, Fig. 6.
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`33.
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`The Accused RFSoC Products’ analog-to-digital converter system has signal
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`converters arranged and configured to successively process said samples. For example, the
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`RFSoC analog-to-digital converter system includes a 3-stage pipelined successive approximation
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`register (SAR) architecture, where successive stages are separated by residue amplifiers. A first
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`10
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 10
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`stage processes an analog input signal. A second stage processes a residue signal generated by
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`the first stage. A third stage processes a residue signal generated by the second stage.
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`Verbruggen White Paper, Fig. 7.
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`34.
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`The Accused RFSoC Products’ analog-to-digital converter system has at least one
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`digital-to-analog converter configured to respond to a random digital code and inject analog
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`dither signals into at least a selected one of said sampler and said signal converters which process
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`said samples and said analog dither signals into a plurality of digital codes. For example, the
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`Accused RFSoC Products’ analog-to-digital converter system has digital-to-analog converters
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`that receive a 3.7-bit pseudo-random bit sequence and inject analog dither signals at an input of
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`an analog-to-digital converter:
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`
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`See, e.g., Vaz VLSI Paper, 99.
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`35.
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`The Accused RFSoC Products’ analog-to-digital converter system has an
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`aligner/corrector coupled to said signal converters to process said plurality of digital codes into a
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`combined digital code that includes a first portion that corresponds to said samples and a second
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`portion that corresponds to said analog dither signals. For example, the Accused RFSoC
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`11
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 11
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`Products include a combiner (for example, 222) that generates a digital output signal (for
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`example, 220).
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`
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`See, e.g., ʼ395 Patent, Fig. 5; see also Vaz VLSI Paper, Fig. 1.
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`36.
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`The Accused RFSoC Products’ analog-to-digital converter system has a decoder
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`having a transfer function configured to convert said random digital code to said second portion
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`for differencing with said combined digital code to thereby provide said system digital code. For
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`example, the decoder in the Accused RFSoC Products’ analog-to-digital converter system
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`subtracts a digital dither signal code from the output signal of the analog-to-digital converter to
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`provide a digitized version of the sampled signals:
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`12
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 12
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`See, e.g., Vaz VLSI Paper, 99.
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`37.
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`In the Accused RFSoC Products’ analog-to-digital converter system, said samples
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`are thus processed along different signal-processing paths of said signal converters to thereby
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`enhance linearity of said system. For example, a linearization dither is injected after sampling
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`and prior to the conversion processing that is performed in the Accused RFSoC Products’
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`analog-to-digital converters to improve linearity of the analog-to-digital converter. See, e.g.,
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`Verbruggen White Paper, Fig. 4.
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`38.
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`Xilinx has actively and knowingly induced, and is actively and knowingly
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`inducing, infringement of the ʼ452 Patent, at least by its customers’ use of the Accused RFSoC
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`Products. For example, on information and belief, Xilinx instructs its customers by way of
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`manuals or product documentation to infringe the asserted claims by using the Accused RFSoC
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`Products. Xilinx has had knowledge of the ʼ452 patent and its infringement of the ʼ452 patent
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`since at least July 31, 2019, when ADI provided Xilinx with claim charts substantiating its
`
`infringement of the patent. Xilinx’s inducement of infringement of the ʼ452 Patent has been
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`done with specific intent to infringe that patent.
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`13
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 13
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`39.
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`Xilinx’s infringement of the ʼ452 Patent has been willful and its ongoing
`
`infringement of the ʼ452 Patent continues to be willful. Xilinx has chosen to manufacture and
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`sell the Accused RFSoC Products, even after ADI’s notice, knowing that such products would
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`infringe the ’452 Patent.
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`40.
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`ADI has been and is being irreparably harmed, and has incurred and will continue
`
`to incur damages, as a result of Xilinx’s infringement of the ʼ452 Patent.
`
`COUNT II
`(Infringement of U.S. Patent No. 7,663,518)
`
`41.
`
`ADI incorporates the allegations contained in the preceding paragraphs as if fully
`
`set forth herein.
`
`42.
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`Xilinx has infringed and continues to infringe, directly and/or indirectly, literally
`
`and/or equivalently, one or more claims of the ʼ518 Patent, including at least claim 1, by making,
`
`using, selling, offering for sale in, and/or importing into, the United States certain products with
`
`analog-to-digital conversion technology, including at least the Accused RFSoC Products.
`
`43.
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`The Accused RFSoC Products include an analog-to-digital converter that has a
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`conversion engine comprising a switched capacitor array having redundancy. For example, the
`
`Accused RFSoC Products’ analog-to-digital converters include an asynchronous pipelined-SAR
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`analog-to-digital converter:
`
`14
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 14
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`
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`See, e.g., Vaz White Paper, 277. The Accused RFSoC Products’ analog-to-digital converters are
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`13-bit converters with a 3-stage pipelined successive approximation register (SAR) architecture,
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`where each stage has 5 bits, thereby providing redundancy. See, e.g., Vaz White Paper, 276.
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`44.
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`The Accused RFSoC Products’ analog-to-digital converters have two analog-to-
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`digital units, each analog-to-digital unit consisting of four sub-ADC slices and a sampling
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`network with a front-end switch and four channel switches. See, e.g., Vaz White Paper, 276
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`(“Each 2GS/S ADC unit consists of four interleaved 500 MS/s sub-ADC slices and a sampling
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`network composed of a front-end switch and four channel switches used to interleave the four
`
`ADC slices without time-skew calibration requirements.”); id. (“Fig. 16.1.1b shows the topology
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`of each sub-ADC. It uses three asynchronous 5b SAR stages separated by two residue amplifiers
`
`15
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 15
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`(RA). For speed reasons, each stage uses a split-capacitor MDAC to maintain constant common
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`mode and five cascaded dynamic comparators.”).
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`45.
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`The Accused RFSoC Products’ analog-to-digital converters have a dither device
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`for applying a dither to the conversion engine. For example, the first and second stages in a sub-
`
`ADC slice use dithering injecting capacitors to apply dither to the conversion engine:
`
`
`
`See, e.g., Xilinx ISSCC Presentation, slide 21.
`
`46.
`
`The Accused RFSoC Products’ analog-to-digital converters have a controller
`
`adapted to operate the conversion engine to perform a successive approximation conversion of
`
`an analog input. For example, the Accused RFSoC Products’ analog-to-digital converters
`
`include a controller that provides control signals (e.g., convert, clear) for each successive
`
`approximation register (SAR) stage in the sub-ADC slice:
`
`
`
`16
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 16
`
`

`

`Case 1:19-cv-02225-UNA Document 1 Filed 12/05/19 Page 17 of 40 PageID #: 17
`
`
`
`
`See, e.g., Vaz White Paper, 277.
`
`47.
`
`In the Accused RFSoC Products’ analog-to-digital converters the dither is
`
`removed from the conversion engine prior to completion of successive approximation bit trials as
`
`part of the analog-to-digital conversion. For example, the second and third stages in the sub-
`
`ADC slice use dithering removing capacitors that remove dither before completion of the analog-
`
`to-digital conversion:
`
`See, e.g., Xilinx ISSCC Presentation, slide 20.
`
`17
`
`
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 17
`
`

`

`Case 1:19-cv-02225-UNA Document 1 Filed 12/05/19 Page 18 of 40 PageID #: 18
`
`
`48.
`
`Xilinx has actively and knowingly induced, and is continuing to actively and
`
`knowingly induce, infringement of the ʼ518 Patent, at least by its customers’ use of the Accused
`
`RFSoC Products. For example, on information and belief, Xilinx instructs its customers by way
`
`of manuals or product documentation to infringe the asserted claims by using the Accused
`
`RFSoC Products. Xilinx has had knowledge of the ʼ518 patent and its infringement of the ʼ518
`
`patent since at least July 31, 2019, when ADI provided Xilinx with claim charts substantiating its
`
`infringement of the patent. Xilinx’s inducement of infringement of the ʼ518 Patent has been done
`
`with specific intent to infringe that patent.
`
`49.
`
`Xilinx’s infringement of the ʼ518 Patent has been willful and its ongoing
`
`infringement of the ʼ518 Patent continues to be willful. Xilinx has chosen to manufacture and
`
`sell the Accused RFSoC Products, even after ADI’s notice, knowing that such products would
`
`infringe the ’518 Patent.
`
`50.
`
`ADI has been and is being irreparably harmed, and has incurred and will continue
`
`to incur damages, as a result of Xilinx’s infringement of the ʼ518 Patent.
`
`COUNT III
`(Infringement of U.S. Patent No. 6,900,750)
`
`51.
`
`ADI incorporates the allegations contained in the preceding paragraphs as if fully
`
`set forth herein.
`
`52.
`
`Xilinx has infringed and continues to infringe, directly and/or indirectly, literally
`
`and/or equivalently, one or more claims of the ʼ750 Patent, including at least claim 19, by
`
`making, using, selling, offering for sale in, and/or importing into, the United States certain
`
`products with analog-to-digital conversion technology, including at least the Accused RFSoC
`
`Products.
`
`18
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 18
`
`

`

`Case 1:19-cv-02225-UNA Document 1 Filed 12/05/19 Page 19 of 40 PageID #: 19
`
`
`53.
`
`The Accused RFSoC Products adjust an offset signal in a signal conditioning
`
`system. For example, the RFSoC analog-to-digital converters include an analog-to-digital
`
`converter with a 3-stage pipelined successive approximation register (SAR) architecture, where
`
`the stages are separated by residue amplifiers:
`
`
`
`
`
`Verbruggen White Paper, Figs. 4, 7.
`
`54.
`
`The Accused RFSoC Products’ analog-to-digital converters clock a first converter
`
`with a random clock. For example, the Accused RFSoC Products’ analog-to-digital converters
`
`have an analog-to-digital converter with the 3-stage pipelined successive approximation register
`
`(SAR) architecture. See, e.g., Verbruggen White Paper, Fig. 4. The Accused RFSoC Products’
`
`analog-to-digital converters also include a 1-bit pseudo-random bit sequence (i.e., a random
`
`clock) to control chopping of the input signal to the analog-to-digital converter.
`
`55.
`
`The Accused RFSoC Products’ analog-to-digital converters sense a first offset
`
`signal of the first converter. For example, the Accused RFSoC Products’ analog-to-digital
`
`19
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 19
`
`

`

`Case 1:19-cv-02225-UNA Document 1 Filed 12/05/19 Page 20 of 40 PageID #: 20
`
`
`converters include offset calibration loops that measure and correct the average of each channel
`
`output of the analog-to-digital converter. The Accused RFSoC Products’ analog-to-digital
`
`converters include an offset calibration block inside the chopping path (OCB1) and an offset
`
`calibration block outside the chopping path (OCB2):
`
`See, e.g., Vaz VLSI Paper, 99.
`
`56.
`
`The Accused RFSoC Products’ analog-to-digital converters condition one of an
`
`input signal and an output signal of the first converter with the first offset signal. For example,
`
`
`
`20
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 20
`
`

`

`Case 1:19-cv-02225-UNA Document 1 Filed 12/05/19 Page 21 of 40 PageID #: 21
`
`
`the first offset sensor includes two loops; one offset calibration loop is active inside the chopping
`
`and the second offset calibration loop is acting outside the chopping:
`
`
`
`See, e.g., Verbruggen White Paper, Fig. 9.
`
`57.
`
`Xilinx has actively and knowingly induced, and is continuing to actively and
`
`knowingly induce, infringement of the ʼ750 Patent, at least by its customers’ use of the Accused
`
`RFSoC Products. For example, on information and belief, Xilinx instructs its customers by way
`
`of manuals or product documentation to infringe the asserted claims by using the Accused
`
`RFSoC Products. Xilinx has had knowledge of the ʼ750 patent and its infringement of the ʼ750
`
`patent since at least July 31, 2019, when ADI provided Xilinx with claim charts substantiating its
`
`infringement of the patent. Xilinx’s inducement of infringement of the ʼ750 Patent has been
`
`done with specific intent to infringe that patent.
`
`58.
`
`Xilinx’s infringement of the ʼ750 Patent has been willful and its ongoing
`
`infringement of the ʼ750 Patent continues to be willful. Xilinx has chosen to manufacture and
`
`21
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 21
`
`

`

`Case 1:19-cv-02225-UNA Document 1 Filed 12/05/19 Page 22 of 40 PageID #: 22
`
`
`sell the Accused RFSoC Products, even after ADI’s notice, knowing that such products would
`
`infringe the ’750 Patent.
`
`59.
`
`ADI has been and is being irreparably harmed, and has incurred and will continue
`
`to incur damages, as a result of Xilinx’s infringement of the ʼ750 Patent.
`
`COUNT IV
`(Infringement of U.S. Patent No. 10,250,250)
`
`60.
`
`ADI incorporates the allegations contained in the preceding paragraphs as if fully
`
`set forth herein.
`
`61.
`
`Xilinx has infringed and continues to infringe, directly and/or indirectly, literally
`
`and/or equivalently, one or more claims of the ’250 Patent, including at least claim 1, by making,
`
`using, selling, offering for sale in, and/or importing into, the United States certain products with
`
`analog-to-digital conversion technology, including at least the Accused RFSoC Products.
`
`62.
`
`Xilinx’s Accused RFSoC Products include an analog-to-digital converter with a
`
`bootstrapped switching circuit for accelerated turn on. For example, the Accused RFSoC
`
`Products include four “bootstrapped switches” (BS), acting as sampling switches, in the analog-
`
`to-digital converter’s “sampling network”:
`
`22
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1013 Page 22
`
`

`

`Case 1:19-cv-02225-UNA Document 1 Filed 12/05/19 Page 23 of 40 PageID #: 23
`
`
`
`
`See, e.g., Verbruggen White Paper, at Fig. 6 and 97-98 (confirming RFSOC includes four
`
`sampling switches which are bootstrapped).
`
`63.
`
`The Accused RFSoC Products include four sampling switches as bootstrapped
`
`switching circuits. Each sampling switch receives a voltage input signal and a gate voltage. For
`
`example, the sampling switch receives a voltage input signal on a source, in which the gate is
`
`controlled by an output of a bootstrapped voltage generator, which generates a boosted voltage
`
`based on the voltage input signal. The sampling switch is implemented as a MOS transistor.
`
`See, e.g., Verbruggen White Paper, at 97-98, Fig. 6.
`
`64.
`
`The bootstrapped switching circuit in the Accused RFSoC Products includes the
`
`bootstrapped voltage generator comprising a positive feedback loop, which is activated by a
`
`clock signal, to generate a gate voltage for turning on the sampling switch. For example, a
`
`bootstrapped voltage generator portion of the bootstrapped switching circuit generates the gate
`
`voltage for the sampling switch in the sampling network shown above. Id.
`
`65.
`
`The bootstrapped voltage generator portion’s positive feedback loop includes an
`
`output tr