IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
`
`C.A. No. 19-2225 (RGA)
`
`ANALOG DEVICES, INC.,
`
`Plaintiff,
`
`v.
`
`XILINX, INC.,
`
`Defendant.
`XILINX, INC. and
`XILINX ASIA PACIFIC PTE. LTD.,
`
`Counterclaim Plaintiffs,
`
`v.
`
`ANALOG DEVICES, INC.,
`
`Counterclaim Defendant.
`
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`ANALOG DEVICES, INC.’S OPENING CLAIM CONSTRUCTION BRIEF
`REGARDING THE ANALOG ASSERTED PATENTS
`
`MORRIS, NICHOLS, ARSHT & TUNNELL LLP
`Jack B. Blumenfeld (#1014)
`Brian P. Egan (#6227)
`1201 North Market Street
`P.O. Box 1347
`Wilmington, DE 19899
`(302) 658-9200
`jblumenfeld@mnat.com
`began@mnat.com
`
`Attorneys for Plaintiff / Counterclaim
`Defendant Analog Devices, Inc.
`
`OF COUNSEL:
`
`William F. Lee
`Cynthia D. Vreeland
`Peter M. Dichiara
`Stephanie Neely
`Nicole M. Fontaine Dooley
`WILMER CUTLER PICKERING HALE
`AND DORR LLP
`60 State Street
`Boston, MA 02109
`(617) 526-6000
`
`Keith Howell
`WILMER CUTLER PICKERING HALE
`AND DORR LLP
`1875 Pennsylvania Avenue, NW
`Washington, DC 20006
`(202) 663-6000
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1027 Page 1
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`
`
`Aaron Thompson
`WILMER CUTLER PICKERING HALE
` AND DORR LLP
`350 South Grand Avenue, Suite 2400
`Los Angeles, CA 90071
`(213) 443-5300
`
`November 5, 2020
`
`
`
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`TABLE OF CONTENTS
`
`INTRODUCTION ...............................................................................................................1 
`U.S. PATENT NO. 7,274,321 .............................................................................................2 
`“Second Converter Core” / “Using a Second Converter Core” / “Second
`A. 
`Conversion Core”.....................................................................................................2 
`1. 
`The ’321 Invention .......................................................................................2 
`2. 
`Representative Claim ...................................................................................4 
`3. 
`Analog’s Proposed Construction .................................................................5 
`“Operating in Parallel” .............................................................................................8 
`B. 
`“Operating … in a Cooperative Manner” / “Co-Operate” .......................................8 
`C. 
`US PATENT NO. 10,250,250 ...........................................................................................10 
`A. 
`“Jump Start Circuit” ...............................................................................................10 
`1. 
`The ’250 Invention .....................................................................................10 
`2. 
`Representative Claim .................................................................................12 
`3. 
`Analog’s Proposed Construction ...............................................................12 
`“Startup” ................................................................................................................13 
`B. 
`“Period of Time” / “Limited Period of Time” .......................................................14 
`C. 
`US PATENT NO. 6,900,750 .............................................................................................16 
`A. 
`“Random Clock” ....................................................................................................16 
`1. 
`The ’750 Invention .....................................................................................16 
`2. 
`Representative Claim .................................................................................16 
`3. 
`Analog’s Proposed Construction ...............................................................17 
`“Converter” / “Converter Circuits” ........................................................................18 
`B. 
`U.S. PATENT NO. 7,286,075 ...........................................................................................18 
`“First Group of Capacitors” / “Second Group of Capacitors for Applying
`A. 
`Dither”/ “Second Group of Capacitors”/ “Group of Capacitors” /
`“Switched Capacitor Digital to Analog Converter Responsive to a Control
`Word” .....................................................................................................................18 
`1. 
`The ’075 Invention .....................................................................................19 
`2. 
`Representative Claim .................................................................................21 
`3. 
`Analog’s Proposed Construction ...............................................................21 
`“The Array” ...........................................................................................................23 
`
`
`B. 
`
`i
`
`I. 
`II. 
`
`III. 
`
`IV. 
`
`V. 
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`
`
`TABLE OF AUTHORITIES
`
`
`
`Page(s)
`
`Cases
`
`3M Innovative Properties Co. v. Tredegar Corp.,
`725 F.3d 1315 (Fed. Cir. 2013)................................................................................................24
`
`Fin Control Sys. Pty. Ltd. v. OAM, Inc.,
`265 F.3d 1311 (Fed. Cir. 2001).......................................................................................... 18-19
`
`Gillette Co. v. Energizer Holdings, Inc.,
`405 F.3d 1367 (Fed. Cir. 2005)................................................................................................10
`
`Hockerson-Halberstadt, Inc. v. Converse Inc.,
`183 F.3d 1369 (Fed. Cir. 1999)................................................................................................14
`
`Interval Licensing LLC v. AOL, Inc.,
`766 F.3d 1364 (Fed. Cir. 2014)................................................................................................16
`
`Jack Guttman, Inc. v. Kopykake Enterprises, Inc.,
`302 F.3d 1352 (Fed. Cir. 2002)................................................................................................14
`
`Mentor Graphics Corp. v. EVE-USA, Inc.,
`851 F.3d 1275 (Fed. Cir. 2017)................................................................................................16
`
`Micro Chem., Inc. v. Great Plains Chem. Co.,
`194 F.3d 1250 (Fed. Cir. 1999)..................................................................................................8
`
`Nevro Corp. v. Boston Scientific Corporation,
`955 F.3d 35, 133 U.S.P.Q.2d (Fed. Cir. 2020) ........................................................................16
`
`SRI International v. Matsushita Elec. Corp. of America,
`775 F.2d 1107 (Fed. Cir. 1985)................................................................................................10
`
`SZ DJI Technology Co., Ltd. v. Autel Robotics USA LLC,
`2019 WL 6840357 (D. Del. 2019) ...........................................................................................16
`
`TecSec, Inc. v. Adobe Sys. Inc.,
`658 F. App’x 570 (Fed. Cir. 2016) ..........................................................................................18
`
`Unique Concepts, Inc. v. Brown,
`939 F.2d 1558 (Fed. Cir. 1991)................................................................................................10
`
`Statute
`
`35 U.S.C. § 112 ..........................................................................................................................8, 15
`
`
`
`ii
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`I.
`
`INTRODUCTION
`
`
`
`Analog proposes construing the disputed claim terms consistent with their ordinary
`
`meanings and, where applicable, the patents’ lexicography. Xilinx, on the other hand, attempts to
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`improperly import multiple limitations into these patents in an effort to avoid infringement.
`
`Xilinx’s constructions are not supported by the intrinsic evidence. They also are inconsistent with
`
`its positions in multiple co-pending IPRs. Analog accordingly requests that the Court adopt its
`
`proposed constructions.
`
`II.
`
`TECHNOLOGY BACKGROUND
`
`Analog is a leading provider of analog to digital converters (ADC). Analog’s patents
`
`disclose sophisticated circuit components for use in high speed ADCs.
`
`ADCs convert analog signals (continuous signals, such as wireless transmissions or radio
`
`signals) into digital signals that can be processed by computers.
`
`ADCs accomplish this conversion by “sampling” the analog signal at different points in
`
`time, “quantizing” the amplitudes of the samples as numeric values, then “encoding” the quantized
`
`values as bits (i.e., 0s and 1s). These tasks, including sampling, may be coordinated by clock
`
`
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`signals.
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`
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`1
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`“residue” corresponding to a remaining portion of the analog signal. Id., 7:55-68. The second
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`converter core (10a) quantizes that residue into a digital representation of the remaining portion of
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`the analog signal. Id., 7:66-8:3. The digital representations from each core are then combined by
`
`combiner (30) to provide the digital representation for the full analog signal. Id., 8:4-9.
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`3
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`difference between the input signal and the analog
`representation of the first digital result;
`a second converter core for performing a second part of
`the analog to digital conversion by converting the first
`residue;
`wherein the analog to digital further comprises a controller for
`controlling the operation of the engines such that the
`engines co-operate to perform a successive approxima-
`tion search, and wherein the first converter core is
`further operable to act as the first residue generator.
`
`3.
`
`Analog’s Proposed Construction
`
`
`
`The primary dispute is whether these terms are structural or functional.
`
`Analog contends that the terms are structural, and that they should be construed consistent
`
`with their plain/ordinary meanings. As the Federal Circuit confirmed in Williamson v. Citrix
`
`Online, LLC, if “the words of the claim are understood by persons of ordinary skill in the art to
`
`have a sufficiently definite meaning as the name for structure,” it is not means-plus-function. 792
`
`F.3d 1339, 1349 (Fed. Cir. 2015). That is certainly the case here. As Dr. Hanumolu confirms, a
`
`person of ordinary skill in the art (“POSITA”) would understand “converter core” to refer to
`
`structure, namely, the converter circuitry that converts analog signals into digital representations.
`
`Declaration of Pavan Hanumolu (“Hanumolu Decl.”), ¶11. Indeed, in Genuine Enabling
`
`Technology LLC v. Sony Corp., the parties agreed that a POSITA would “readily underst[an]d”
`
`the meaning of “converter” “without the need for clarification and it connotes sufficiently definite
`
`structure—a device that converts data or signals from one form to another.” Ex. 2, C.A. No. 17-
`
`135 (D.D.E. Mar. 9, 2020), slip op. at 28.
`
`The claims and specification both use the term, consistent with this ordinary meaning, to
`
`refer to structure. They confirm, for example, that the claimed converters include “converter
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`cores” with engines that perform the conversion. Ex. 1, ’321 patent, claims 1, 14 (referring to
`
`
`
`
`5
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`converter cores with switched capacitor engines); Fig. 2, 1:5-9, 2:51-3:3, 3:8-36, 7:17-29
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`(describing cores).
`
`Xilinx’s position is inconsistent not only with Williamson, but also with its own
`
`representations in public literature, in filings with the PTAB, and even in this case. To provide a
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`few of many examples:
`
` Xilinx consistently uses the terms “converter,” “converter core,” and “core” to refer to
`
`structures in its own literature. See, e.g., Ex. 3, Erdmann et al., A Heterogeneous 3D-
`
`IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data
`
`Converters, JSSC Vol. 50 No. 1 (2015) at 259 (referencing “data converter core”); Ex.
`
`4, Collins et al., RFSoC Integrates RF Sampling Data Converters for 5G New Radio,
`
`Microwave Journal, June 2017 at 24 (referencing “analog to digital converters”); Ex.
`
`5, Refai-Ahmed et al., Extending the Cooling Limit of Remote Radio Head (RRH)
`
`Systems Based on Level 1 Thermal Management, 2018 IEEE 20th Electronics
`
`Packaging Technology Conference (EPTC), Singapore, Singapore, 2018, at 1
`
`(referencing “analog to digital (ADC) and digital to analog (DAC) converters”); Ex.
`
`18, B. Jiao and Mayder, Critical on-Board Crosstalk Path Optimization for RFSoC
`
`with Multiple Gsps RF ADCs and DACs, 2018 IEEE 27th Conference on Electrical
`
`Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, 2018, at
`
`275 (referencing “analog to digital converters”); see also Hanumolu Decl., ¶12.1
`
` Xilinx has filed multiple IPRs challenging Analog patent claims with “converter”
`
`terms, and in every one of those contends these terms have plain/ordinary meanings.
`
`See, e.g., Ex. 6, IPR2020-01219, Petition, 14, 21, 30, 89-90 (claiming “converter” terms
`
`
`1 All emphasis added unless otherwise noted.
`
`
`
`
`6
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`have plain/ordinary meanings); Ex. 7, IPR2020-01484, Petition, 23, 28, 30, 38-39, 45
`
`(claiming “converter circuits”/“converter” terms have plain/ordinary meanings); Ex. 8,
`
`IPR2020-01483, Petition, 25, 97-102 (same); Ex. 19, IPR2020-01564, Petition, 33, 35,
`
`37, 39, 89-91 (same); Ex. 9, IPR2020-01559, Petition, 23-24, 38-58 (claiming ADC
`
`“converter” has plain/ordinary meaning); Ex. 10, IPR2020-01561, Petition, 16-20, 102-
`
`105 (claiming ADC “converter” and “signal converters” have plain/ordinary
`
`meanings).
`
` Xilinx concedes in this case that the “converter” term in Analog’s ’750 patent is not
`
`means-plus-function. See infra. p.19.
`
` Xilinx also treats the “converter circuits” terms in its own asserted U.S. Patent No.
`
`8,548,071 as structural, not identifying these terms for construction as is required for
`
`means-plus-function terms. See Xilinx’s Answer and Counterclaims, Jan. 21, 2020
`
`(D.I. 11); Ex. 8.2
`
`Moreover, even if the ’321 patent terms were purely functional – which they are not –
`
`Xilinx’s lengthy list of corresponding structure is not required to perform the purported function.
`
`Instead, the only required structure is one or more conversion engines. Micro Chem., Inc. v. Great
`
`Plains Chem. Co., 194 F.3d 1250, 1258 (Fed. Cir. 1999) (“Nor does [35 U.S.C. §112 ¶6] permit
`
`incorporation of structure from the written description beyond that necessary to perform the
`
`claimed function.”).
`
`
`
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`2 Xilinx also has consistently treated other “core” terms as structural. See, e.g., Ex. 21, Price and
`Patterson, Reconfigurable Breakpoints for Co-debug, FPL 2001, LNCS 2147 (2001) at 478
`(referencing a “global clock converter core”). See also Hanumolu Decl., ¶13.
`7
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`Analog proposes construing the terms consistent with their plain/ordinary meanings. As
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`Dr. Hanumolu confirms, the claims and specification use these terms consistent with these ordinary
`
`meanings, to confirm that the engines are working jointly together toward the same end.
`
`Hanumolu Decl., ¶15; see, also Ex. 11, Cambridge Dictionary (defining cooperate as “to act or
`
`work together for a particular purpose”); Ex. 12, Oxford English Dictionary (defining cooperate
`
`as “[t]o work together, act in conjunction (with another person or thing, to an end or purpose, or
`
`in a work).”
`
`
`
`Moreover, the ’321 claims specifically describe the nature of the cooperation. Claim 1
`
`states, for example, that the engines “co-operate to perform a successive approximation search.”
`
`Claims 15-16, in contrast to claim 1, state that the engines cooperate to perform the conversion
`
`“where at least two bits can be determined during a single trial step.” Ex. 1, ’321 patent, claim 16;
`
`see also claim 15 (similar language). And claim 2 further limits claim 1 by specifying that “at
`
`least one of the converter cores can determine a plurality of bits during a single trial step.” Id.,
`
`claim 2.
`
`
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`Xilinx’s proposed constructions violate multiple basic claim construction principles. First,
`
`Xilinx, attempts to read an exemplary embodiment into the claims. See, e.g., id., 3:29-35 (“As a
`
`further enhancement to throughput, at least one, and preferably both the first and second
`
`converter cores comprise at least three successive approximation converter engines arranged in
`
`parallel and operating in a co-operative manner such that each successive conversion cycle within
`
`a single converter core can determine two bits simultaneously.”). It is a basic rule of claim
`
`construction that preferred embodiments generally should not be imported into the claims. See,
`
`e.g., Gillette Co. v. Energizer Holdings, Inc., 405 F.3d 1367, 1371 (Fed. Cir. 2005).
`
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`
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`9
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`specific voltage, so that the analog input signal is sampled precisely with limited distortion.
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`Ordinarily, this bootstrapped circuit employs a positive feedback loop to provide this specific turn-
`
`on voltage to the sampling switch during a sampling period. Ex. 13, ’250 patent, 3:56-4:8.
`
`The ’250 inventors recognized that, although positive feedback loops are considered fast,
`
`they can be too slow for ultra-high speed sampling. The inventors thus created a bootstrapped
`
`switching circuit with a “jump start circuit” which, as its name suggests, jumpstarts the operation
`
`of the bootstrapped switching circuit by turning on the output transistor.
`
`Figure 3 shows an example of the invention:
`
`The sampling switch (MN 108) receives the analog input signal (VINX) , and when turned
`
`on with an appropriate control voltage (VBSTRP) during the sampling period, allows the analog
`
`input signal (VINX) to pass to the “sampling capacitor.” Id., 3:1-5, 4:64-67. An input transistor
`
`(MN 212) and boot capacitor (CBOOT) generate the appropriate control voltage (VBSTRP). An
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`11
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`output transistor (MP 202), when turned on, passes the appropriate control voltage (VBSTRP) from
`
`boot capacitor CBOOT to the sampling switch (MN 108) . The positive feedback loop, having
`
`input transistor (MN 212) and output transistor (MP 202), generates the appropriate control
`
`voltage to turn on the sampling switch (MN 108) during the sampling period. Id., 6:22-48.
`
`The jumpstart circuit “jump starts” this process by turning on the output transistor
`
`(MP 202) during “startup” of the positive feedback loop (i.e., beginning when the system clock
`
`turns “high”), and keeping the output transistor (MP 202) turned on for a short period of time
`
`during the startup of the positive feedback loop. Id.; see also, id., 5:12-13. After that limited
`
`period of time, the positive feedback loop continues assisting the output transistor (MP 202) in
`
`generating the appropriate voltage to sampling switch (MN 108). Id., 6:22-48.
`
`2.
`
`Representative Claim
`
`U.S. Patent No. 10,250,250 Claim 1
`
`A bootstrapped switching circuit with accelerated turn
`on, comprising:
`a sampling switch to receive a voltage input signal and a
`gate voltage;
`a bootstrapped voltage generator comprising a positive
`feedback loop, wherein the positive feedback loop is
`activated by a clock signal to generate the gate voltage
`for turning on the sampling switch, and the positive
`feedback loop comprises: an output transistor to output
`the gate voltage of the sampling switch, and an input
`transistor to receive the voltage input signal and to be
`driven by the gate voltage as positive feedback;
`and a jump start circuit to turn on the output transistor, and to
`cease turning on the output transistor after a limited
`period of time during a startup of the positive feedback
`loop to allow the positive feedback loop to continue
`assisting the output transistor in generating the gate
`voltage for turning on the sampling switch.
`
`3.
`
`Analog’s Proposed Construction
`
`The primary dispute is the role of the “jump start circuit.”
`
`12
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`31. The patent further confirms that this timing “can vary depending on implementation” (id.,
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`6:59-60), explicitly identifies and discusses factors that can be used to determine this timing (7:20-
`
`30), and confirms that it “can be determined from simulations or testing” (7:24-25). As Dr.
`
`Hanumolu confirms, a POSITA reading the specification could readily determine this timing.
`
`Hanumolu Decl., ¶19.
`
`
`
`Xilinx’s contention that this term is indefinite is inconsistent both with the caselaw and
`
`with its own IPR petition on the ’250 patent. As the Federal Circuit has confirmed, “[c]laim
`
`language employing terms of degree has long been found definite where it provide[s] enough
`
`certainty to one of skill in the art when read in the context of the invention.” Interval Licensing
`
`LLC v. AOL, Inc., 766 F.3d 1364, 1370 (Fed. Cir. 2014). That is certainly the case here, and it has
`
`been found so in other cases where, as here, the specification teaches a POSITA how to determine
`
`if the claim term is met. See Mentor Graphics Corp. v. EVE-USA, Inc., 851 F.3d 1275, 1291 (Fed.
`
`Cir. 2017) (claim term “near” sufficiently definite where the specification taught a POSITA how
`
`to evaluate nearness); SZ DJI Tech. Co. v. Autel Robotics USA LLC, Civ. A. No. 16-706-LPS, 2019
`
`WL 6840357, *4-5 (D. Del. Dec. 16, 2019) (claim language “sufficiently distal” not indefinite
`
`where “[t]he specification teaches that the meaning of the term may vary depending on certain
`
`conditions”); Nevro Corp. v. Boston Scientific Corp., 955 F.3d 35, 39-40 (Fed. Cir. 2020) (claim
`
`term “paresthesia-free” not indefinite where the specification “teaches how to generate and deliver
`
`the claimed signals using the recited parameters”).
`
`Consistent with this case law, and inconsistent with its position here, Xilinx expressly
`
`represented to the Patent Office – in its IPR petition challenging the ’250 patent – that these terms
`
`could be understood based on their plain/ordinary meanings. See Ex. 14, IPR2020-01210, Petition,
`
`13.
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`15
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`a first converter;
`a random clock, said random clock configured to decor-
`relate an input signal provided to said first converter
`from said random clock so that the average output
`signal of said first converter is proportional to a first
`offset signal; and
`a first offset sensor connected to sense the first offset
`signal, and in response to said sensing, to condition said
`first converter output.
`
`
`3.
`
`Analog’s Proposed Construction
`
`
`
`The primary dispute is whether the claimed “random clock” can include a random clock
`
`generator, a pseudorandom clock generator, or an aperiodic clock generator.
`
`Analog proposes construing the term consistent with the complete lexicography in the
`
`patent. Specifically, the specification states:
`
`The term “random clock signal” is used here and throughout the disclosure to define
`clock signals where a previous portion of the clock signal is not used to determine
`a future portion of the clock signal. The random clock signals can be provided by
`a random clock generator, a pseudorandom clock generator, or an aperiodic clock
`generator.
`
`Id., 5:57-63. As Dr. Hanumolu confirms, a POSITA would appreciate, consistent with this
`
`lexicography, that a random clock signal can be generated with a random, pseudorandom, or
`
`aperiodic clock generator, as the specification confirms. Hanumolu Decl., ¶20.
`
`
`
`Analog’s proposal is also consistent with the claim language. Claim 2 expressly recites
`
`that the “random clock” referenced in claim 1 includes “at least one of a random clock generator,
`
`a pseudorandom clock generator, and an aperiodic clock generator.” Ex. 15, ’750 patent, claim
`
`2. An independent claim should not be limited to a dependent claim, and must be at last broad
`
`enough to include it. The “random clock” in claim 1, therefore, must be broad enough to
`
`encompass these examples. TecSec, Inc. v. Adobe Sys. Inc., 658 F. App’x 570, 577 (Fed. Cir.
`
`2016) (explaining that “the limitation in the parent be at least broad enough to encompass the
`
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`17
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`2.
`
`Representative Claim
`
`U.S. Patent No. 7,286,075 Claim 1
`
`An analog to digital converter for converting an analog
`input signal to a digital output signal, comprising
` a first group of capacitors for participation in a successive approxi-
`mation conversion, each capacitor having at least one asso-
`ciated switch for controllably connecting a terminal of the
`capacitor to a first reference voltage or to a second reference
`voltage;
`a second group of capacitors for applying a dither
`and having switches for selectively connecting the capaci-
`tors to the first reference voltage or the second reference
`voltage and a sequence generator for generating a sequence
`of bits, wherein during sampling of the analog input signal
`onto at least some of the capacitors of the first group of
`capacitors or during conversion of a sample of the analog
`input signal an output of the sequence generator is supplied
`to the switches of the second group of capacitors to control
`whether a given capacitor within the second group is con-
`nected by its associated switch to the first reference voltage
`or to the second reference voltage, so as to apply a dither to
`said conversion.
`
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`3.
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`Analog’s Proposed Construction
`
`The parties dispute whether the first and second groups of capacitors must have entirely
`
`distinct capacitors all used “exclusively and only” for one specific function, or whether the
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`capacitors can have multiple functions.
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`Analog proposes construing these terms consistent with their ordinary meanings, which do
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`not require the specificity or exclusivity that Xilinx attempts to read into the claims. See Hanumolu
`
`Decl., ¶21. The term “exclusively” does not appear in the claims, and the only time “exclusively”
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`appears in the specification, it undermines Xilinx’s constructions. See, e.g., Ex. 16, ’075 patent,
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`8:16-19 (confirming capacitors AC1 to AC3 can be used “either exclusively” to implement the
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`dither, “or in addition to the lower weight capacitors of the sub DAC in order to implement the
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`dither functionality.”); see also id., 9:30-35 (“the dither capacitors do not necessarily have to be
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`21
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`additional capacitors but could be selected from capacitors of the sample and convert switched
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`capacitor array.”). The specification further confirms that the capacitors can have functions
`
`beyond sampling, conversion, and dither, including for example “error correction” and a “improve
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`the signal to noise ratio.” Id., 7:1-7, 11:16, 20-24; see also Hanumolu Decl., ¶21.
`
`Xilinx appears to be basing its proposals on the prosecution history of the patent, but it is
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`plainly misreading that history. See Hanumolu Decl., ¶22. During prosecution, the inventors made
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`some amendments to distinguish U.S. Patent No.7,015,853 (“Wolff”), confirming for claim 1 that
`
`the invention included a “first group of capacitors” used for conversion and a “second group of
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`capacitors” for applying dither. Ex. 17, 12/4/2006 Response, at 5. The inventors explained, in
`
`making this amendment, that Wolff did not disclose a “second group of capacitors (which does
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`not participate in the conversion) for applying a dither to the conversion.” Id., 12. But the
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`inventors in no way limited their invention to a “first group of capacitors” used “exclusively and
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`only” for sampling and converting, or a “second group of converters” used “exclusively and only”
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`for applying dither. Instead, the inventors simply stated that the second group of capacitors does
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`not participate in the conversion.
`
`Nothing in the claims or prosecution history precludes any of the capacitors in the first or
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`second groups of capacitors from being used for additional functions beyond dither or conversion,
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`including, for example, error correction, or processes to improve the signal to noise ratio. In short,
`
`nothing in the prosecution history demands the exclusivity Xilinx proposes. 3M Innovative
`
`Properties Co. v. Tredegar Corp., 725 F.3d 1315, 1325 (Fed. Cir. 2013) (“[I]n order for
`
`prosecution disclaimer to attach, the disavowal must be both clear and unmistakable.”); see also
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`Hanumolu Decl., ¶22
`
`
`
`
`22
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1027 Page 26
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1027 Page 27
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`of capacitors …”); id., 2:15-17 (“Advantageously some of the capacitors of the array are used to
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`sample an input signal as well as being involved in its conversion.”); id., 2:18-20 (“Preferably the
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`second group of capacitors are selected from the least significant capacitors within the array of
`
`capacitors.”).
`
`
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`Xilinx proposes overly narrow and unnecessary constructions aimed at attempting to read
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`the same “exclusively and only” language into the array as it does into the two groups of capacitors.
`
`There is no basis for these constructions.
`
`
`
`
`
`
`
`MORRIS, NICHOLS, ARSHT & TUNNELL LLP
`
`/s/ Brian P. Egan
`
`
`
`
`Jack B. Blumenfeld (#1014)
`Brian P. Egan (#6227)
`1201 North Market Street
`P.O. Box 1347
`Wilmington, DE 19899
`(302) 658-9200
`jblumenfeld@mnat.com
`began@mnat.com
`
`Attorneys for Plaintiff / Counterclaim
`Defendant Analog Devices, Inc.
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`
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`OF COUNSEL:
`
`William F. Lee
`Cynthia D. Vreeland
`Peter M. Dichiara
`Stephanie Neely
`Nicole M. Fontaine Dooley
`WILMER CUTLER PICKERING HALE
` AND DORR LLP
`60 State Street
`Boston, MA 02109
`(617) 526-6000
`
`Keith Howell
`WILMER CUTLER PICKERING HALE
` AND DORR LLP
`1875 Pennsylvania Avenue, NW
`Washington, DC 20006
`(202) 663-6000
`
`
`
`
`
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`

`Aaron Thompson
`WILMER CUTLER PICKERING HALE
` AND DORR LLP
`350 South Grand Avenue, Suite 2400
`Los Angeles, CA 90071
`(213) 443-5300
`
`November 5, 2020
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`CERTIFICATION OF COMPLIANCE
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`
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`The undersigned hereby certifies that the foregoing document complies with the Court’s
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`word count limitations set forth in Paragraph 10 of the Scheduling Order (D.I. 28), as it contains
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`4,979 words counted by Microsoft Word, excluding pictures, figures copied from the patent,
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`illustrations, representative claims, the agreed-upon claim constructions, and the tables setting
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`forth the parties’ competing constructions per D.I. 28 footnotes 3 and 4, and excluding the case
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`caption, table of contents, table of authorities, and signature blocks.
`
`
`
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`
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`
`
`/s/ Brian P. Egan
`
`
`
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`Brian P. Egan (#6227)
`
`
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`1
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1027 Page 30
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`CERTIFICATE OF SERVICE
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`I hereby certify that on November 5, 2020, copies of the foregoing were caused to be served
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`VIA ELECTRONIC MAIL
`
`VIA ELECTRONIC MAIL
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`VIA ELECTRONIC MAIL
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`VIA ELECTRONIC MAIL
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`upon the following in the manner indicated:
`
`Anne Shea Gaza, Esquire
`Robert M. Vrana, Esquire
`Samantha G. Wilson, Esquire
`YOUNG CONAWAY STARGA