throbber
Trials@uspto.gov
`571-272-7822
`
` Paper 42
`Entered: July 8, 2022
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC., MICRON SEMICONDUCTOR
`PRODUCTS, INC., MICRON TECHNOLOGY TEXAS LLC,
`DELL TECHNOLOGIES INC., DELL INC., and HP INC.,
`Petitioner,
`v.
`UNIFICATION TECHNOLOGIES LLC,
`Patent Owner.
`
`IPR2021-00343
`Patent 8,533,406 B2
`
`
`
`
`
`
`
`
`
`Before JUSTIN T. ARBES, TERRENCE W. McMILLIN, and
`CHRISTOPHER L. OGDEN, Administrative Patent Judges.1
`ARBES, Administrative Patent Judge.
`
`JUDGMENT
`Final Written Decision
`Determining Some Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`
`
`1 Katherine K. Vidal, Under Secretary of Commerce for Intellectual Property
`and Director of the United States Patent and Trademark Office (Director),
`is recused from this proceeding and took no part in this decision. See
`Director’s Memorandum, Procedures for Recusal to Avoid Conflicts of
`Interest and Delegations of Authority (Apr. 20, 2022) (Recusal Procedure
`Memo), available at https://go.usa.gov/xJjch; Interim Process for Director
`Review (§ 20), available at https://go.usa.gov/xJjce.
`
`

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`IPR2021-00343
`Patent 8,533,406 B2
`
`INTRODUCTION
`I.
`A. Background and Summary
`Petitioners Micron Technology, Inc., Micron Semiconductor Products,
`Inc., Micron Technology Texas LLC, Dell Technologies Inc., Dell Inc., and
`HP Inc. (collectively, “Petitioner”) filed a Petition (Paper 4, “Pet.”)
`requesting inter partes review of claims 15–21 and 26–30 of U.S. Patent
`No. 8,533,406 B2 (Ex. 1001, “the ’406 patent”) pursuant to 35 U.S.C.
`§ 311(a). On July 9, 2021, we instituted an inter partes review as to all
`challenged claims on all grounds of unpatentability asserted in the Petition.
`Paper 9 (“Decision on Institution” or “Dec. on Inst.”). Patent Owner
`Unification Technologies LLC subsequently filed a Patent Owner Response
`(Paper 21, “PO Resp.”), Petitioner filed a Reply (Paper 28, “Reply”), and
`Patent Owner filed a Sur-Reply (Paper 33, “Sur-Reply”). An oral hearing
`was held on April 13, 2022, and a transcript of the hearing is included in the
`record (Paper 36, “Tr.”).
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision is issued pursuant to 35 U.S.C. § 318(a). For the reasons that
`follow, we determine that Petitioner has shown by a preponderance of the
`evidence that claims 15–21 and 26 of the ’406 patent are unpatentable, and
`we cannot reach a decision on the merits with respect to whether Petitioner
`has established the unpatentability of claims 27–30.
`
`
`B. Related Matters
`The parties indicate that the ’406 patent is the subject of the following
`district court cases: Unification Technologies LLC v. Dell Technologies,
`Inc., Case No. 6:20-cv-499-ADA (W.D. Tex.), Unification Technologies
`LLC v. HP Inc., Case No. 6:20-cv-501-ADA (W.D. Tex.), and Unification
`
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`IPR2021-00343
`Patent 8,533,406 B2
`Technologies LLC v. Micron Technology, Inc., Case No. 6:20-cv-500-ADA
`(W.D. Tex.) (“the district court case”). Pet. 66; Paper 6, 2–3. Petitioner also
`filed petitions challenging claims of patents related to the ’406 patent in
`Cases IPR2021-00344 and IPR2021-00345.
`
`
`C. The ’406 Patent
`The ’406 patent discloses techniques for “managing data in a storage
`device using an empty data segment directive.” Ex. 1001, col. 1, ll. 28–30.
`“Typically, when data is no longer useful it may be erased. In many file
`systems, an erase command deletes a directory entry in the file system while
`leaving the data in place in the storage device containing the data,” such that
`the storage device is unaware that the data is now invalid. Id. at col. 1,
`ll. 32–36. “Another method of erasing data is to write zeros, ones, or some
`other null data character to the data storage device to actually replace the
`erased file,” but doing so is inefficient because “valuable bandwidth is used
`while transmitting the data” and “space in the storage device is taken up by
`the data used to overwrite invalid data.” Id. at col. 1, ll. 36–42. The
`’406 patent attempts to overcome these issues by having the storage device
`“receive a directive that data is to be erased” and store a “data segment
`token” that represents erased data, rather than performing either of the
`typical erase methods. Id. at col. 1, l. 63–col. 2, l. 1.
`
`
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`IPR2021-00343
`Patent 8,533,406 B2
`Figure 1A of the ’406 patent is reproduced below.
`
`
`Figure 1A depicts clients 114 in communication over computer network 116
`with computer 112 having solid-state storage device 102.2 Id. at col. 6,
`ll. 44–51. Solid-state storage device 102 comprises solid-state storage 110
`(e.g., flash memory) and solid-state storage controller 104 for writing to
`solid-state storage 110 (via write data pipeline 106), reading from solid-state
`storage 110 (via read data pipeline 108), and performing other operations on
`
`
`2 A solid-state storage device is a type of non-volatile memory that stores
`data in pages within blocks, where each page is identified by a unique
`physical address. Data in a solid-state storage device cannot be directly
`overwritten with new data, but instead must first be erased (at the block
`level) and then written (to pages). See Ex. 1001, col. 1, ll. 43–50.
`
`4
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`IPR2021-00343
`Patent 8,533,406 B2
`solid-state storage 110. Id. at col. 6, ll. 52–59. When a “data packet is
`stored and the physical address of the data packet is assigned,” the
`solid-state storage controller creates an entry in an index that maps a “logical
`identifier” of the object to “one or more physical addresses corresponding to
`where the storage controller” stored the data packet and any object metadata
`packets. Id. at col. 11, ll. 53–59.
`Write data pipeline 106 includes garbage collector bypass 316 that
`“receives data segments from the read data pipeline 108 as part of a data
`bypass in a garbage collection system.” Id. at col. 27, ll. 19–22, Fig. 3.
`According to the ’406 patent,
`[a] garbage collection system typically marks packets that are no
`longer valid, typically because the packet is marked for deletion
`or has been modified and the modified data is stored in a different
`location. At some point, the garbage collection system deter-
`mines that a particular section of storage may be recovered. This
`determination may be due to a lack of available storage capacity,
`the percentage of data marked as invalid reaching a threshold, a
`consolidation of valid data, an error detection rate for that section
`of storage reaching a threshold, or improving performance based
`on data distribution, etc. Numerous factors may be considered
`by a garbage collection algorithm to determine when a section of
`storage is to be recovered.
`Id. at col. 27, ll. 22–34. The ’406 patent discloses an apparatus comprising
`(1) a “request receiver module” that “receive[s] an indication identifying
`data that can be erased from a non-volatile storage medium,” where the
`indication identifies the data using a “logical identifier,” (2) a “marking
`module” that “invalidate[s] an association between the logical identifier and
`the physical address” to which the logical identifier is mapped in the index,
`(3) a “storage recovery module” that “recover[s] the physical storage
`location at the physical address” at an appropriate time, and (4) a “storage
`
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`IPR2021-00343
`Patent 8,533,406 B2
`module” that “store[s] data associated with another logical identifier on the
`physical storage location in response to recovering the physical storage
`location.” Id. at col. 2, l. 61–col. 3, l. 39.
`
`
`D. Illustrative Claim
`Challenged claims 15, 27, and 30 of the ’406 patent are independent.
`Claims 16–21 and 26 depend from claim 15, and claims 28 and 29 depend
`from claim 27. Claim 15 recites:
`15. An apparatus, comprising:
`a non-volatile storage medium;
`a request receiver module of a storage layer for the
`non-volatile storage medium configured to receive an indication
`that a data structure, corresponding to data stored on the
`non-volatile storage medium, has been deleted, wherein the
`indication comprises a logical identifier that is associated with
`the data structure by a storage client, and wherein the logical
`identifier is mapped to a physical address of the data on the
`non-volatile storage medium; and
`a marking module configured to record that the data stored
`at the physical address mapped to the logical identifier can be
`erased from the non-volatile storage medium in response to
`receiving the indication.
`
`
`E. Evidence
`The pending grounds of unpatentability in the instant inter partes
`review are based on the following prior art:
`U.S. Patent No. 7,624,239 B2, filed Nov. 14, 2005, issued
`Nov. 24, 2009 (Ex. 1002, “Bennett”);
`U.S. Patent No. 7,057,942 B2, issued June 6, 2006
`(Ex. 1003, “Suda”); and
`Eran Gal & Sivan Toledo, “Mapping Structures for Flash
`Memories: Techniques and Open Problems,” Proceedings of the
`
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`IPR2021-00343
`Patent 8,533,406 B2
`IEEE International Conference on Software – Science,
`Technology & Engineering (SwSTE’05), Aug. 2005 (Ex. 1010,
`“SwSTE’05”).
`Petitioner filed a declaration from R. Jacob Baker, Ph.D., P.E. (Ex. 1004)
`with its Petition. Patent Owner filed a declaration from Vijay K. Madisetti,
`Ph.D. (Ex. 2010) with its Response. Also submitted as evidence are
`transcripts of the depositions of Dr. Baker (Ex. 2012) and Dr. Madisetti
`(Ex. 1038).
`
`
`35 U.S.C. §
`103(a)3
`
`Reference(s)/Basis
`Bennett4
`
`F. Asserted Grounds
`This inter partes review involves the following grounds of
`unpatentability:
`Claims Challenged
`15–21, 26–30
`
`3 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011) (“AIA”), amended 35 U.S.C. §§ 103 and 112. Because the
`challenged claims of the ’406 patent have an effective filing date before the
`effective date of the applicable AIA amendments, we refer to the pre-AIA
`versions of 35 U.S.C. §§ 103 and 112. See Pet. 4–5.
`4 Petitioner asserts that the challenged claims are unpatentable over
`(1) Bennett, (2) Suda, and (3) Suda and SwSTE’05, each “in view of a
`[person of ordinary skill in the art’s] knowledge.” Pet. 8. As explained in
`the Decision on Institution, we do not include the general knowledge of a
`person of ordinary skill in the art in listing the grounds themselves,
`recognizing that such knowledge is considered in every obviousness
`analysis. See Dec. on Inst. 6 n.3; 35 U.S.C. § 311(b) (inter partes review
`“only on the basis of prior art consisting of patents or printed publications”);
`Koninklijke Philips N.V. v. Google LLC, 948 F.3d 1330, 1337 (Fed. Cir.
`2020) (“Although the prior art that can be considered in inter partes reviews
`is limited to patents and printed publications, it does not follow that we
`ignore the skilled artisan’s knowledge when determining whether it would
`have been obvious to modify the prior art. . . . Regardless of the tribunal, the
`inquiry into whether any ‘differences’ between the invention and the prior
`
`7
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`IPR2021-00343
`Patent 8,533,406 B2
`Claims Challenged
`15–21, 26–30
`21, 26, 28
`
`
`
`35 U.S.C. §
`103(a)
`103(a)
`
`Reference(s)/Basis
`Suda
`Suda, SwSTE’05
`
`II. ANALYSIS
`A. Level of Ordinary Skill in the Art
`In determining the level of ordinary skill in the art for a challenged
`patent, we look to “1) the types of problems encountered in the art; 2) the
`prior art solutions to those problems; 3) the rapidity with which innovations
`are made; 4) the sophistication of the technology; and 5) the educational
`level of active workers in the field.” Ruiz v. A.B. Chance Co., 234 F.3d 654,
`666–667 (Fed. Cir. 2000). “Not all such factors may be present in every
`case, and one or more of them may predominate.” Id.
`Petitioner states that it assumes an effective filing date of December 6,
`2006, for the challenged claims of the ’406 patent, and argues that a person
`of ordinary skill in the art at that time would have had “a Bachelor of
`Science degree in computer science or electrical engineering and at least two
`years of experience in the design, development, implementation, or
`management of solid-state memory devices.” Pet. 4–5 (citing Ex. 1004
`¶ 55). According to Petitioner, an ordinarily skilled artisan also
`
`art would have rendered the invention obvious to a skilled artisan necessarily
`depends on such artisan’s knowledge.”); Randall Mfg. v. Rea, 733 F.3d
`1355, 1362 (Fed. Cir. 2013) (“[T]he knowledge of [an ordinarily skilled]
`artisan is part of the store of public knowledge that must be consulted when
`considering whether a claimed invention would have been obvious.”);
`Dow Jones & Co. v. Ablaise Ltd., 606 F.3d 1338, 1349 (Fed. Cir. 2010)
`(“[The obviousness] analysis requires an assessment of the . . . ‘background
`knowledge possessed by a person having ordinary skill in the art.’” (citing
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 401 (2007))).
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`IPR2021-00343
`Patent 8,533,406 B2
`would have known, as background information: how flash
`memory erases data, how flash memory programs or writes data,
`how memory is used in a cache hierarchy, relative speeds of flash
`memory compared to other memory, how garbage collection is
`used with flash memory, how to use wear leveling to combat
`endurance limits of flash memory, how the [Flash Translation
`Layer (“FTL”)] works, and industry standards affecting flash
`memory including the [Advance Technology Attachment
`(“ATA”)] standard.
`Id. (citing Ex. 1004 ¶¶ 55–56). Patent Owner applies the same definition of
`the level of ordinary skill in the art. PO Resp. 17 (citing Ex. 2010
`¶¶ 47–52). Based on the full record developed during trial, including our
`review of the ’406 patent and the types of problems and solutions described
`in the ’406 patent and cited prior art, we agree with Petitioner’s proposed
`definition of the level of ordinary skill in the art and apply it for purposes of
`this Decision. See, e.g., Ex. 1001, col. 1, ll. 25–59 (describing in the
`“Background of the Invention” section of the ’406 patent various write, read,
`and erase procedures for solid-state storage devices).
`
`
`B. Claim Interpretation
`We interpret the claims of the challenged patent
`using the same claim construction standard that would be used to
`construe the [claims] in a civil action under 35 U.S.C. 282(b),
`including construing the [claims] in accordance with the ordinary
`and customary meaning of such [claims] as understood by one of
`ordinary skill in the art and the prosecution history pertaining to
`the patent.
`37 C.F.R. § 42.100(b) (2020). “In determining the meaning of [a] disputed
`claim limitation, we look principally to the intrinsic evidence of record,
`examining the claim language itself, the written description, and the
`prosecution history, if in evidence.” DePuy Spine, Inc. v. Medtronic
`
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`Sofamor Danek, Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006). Claim terms
`are given their plain and ordinary meaning as would be understood by a
`person of ordinary skill in the art at the time of the invention and in the
`context of the entire patent disclosure. Phillips v. AWH Corp., 415 F.3d
`1303, 1313 (Fed. Cir. 2005) (en banc). “There are only two exceptions to
`this general rule: 1) when a patentee sets out a definition and acts as his own
`lexicographer, or 2) when the patentee disavows the full scope of a claim
`term either in the specification or during prosecution.” Thorner v. Sony
`Comput. Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012).
`After the Petition was filed, the district court issued a Claim
`Construction Order construing various terms of the ’406 patent:
`Claim Term
`Construction
`An identifier that can be associated
`with a physical address on a storage
`device for identifying data stored at
`the physical address
`
`“logical identifier”
`
`“logical identifier [that/in
`the index] is empty”
`
`Indefinite
`
`“marking module”
`
`“storage module”
`
`“index module”
`
`Not indefinite; not subject to §112(f);
`plain and ordinary meaning
`Not indefinite; not subject to §112(f);
`plain and ordinary meaning
`Not indefinite; not subject to §112(f);
`plain and ordinary meaning
`
`Ex. 2006, 2–3.
`We address three claim interpretation issues. First, in the Decision on
`Institution, based on the record at the time, we agreed with and adopted the
`district court’s construction of “logical identifier.” Dec. on Inst. 11–12. The
`parties agree with that construction. See PO Resp. 18; Reply 4. Based on
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`IPR2021-00343
`Patent 8,533,406 B2
`the full trial record, we interpret “logical identifier” in the same manner as
`the district court.
`Second, claim 27 recites “a request receiver module configured to
`receive an indication comprising a logical identifier that is empty,” and
`claim 30 similarly recites “a request receiver module configured to receive
`an indication that a specified logical identifier is empty” and “a read request
`response module configured to return an indication that the logical identifier
`is empty” (emphasis added). The district court’s Claim Construction Order
`lists “[i]ndefinite” as the final construction for the phrase “logical identifier
`[that/in the index] is empty.” Ex. 2006, 2 (alteration in original). Petitioner
`asserted in the Petition that we should instead adopt Patent Owner’s original
`proposed construction from the district court case of “data identified by the
`[logical identifier] that does not need to be preserved,” but Petitioner did not
`provide any explanation for why such an interpretation is justified. Pet. 6–7
`(alteration in original). In the Decision on Institution, based on the record at
`the time, we explained why we were “unable to interpret the ‘empty’ phrases
`in claims 27 and 30, and c[ould ]not ascertain the scope of the claims with
`reasonable certainty for purposes of assessing patentability.” Dec. on Inst.
`12–14. For example, we noted that, given the interpretation of “logical
`identifier” above, a logical identifier is simply “information identifying
`something else” and “either exists or does not exist”; it cannot be considered
`“empty.” Id. at 13. We encouraged the parties, to the extent they disagreed
`with that determination, to “provide an explanation and cite evidence in
`support of the proposed interpretation in their papers during trial.” Id. at 14.
`Patent Owner argues that, based on our earlier determination,
`Petitioner has failed to prove that claims 27–30 are unpatentable. PO Resp.
`22, 49, 53–54. Petitioner does not address claims 27–30 in its Reply.
`
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`Neither party provides any argument or evidence disputing our reasoning in
`the Decision on Institution or the district court’s conclusion that the claim
`phrases are indefinite. Based on the full trial record, we maintain our earlier
`determination and incorporate the previous analysis herein. See Dec. on
`Inst. 12–14.
`Third, with respect to the “module” terms listed above, neither party
`argues that the terms are means-plus-function limitations under 35 U.S.C.
`§ 112, sixth paragraph, and the district court construed them not to be
`means-plus-function limitations. See PO Resp. 18; Reply 4; Ex. 2006, 2–3.
`We presume that the terms are not means-plus-function limitations because
`they do not use the word “means” and find no basis on the record before us
`to conclude otherwise. See Dyfan, LLC v. Target Corp., 28 F.4th 1360,
`1365 (Fed. Cir. 2022) (“Because invoking § 112 ¶ 6 is typically a choice left
`to the claim drafter, we presume at the first step of the analysis that a claim
`limitation is subject to § 112 ¶ 6 when the claim language includes the term
`‘means.’ . . . The inverse is also true—we presume that a claim limitation is
`not drafted in means-plus-function format in the absence of the term
`‘means.’ . . . [T]his presumption is rebuttable [and] can be overcome if a
`challenger demonstrates that the claim term ‘fails to recite sufficiently
`definite structure.’”) (citing Williamson v. Citrix Online, LLC, 792 F.3d
`1339, 1348–49 (Fed. Cir. 2015)).
`No other claim terms require interpretation to decide the issues
`presented during trial. See Nidec Motor Corp. v. Zhongshan Broad Ocean
`Motor Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017) (“Because we need only
`construe terms ‘that are in controversy, and only to the extent necessary to
`resolve the controversy,’ we need not construe [a particular claim limitation]
`
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`where the construction is not ‘material to the . . . dispute.’” (citation
`omitted)).
`
`
`C. Legal Standards
`To prevail in its challenges to the patentability of claims 15–21 and
`26–30 of the ’406 patent, Petitioner must demonstrate by a preponderance of
`the evidence that the claims are unpatentable. 35 U.S.C. § 316(e). “In an
`[inter partes review], the petitioner has the burden from the onset to show
`with particularity why the patent it challenges is unpatentable.” Harmonic
`Inc. v. Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed. Cir. 2016). This burden
`of persuasion never shifts to Patent Owner. Dynamic Drinkware, LLC v.
`Nat’l Graphics, Inc., 800 F.3d 1375, 1378 (Fed. Cir. 2015); see also In re
`Magnum Oil Tools Int’l, Ltd., 829 F.3d 1364, 1376 (Fed. Cir. 2016)
`(“Where, as here, the only question presented is whether due consideration
`of the four Graham factors renders a claim or claims obvious, no burden
`shifts from the patent challenger to the patentee.”).
`A claim is unpatentable for obviousness if, to one of ordinary skill in
`the pertinent art, “the differences between the subject matter sought to be
`patented and the prior art are such that the subject matter as a whole would
`have been obvious at the time the invention was made.” KSR, 550 U.S. at
`406 (quoting 35 U.S.C. § 103(a) (2006)). The question of obviousness is
`resolved on the basis of underlying factual determinations, including “the
`scope and content of the prior art”; “differences between the prior art and the
`claims at issue”; and “the level of ordinary skill in the pertinent art.”
`Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966). Additionally,
`objective indicia of nonobviousness, such as “commercial success, long felt
`but unsolved needs, failure of others, etc., might be utilized to give light to
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`the circumstances surrounding the origin of the subject matter sought to be
`patented. As indicia of obviousness or nonobviousness, these inquiries may
`have relevancy.” Id. When conducting an obviousness analysis, we
`consider a prior art reference “not only for what it expressly teaches, but also
`for what it fairly suggests.” Bradium Techs. LLC v. Iancu, 923 F.3d 1032,
`1049 (Fed. Cir. 2019) (citation omitted).
`A patent claim “is not proved obvious merely by demonstrating that
`each of its elements was, independently, known in the prior art.” KSR,
`550 U.S. at 418. An obviousness determination requires finding “both ‘that
`a skilled artisan would have been motivated to combine the teachings of the
`prior art references to achieve the claimed invention, and that the skilled
`artisan would have had a reasonable expectation of success in doing so.’”
`Intelligent Bio-Sys., Inc. v. Illumina Cambridge Ltd., 821 F.3d 1359,
`1367–68 (Fed. Cir. 2016) (citation omitted); see KSR, 550 U.S. at 418
`(for an obviousness analysis, “it can be important to identify a reason that
`would have prompted a person of ordinary skill in the relevant field to
`combine the elements in the way the claimed new invention does”). Also,
`“[t]hough less common, in appropriate circumstances, a patent can be
`obvious in light of a single prior art reference if it would have been obvious
`to modify that reference to arrive at the patented invention.” Arendi S.A.R.L.
`v. Apple Inc., 832 F.3d 1355, 1361 (Fed. Cir. 2016).
`“Although the KSR test is flexible, the Board ‘must still be careful not
`to allow hindsight reconstruction of references . . . without any explanation
`as to how or why the references would be combined to produce the claimed
`invention.’” TriVascular, Inc. v. Samuels, 812 F.3d 1056, 1066 (Fed. Cir.
`2016) (citation omitted). Further, an assertion of obviousness “cannot be
`sustained by mere conclusory statements; instead, there must be some
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`articulated reasoning with some rational underpinning to support the legal
`conclusion of obviousness.” KSR, 550 U.S. at 418 (quoting In re Kahn,
`441 F.3d 977, 988 (Fed. Cir. 2006)); accord In re NuVasive, Inc., 842 F.3d
`1376, 1383 (Fed. Cir. 2016) (stating that “conclusory statements” amount to
`an “insufficient articulation[] of motivation to combine”; “instead, the
`finding must be supported by a ‘reasoned explanation’” (citation omitted));
`Magnum Oil, 829 F.3d at 1380 (“To satisfy its burden of proving
`obviousness, a petitioner cannot employ mere conclusory statements. The
`petitioner must instead articulate specific reasoning, based on evidence of
`record, to support the legal conclusion of obviousness.”).
`
`D. Obviousness Ground Based on Suda (Claims 15–21 and 26–30)
`1. Suda
`Suda discloses a “memory management device for managing a
`nonvolatile semiconductor memory.” Ex. 1003, code (57). Figure 1 of Suda
`is reproduced below.
`
`
`
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`Figure 1 depicts host device 2, which may be a digital camera, in
`communication with memory card 1 comprising host interface section 12,
`flash memory controlling section 11, and flash memory 14 (e.g., a NAND
`type nonvolatile memory). Id. at col. 2, ll. 58–66. “[F]lash memory
`controlling section 11 manages data erasure and a table indicating a
`relationship between logical blocks and physical blocks of the flash memory
`14.” Id. at col. 3, ll. 13–15. Logical and physical address table 13a, stored
`in random access memory (RAM) 13, “manages logical addresses and
`physical addresses allocated to physical blocks in which data items are
`written, of the physical blocks in the flash memory 14, in association with
`each other.” Id. at col. 3, ll. 41–47.
`According to Suda, when a subset of pages of a physical block are
`erased, “the time required for data erasure is long” because the non-erased
`pages must be read and “written to another physical block.” Id. at col. 4,
`ll. 60–67; see also id. at col. 1, ll. 19–23. Suda discloses an improved
`process that instead writes “erasure area pointer[s]” to erasure area pointer
`storage area 13b in RAM 13 indicating that pages in a particular address
`range are in a “virtual erased state.” Id. at col. 5, ll. 14–23. “The virtual
`erased state is a state in which the flash memory controlling section 11 does
`not actually erase data items to be erased, i.e., they are subjected to virtual
`erasure, in response to an access command from the host device 2.” Id. at
`col. 5, ll. 23–27. Specifically, when host device 2 issues a data read
`command with a logical block address, flash memory controlling section 11
`obtains the corresponding physical block address from logical and physical
`address table 13a, then looks to erasure area pointer storage area 13b to
`determine whether the requested data is within “an area indicated by the
`
`16
`
`

`

`IPR2021-00343
`Patent 8,533,406 B2
`erasure area pointer or pointers”; if so, flash memory controlling section 11
`outputs “initial-value” (i.e., empty) data. Id. at col. 9, ll. 52–62.
`Figure 8 of Suda is reproduced below.
`
`
`Figure 8 is a flowchart depicting the disclosed erase process. Id. at col. 2,
`ll. 38–40. Host device 2 issues an erase command to erase particular pages
`of data stored in a physical block (step S1). Id. at col. 7, ll. 11–19. Flash
`memory controlling section 11 refers to logical and physical address table
`13a and “detects the physical address of a physical block related to a logical
`block given an address design[at]ed in the erasure command” (step S2), then
`“determines whether an address range corresponding to an area in which the
`data items to be erased in response to the erase command are stored is
`already stored in the erasure area pointer storage area 13b” (step S3). Id. at
`col. 7, ll. 30–42. If not, it stores erasure area pointers (i.e., a “start pointer”
`
`17
`
`

`

`IPR2021-00343
`Patent 8,533,406 B2
`for the first page address and “end pointer” for the last page address) in
`erasure area pointer storage area 13b (step S4). Id. at col. 5, ll. 36–46, col. 7,
`ll. 43–55, Figs. 3–5. Flash memory controlling section 11 then “determines
`whether or not the address range indicated by the erasure area pointer[s] . . .
`is coincident with the size of a physical block to be subjected to data
`erasure” (step S5). Id. at col. 7, ll. 56–63. If it is coincident (i.e., the entire
`physical block is already in a “virtual erased state”), the block may be put
`into an “unused state” by, for example, erasing the associated address
`information in logical and physical address table 13a (step S6). Id. at col. 7,
`l. 64–col. 8, l. 2. If it is not coincident, flash memory controlling section 11
`writes the data items written to erasure area pointer storage area 13b to flash
`memory 14 so that “even if a power supply to the memory card 1 is turned
`off, the information of the erasure area pointer is maintained, and thus a
`virtual erased state is also maintained” (step S7). Id. at col. 8, ll. 3–12.
`
`
`2. Claim 15
`Petitioner argues that claim 15 is unpatentable over Suda5 under
`35 U.S.C. § 103(a), relying on the testimony of Dr. Baker as support.
`Pet. 36–41 (citing Ex. 1004). Patent Owner makes various arguments in
`response, relying on the testimony of Dr. Madisetti. PO Resp. 23–38 (citing
`Ex. 2010); Sur-Reply 8–16.
`
`
`
`5 The three prior art references at issue in this proceeding (Suda, SwSTE’05,
`and Bennett) were not of record during prosecution of the ’406 patent. See
`Ex. 1001, code (56); Pet. 9.
`
`18
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`

`IPR2021-00343
`Patent 8,533,406 B2
`
`a) Petitioner’s Arguments
`Petitioner argues that Suda teaches or renders obvious all of the
`limitations of claim 15. Pet. 36–41. Petitioner asserts that Suda teaches an
`“apparatus” (i.e., the memory device shown in Figure 1) comprising a
`“non-volatile storage medium” (i.e., flash memory 14), “request receiver
`module” (i.e., host interface section 12 or flash memory controlling section
`11 performing various functions in the disclosed erase process), and
`“marking module” (i.e., flash memory controlling section 11 performing
`various functions in the disclosed erase process). Id. Specifically, with
`respect to the recited “request receiver module,” Petitioner argues that a
`person of ordinary skill in the art “would have recognized Suda’s flash
`memory controlling section or host interface sections, both of which
`receive[] commands originating from a host device, as the ‘request receiver
`module.’” Id. at 37–38.
`Claim 15 recites that the request receiver module is configured to
`“receive an indication that a data structure, corresponding to data stored on
`the non-volatile storage medium, has been deleted.” Petitioner relies on
`Suda’s host interface section 12 and flash memory controlling section 11
`receiving an erase command from a digital camera (i.e., host device 2)
`connected to the memory device. Id. at 37–39. According to Petitioner,
`a person of ordinary skill in the art would have understood that the erase
`command from the digital camera “indicates that a digital photo (the recited
`‘data structure’) has been selected for deletion by a user.” Id. at 38. The
`digital photo “would have a data structure in the form of a .jpg, .gif, .raw, or
`any file system data structure” and “be stored as data on the flash memory of
`the memory device. Thus, a [person of ordinary skill in the art] would have
`understood Suda’s erase command to be [an] indication that a picture file,
`
`19
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`

`IPR2021-00343
`Patent 8,533,406 B2
`corresponding to digital photo data stored on the flash memory, has been
`deleted by a user.” Id. (citation omitted); see Ex. 1003, col. 7, ll. 11–19,
`34–38 (describing an example of an “erase command to erase 16384-bytes
`data items (32 pages) of the data items which are managed when they are
`stored in a physical block given physical block address ‘3

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