throbber
Trials@uspto.gov
`571-272-7822
`
`
`
`
`
`
`Paper 41
`Date: July 15, 2022
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC., MICRON SEMICONDUCTOR
`PRODUCTS, INC., MICRON TECHNOLOGY TEXAS LLC,
`DELL TECHNOLOGIES INC., DELL INC., and HP INC.,
`Petitioner,
`
`v.
`
`UNIFICATION TECHNOLOGIES LLC,
`Patent Owner.
`
`IPR2021-00345
`Patent 9,632,727 B2
`
`
`
`
`
`
`
`
`
`Before JUSTIN T. ARBES, TERRENCE W. McMILLIN, and
`CHRISTOPHER L. OGDEN, Administrative Patent Judges.1
`
`OGDEN, Administrative Patent Judge.
`
`JUDGMENT
`Final Written Decision
`Determining All Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`
`
`1 Katherine K. Vidal, Under Secretary of Commerce for Intellectual Property
`and Director of the United States Patent and Trademark Office, is recused
`from this proceeding and took no part in this decision. See Director’s
`Memorandum, Procedures for Recusal to Avoid Conflicts of Interest and
`Delegations of Authority (Apr. 20, 2022), https://go.usa.gov/xJjch; Interim
`Process for Director Review § 20, https://go.usa.gov/xJjce.
`
`

`

`IPR2021-00345
`Patent 9,632,727 B2
`
`
` INTRODUCTION
`
`In response to a Petition (Paper 4, “Pet.”) filed by Petitioners Micron
`Technology, Inc., Micron Semiconductor Products, Inc., Micron Technology
`Texas LLC, Dell Technologies Inc., Dell Inc., and HP Inc. (collectively,
`“Petitioner”), the Board instituted an inter partes review of claims 1–6 and
`12–16 of U.S. Patent No. 9,632,727 B2 (Ex. 1001, “the ’727 patent”). (Paper
`9, “Dec.”). Patent Owner Unification Technologies LLC (“UTL”) filed a
`Patent Owner Response (Paper 21, “PO Resp.”), Petitioner filed a Reply to
`the Patent Owner Response (Paper 28, “Pet. Reply”), and UTL filed a Sur-
`reply (Paper 33, “PO Sur-reply”).
`We held an oral hearing on April 13, 2022, and the transcript is
`entered on the record. Paper 36 (“Tr.”).
`This is a final written decision under 35 U.S.C. § 318(a) as to whether
`the claims challenged in the inter partes review are unpatentable. For the
`reasons below, we conclude that Petitioner has shown that all the challenged
`claims are unpatentable on at least one ground of the Petition.
`
` BACKGROUND
`
`A. RELATED PROCEEDINGS
`
`The parties identify the following as related matters: Unification
`Technologies LLC v. Dell Technologies, Inc., No. 6:20-cv-499-ADA
`(W.D. Tex. filed June 5, 2020), Unification Technologies LLC v. Micron
`Technology, Inc., No. 6:20-cv-500-ADA (W.D. Tex. filed June 5, 2020) (“the
`district court case”), and Unification Technologies LLC v. HP Inc., No. 6:20-
`cv-501-ADA (W.D. Tex. filed June 5, 2020). Pet. 67; Paper 6, 2–3.
`
`2
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`IPR2021-00345
`Patent 9,632,727 B2
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`
`Petitioner also filed petitions challenging claims of patents related to
`the ’727 patent in IPR2021-00343 and IPR2021-00344, for which the Board
`issued final written decisions on July 8, 2022.
`
`B.
`
`THE ’727 PATENT (EX. 1001)
`
`The ’727 patent discloses a technique “for managing a non-volatile
`storage medium.” Ex. 1001, code (57). According to the patent, at the time
`of the claimed invention there were at least two known strategies for a file
`system to delete data in non-volatile storage media when that data is no
`longer useful. First, it could issue an erase command that “deletes a directory
`entry in the file system while leaving the data in place in the storage device
`containing the data.” Id. at 1:32–35. “Typically, a data storage device is not
`involved in this type of erase operation.” Id. at 1:35–36. Thus, according to
`UTL, this approach has the drawback of “the data storage device being
`unaware [when] data has become invalid.” PO Resp. 2 (citing Ex. 1001,
`1:35–36).
`In the second strategy, the file system could “write zeros, ones, or
`some other null data character to the data storage device to actually replace
`the erased file.” Ex. 1001, 1:37–39. But according to the ’727 patent, “this is
`inefficient because valuable bandwidth is used while transmitting” the
`highly-redundant overwriting data. Id. at 1:39–41, 1:51–60. Also, the ’727
`patent states that the approach is ineffective when used in solid-state storage
`devices, because such devices typically do not have the ability to overwrite
`previously stored data to erase it. Id. at 1:43–50. For example, flash memory
`is a solid-state storage device that stores data in “blocks,” each block
`containing smaller “pages” of data. Id. at 6:66–7:1, 17:30–33. Such devices
`
`
`
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`3
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`IPR2021-00345
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`cannot write a page of new data over a page of old data without first erasing
`the entire block containing the old data. See Pet. 3 (citing Ex. 1004 ¶ 73); PO
`Resp. 13 (citing Ex. 1003, 4:37–38).
`The ’727 patent attempts to overcome these drawbacks. See Ex. 1001,
`1:64–2:6. In the claimed invention, data are represented by two types of
`addresses: physical addresses that indicate the physical location of the data
`on the storage medium, and logical addresses that identify data logically
`while internally mapping the data to associated physical addresses. See id. at
`2:32–34. When a computer system deletes data corresponding to a particular
`logical address, it sends a message to a storage controller for the medium.
`Id., code (57). This “message may comprise a hint, directive, or other
`indication that the data [associated with the logical address] has been erased
`and/or deleted.” Id. In response to this message, “the storage controller
`records an indication that the contents of a . . . physical address associated
`with the logical [address] do not need to be preserved on the non-volatile
`storage medium.” Id.
`Figure 1A of the ’727 patent, which we reproduce below, is a
`schematic block diagram of the claimed invention. Ex. 1001, 4:35–38, 6:56–
`59.
`
`
`
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`4
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`IPR2021-00345
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`
`
`As shown above, overall system 100 includes clients 114, which
`communicate over computer network 116 with computer 112 having solid-
`state storage device 102. Ex. 1001, 6:56–63, 7:5:7. Solid-state storage device
`102 includes one or more solid-state storage devices 110 (e.g., flash
`
`
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`IPR2021-00345
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`memory) and one or more solid-state storage controllers 104,2 which write to
`storage devices 110 through write data pipeline 106 and read from storage
`devices 110 through read data pipeline 108. Id. at 6:59–7:4, 7:34–37.
`Storage controller 104 includes an “object index module.” Ex. 1001,
`10:50–51, Fig. 2A (item 266). When a “data packet is stored and the
`physical address of the data packet is assigned” to a data object, this object
`index module creates an entry in an index that maps the object’s “logical
`identifier” to “one or more physical addresses corresponding to where the
`storage controller [104 has] stored . . . data packets and any object metadata
`packets.” Id. at 12:1–9. When storage controller 104 receives “a command
`that erases a data block or other object elements,” storage controller 104
`stores an “erase packet that includes . . . a reference to the object, [a]
`relationship to the object, . . . the size of the data block erased,” and
`optionally an “indicat[ion] that the erased object elements are filled with
`zeros.” Id. at 12:25–32. “Thus, the erase [command] can be used to emulate
`actual memory or storage that is erased and actually has a portion of the
`appropriate memory/storage actually stored with zeros in the cells of the
`memory/storage.” Id. at 12:33–36.
`Write data pipeline 106 includes a garbage collection system with a
`garbage collector bypass that “receives data segments from the read data
`pipeline 108.” Ex. 1001, 27:45–48, Fig. 3. This garbage collection system
`“marks packets that are no longer valid, typically because the packet is
`marked for deletion or has been modified and the modified data is stored in a
`
`
`2 The ’727 patent also refers to a particular storage controller as “storage
`controller 152.” See, e.g., Ex. 1001, 8:29. For clarity and consistency, we use
`Figure 1A’s identification of a storage controller as item 104.
`
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`IPR2021-00345
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`different location.” Id. at 27:49–52. When a particular section of storage
`needs to be recovered, such as when the section contains a large number of
`invalid packets, the garbage collection bypass can relocate any still-valid
`data in that section. Id. at 27:62–63. This relocation proceeds by “allow[ing]
`packets to be read into the read data pipeline 108 and then transferred
`directly to the write data pipeline 106 without being routed out of the solid-
`state storage controller 104.” Id. at 27:63–67.
`
`C.
`
`CHALLENGED CLAIMS AND GROUNDS
`
`Independent claim 1, which exemplifies the other challenged claims
`of the ’727 patent, is as follows:
`1[a]
`1. An apparatus, comprising:
`1[b]
`a solid-state storage medium;
`1[c]
`a solid-state storage controller configured to implement
`storage operations on the solid state storage medium in
`response to requests from a computer system, including
`storing data pertaining to logical addresses of a logical
`address space at respective physical addresses of the
`solid-state storage medium; and
`an indexer, comprised within the solid-state storage
`controller, wherein the indexer is configured to assign
`logical addresses of the logical address space to physical
`addresses in use to store data pertaining to the logical
`addresses on the solid-state storage medium;
`1[e] wherein the indexer is further configured to remove an
`assignment between an identified logical address and a
`physical address of the solid-state storage medium in
`response to a message received from a host operating
`system, the message indicating that the identified logical
`address is erased.
`
`1[d]
`
`
`
`
`7
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`

`IPR2021-00345
`Patent 9,632,727 B2
`
`Ex. 1001, 53:22–40 (formatting and reference letters added); Pet. 70–71
`(claim listing). Dependent claims 2–6, which Petitioner also challenges,
`depend directly from claim 1. See id. at 53:41–54:3.
`Petitioner also challenges independent claim 12, which is as follows:
`12[a]
`12. A non-volatile solid-state storage system, comprising:
`12[b] a storage interface configured to communicate with a storage
`client;
`12[c] a storage processor coupled to the storage interface;
`12[d] a flash memory device coupled to the storage processor; and
`12[e] a logical-to-physical translation layer maintained by the
`storage processor, wherein the logical-to-physical
`translation layer maps logical block addresses to
`corresponding respective physical block addresses of the
`flash memory device, wherein the storage processor is
`configured to:
`receive, from the storage client through the storage
`interface, an empty-block directive command and a
`range of logical block addresses,
`update the logical-to-physical translation layer to indicate
`that data stored in physical block addresses
`corresponding to the received logical block addresses
`do not need to be preserved, and
`store persistent data on the flash memory device, the
`persistent data indicating that the data corresponding
`to the received logical block addresses is deleted at the
`storage client.
`
`12[f]
`
`12[g]
`
`12[h]
`
`Ex. 1001, 54:42–64 (formatting and reference letters added); Pet. 73–75
`(claim listing). Dependent claims 13–16, which Petitioner also challenges,
`depend directly or indirectly from claim 12. See id. at 54:65–55:11.
`Petitioner argues three grounds for inter partes review, as summarized
`in the following table:
`
`
`
`
`8
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`IPR2021-00345
`Patent 9,632,727 B2
`
`
`Reference(s)/Basis
`35 U.S.C. §
`Ground Claims Challenged
`Bennett4
`103(a)3
`1
`1–6, 12–16
`Suda5
`103(a)
`2
`1–3, 5, 6, 12–16
`Suda, Bennett
`103(a)
`3
`4, 13
`Pet. 9–10. For each of the grounds, Petitioner also relies on the general
`knowledge of a person of ordinary skill in the art. Pet. 9–10 (citing
`Koninklijke Philips N.V. v. Google LLC, 948 F.3d 1330, 1337–38 (Fed. Cir.
`2020)).
`
`D. DECLARATORY TESTIMONY
`
`Petitioner submits a declaration from Jacob Baker, Ph.D., P.E. as
`expert testimony. Ex. 1004 ¶ 1; see also Ex. 1026 (curriculum vitae). Exhibit
`2012 is the transcript for his deposition, dated September 16, 2021.
`UTL submits a declaration from Vijay K. Madisetti, Ph.D. Ex. 2010;
`see also Ex. 2011 (curriculum vitae). Exhibit 1038 is the transcript for his
`deposition, dated January 7, 2022.
`
`
`3 35 U.S.C. § 103(a) (2006), amended by Leahy–Smith America Invents Act,
`Pub. L. No. 112-29 § 103, sec. (n)(1), 125 Stat. 284, 287, 293 (2011)
`(effective Mar. 16, 2013). The ’727 patent claims priority to a provisional
`application filed on December 6, 2006, which is before the effective date of
`this amendment to § 103. See Ex. 1001, code (60); Pet. 4 (“Solely for
`purposes of this IPR, Petitioners assume, but do not concede, an effective
`filing date of December 6, 2006, for the ’727 patent.”).
`4 Bennett et al., US 7,624,239 B2, filed Nov. 14, 2005, issued Nov. 24, 2009
`(Ex. 1002). Petitioner alleges that Bennett is prior art under 35 U.S.C.
`§ 102(e). Pet. 10. UTL does not contest this in its Response.
`5 Suda et al., US 7,057,942 B2, published Mar. 16, 2006, issued June 6, 2006
`(Ex. 1003). Petitioner alleges that Suda is prior art under 35 U.S.C. § 102(a).
`Pet. 10. UTL does not contest this in its Response.
`
`9
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`IPR2021-00345
`Patent 9,632,727 B2
`
`
` GROUNDS OF THE PETITION
`
`For the reasons below, we determine that Petitioner has shown, by a
`preponderance of the evidence, that claims 1–6 and 12–16 of the ’727 patent
`are unpatentable under the grounds based on Suda (for claims 1–3, 5, 6, 12,
`and 14–16) or the combination of Suda and Bennett (for claims 4 and 13).
`We do not reach Petitioner’s ground relying on Bennett alone, and we do not
`reach Petitioner’s alternative argument for claim 13 relying on Suda alone.
`Before analyzing these grounds in detail, we address two matters that will
`underlie our analysis: the level of ordinary skill in the art and the
`construction we will apply to the claim terms.
`
`A.
`
`LEVEL OF ORDINARY SKILL IN THE ART
`
`The level of ordinary skill in the pertinent art at the time of the
`invention is a factor in how we construe patent claims. See Phillips v. AWH
`Corp., 415 F.3d 1303, 1312–13 (Fed. Cir. 2005) (en banc). It is also one of
`the factors we consider when determining whether a patent claim is obvious
`over the prior art. See Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`To assess the level of ordinary skill, we construct a hypothetical
`“person of ordinary skill in the art,” from whose vantage point we assess
`obviousness and claim interpretation. See In re Rouffet, 149 F.3d 1350, 1357
`(Fed. Cir. 1998). This legal construct “presumes that all prior art references
`in the field of the invention are available to this hypothetical skilled artisan.”
`Id. (citing In re Carlson, 983 F.2d 1032, 1038 (Fed. Cir. 1993)).
`Petitioner argues that a person of ordinary skill would have had “a
`Bachelor of Science degree in computer science or electrical engineering
`and at least two years of experience in the design, development,
`
`
`
`
`10
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`IPR2021-00345
`Patent 9,632,727 B2
`
`implementation, or management of solid-state memory devices.” Pet. 4.
`Professor Baker also opines that a person of ordinary skill would have had
`certain background knowledge about flash memory management, including
`how flash memory erases data, how flash memory programs or
`writes data, how memory is used in a cache hierarchy, relative
`speeds of flash memory compared to other memory, how
`garbage collection is used with flash memory, how to use wear
`leveling to combat endurance limits of flash memory, how the
`[Flash Translation Layer (“FTL”)] works, and industry
`standards affecting flash memory including the [Advance
`Technology Attachment (“ATA”)] standard.
`Pet. 5 (citing Ex. 1004 ¶ 61); see also Ex. 1004 ¶¶ 57, 62–95 (describing
`flash memory technologies that, according to Professor Baker, were well
`understood and widely used before the priority date of the ’727 patent).
`For this proceeding, UTL does not contest Petitioner’s proposed
`articulation of the level of ordinary skill, and Dr. Madisetti applied this
`articulation in his analysis. See PO Resp. 16; Ex. 2010 ¶¶ 47–52. Because
`Petitioner’s uncontroverted articulation of the level of ordinary skill in the
`art is supported by testimonial evidence and appears consistent with the
`types of problems and solutions in the ’727 patent, we adopt it for this
`decision. See, e.g., Ex. 1001, 1:25–60 (“Background of the Invention”
`section of the ’727 patent, describing known write, read, and erase
`procedures for solid-state storage devices).
`
`B.
`
`CLAIM CONSTRUCTION
`
`In an inter partes review, we construe a patent claim “using the same
`claim construction standard that would be used to construe the claim in a
`civil action under 35 U.S.C. 282(b).” 37 C.F.R. § 42.100(b) (2021). This
`generally includes “construing the claim in accordance with the ordinary and
`
`11
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`
`customary meaning of such claim as understood by one of ordinary skill in
`the art and the prosecution history pertaining to the patent.” Id. The ordinary
`and customary meaning of a claim term “is its meaning to the ordinary
`artisan after reading the entire patent,” and “as of the effective filing date of
`the patent application.” Phillips, 415 F.3d at 1313, 1321. There are only two
`circumstances in which a construction departs from the ordinary and
`customary meaning: “1) when a patentee sets out a definition and acts as
`[their] own lexicographer, or 2) when the patentee disavows the full scope of
`a claim term either in the specification or during prosecution.” Thorner v.
`Sony Comput. Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012). Any
`such special meaning of a term “must be sufficiently clear in the
`specification that any departure from common usage would be so understood
`by a person of experience in the field of the invention.” Multiform
`Desiccants Inc. v. Medzam Ltd., 133 F.3d 1473, 1477 (Fed. Cir. 1998).
`To construe the claim terms, “we look principally to the intrinsic
`evidence of record, examining the claim language itself, the written
`description, and the prosecution history, if in evidence.” DePuy Spine, Inc. v.
`Medtronic Sofamor Danek, Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006).
`Petitioner provides a listing of the parties’ proposed claim
`constructions in the district court case, but argues that “[t]hese construction
`disputes do not affect the outcome of [the] Petition with respect to any
`claim.” Pet. 5–7. Although Petitioner asserted in district court that certain
`terms are indefinite, Petitioner states that it has applied UTL’s proposed
`constructions of those terms in its Petition. Id. at 7–8 (citing Spherix Inc. v.
`Matal, 703 F. App’x 982, 983 (Fed. Cir. 2017); Target Corp. v. Proxicom
`Wireless, LLC, IPR2020-00904, Paper 11 at 12 (PTAB Nov. 10, 2020);
`
`
`
`
`12
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`
`Samsung Elecs. Am., Inc. v. Prisua Eng’g Corp., 948 F.3d 1342, 1355 (Fed.
`Cir. 2020); Intel Corp. v. Alacritech, Inc., IPR2017-01391, Paper 8 at 7
`(PTAB Nov. 28, 2017); Vibrant Media v. Gen. Elec. Co., No. IPR2013-
`00172, Paper 50, 10 (PTAB July 28, 2014)).
`After Petitioner filed the Petition, the district court issued a Claim
`Construction Order interpreting five terms of the ’727 patent, as shown in
`the following table:
`Claim Term
`empty-block directive command
`(claims 12, 15)
`
`District Court’s Construction
`“A command that indicates that certain
`blocks contain data that does not need
`to be preserved”
`“Plain and ordinary meaning”
`
`the identified logical address is
`erased (claim 1)
`logical-to-physical translation
`layer (claim 12)
`indexer (claims 1–4)
`
`“Not indefinite; not subject to
`§ 112(f); plain and ordinary meaning”
`“Not indefinite; not subject to
`§ 112(f); plain and ordinary meaning”
`“Not indefinite; not subject to
`§ 112(f); plain and ordinary meaning”
`
`storage processor is configured to
`. . . update the logical-to-physical
`translation layer to indicate that
`data stored in physical block
`addresses corresponding to the
`received logical block addresses
`do not need to be preserved, and
`store persistent data on the flash
`memory device, the persistent
`data indicating that the data
`corresponding to the received
`logical block addresses is deleted
`at the storage client (claim 12)
`Ex. 2006, 2–3; accord PO Resp. 16–17.
`The parties accept the district court’s constructions, except that the
`parties have different views on the meaning of the identified logical address
`
`
`
`
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`is erased. See PO Resp. 17–18; Pet. Reply 10–11. In district court, Petitioner
`argued that this term has its “[p]lain and ordinary meaning,” which “is that
`the identified logical address is erased, not the data associated with the
`identified logical address is erased.” Pet. 6; Ex. 1032, 13; Ex. 1033, 2. UTL
`argued that the term means “the data identified by the logical address does
`not need to be preserved.” Pet. 6; Ex. 2007, 11–13. The district court
`interpreted the term to have its “[p]lain and ordinary meaning,” but
`otherwise, “the Court did not believe that the term needed to be construed.”
`Ex. 2014, 1 (clarifying email from the district court’s law clerk); see also
`Ex. 2006, 2.
`In our Decision instituting trial, we agreed with Petitioner and with
`the district court that the term has its ordinary and customary meaning
`because neither party had pointed to any evidence “that the ’727 patent
`clearly defines this term in the specification or that the applicant has
`otherwise clearly disclaimed any of the term’s ordinary and customary
`scope.” Dec. 14. Likewise, neither party presented such evidence at trial, and
`UTL did not argue that the term departs from its ordinary and customary
`meaning. See PO Resp. 17–20. Thus, given the evidence of record, we agree
`with the district court that the term the identified logical address is erased
`has its ordinary and customary meaning. However, it remains for us to
`determine the scope of that meaning sufficiently to resolve the parties’
`controversy.
`At trial, UTL argues that we should construe the identified logical
`address is erased to mean “data associated with the identified logical
`address is erased.” PO Resp. 17–18 (citing Ex. 2010 ¶¶ 53–56). According
`to UTL, “[t]his construction aligns with industry usage” and “aligns with the
`
`
`
`
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`specification, which recognizes that file systems can erase data associated
`with a logical address without involving the storage device.” Id. at 18 (citing
`Ex. 1001, 1:32–36; Ex. 2007, 2017–2034). UTL also argues that UTL’s
`proposed construction finds support in Petitioner’s own contentions, which
`UTL characterizes as arguing “that removing ‘information about which
`logical identifiers are associated with [which photos]’ satisfies the
`requirement that ‘the identified logical address is erased.’” Id. at 19 (quoting
`Pet. 45).
`But in its Reply, Petitioner disagrees that the term logical address
`includes associated data. Pet. Reply 10–11. According to Petitioner, “claim 1
`separately recites both ‘logical address’ and ‘data,’ for example, ‘storing data
`pertaining to logical addresses,’” so construing logical addresses to include
`associated data would render the claim unintelligible. Id. (quoting Ex. 1001,
`53:27). Petitioner also argues that the ’727 patent provides examples of
`deleting a logical identifier without deleting associated data. Id. at 11 (citing
`Ex. 1001, 2:25–30, 3:11–15).
`We agree with Petitioner that the plain language of claim 1
`distinguishes between a “logical address” and “data pertaining to” the
`logical address which is stored at a physical address on the solid-state
`storage medium. See Ex. 1001, 53:27–29, 53:33–34. We also agree with
`Petitioner that in the ’727 patent disclosure, “deleting an index entry that
`associates the logical identifier with the physical storage location” or
`“deleting a mapping between the logical identifier and the physical storage
`location” would correspond to erasing the “identified logical address” as
`recited in claim 1. See Ex. 1001, 2:25–28, 53:39–40. In these examples, the
`’727 patent does not disclose that the data associated with the logical address
`
`
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`is deleted, just that the link between the logical identifier and the physical
`data has been deleted.
`Thus, we disagree with UTL’s proposed construction of the identified
`logical address is erased to mean “data associated with the identified logical
`address is erased.” Other than this, we need not further construe the term, or
`explicitly construe any other terms, to resolve issues raised in the inter
`partes review. See Nidec Motor Corp. v. Zhongshan Broad Ocean Motor
`Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017) (“[W]e need only construe terms
`‘that are in controversy, and only to the extent necessary to resolve the
`controversy’ . . . .” (quoting Vivid Techs., Inc. v. Am. Sci & Eng’g, Inc., 200
`F.3d 795, 803 (Fed. Cir. 1999))).
`
`C. OBVIOUSNESS GROUNDS BASED ON SUDA (CLAIMS 1–3, 5, 6,
`AND 12–16)
`
`Turning to the grounds of the Petition, we begin with the second
`ground, which asserts that claims 1–3, 5, 6, and 12–16 are unpatentable
`under 35 U.S.C. § 103(a) as obvious over Suda. See Pet. 9–10, 39–60.
`A claim is unpatentable under § 103(a) for obviousness if the
`differences between the claimed subject matter and the prior art are “such
`that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). When a ground in a petition is based on a combination of references,
`we consider “whether there was an apparent reason to combine the known
`elements in the fashion claimed by the patent at issue.” Id. at 418 (citing In
`re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)).
`
`
`
`
`16
`
`

`

`IPR2021-00345
`Patent 9,632,727 B2
`
`
`We base our obviousness inquiry on factual considerations including
`(1) the scope and content of the prior art, (2) any differences between the
`claimed subject matter and the prior art, (3) the level of skill in the art, and
`(4) any objective indicia of obviousness or non-obviousness that may be in
`evidence. See Graham, 383 U.S. at 17–18.
`Considering these factors,6 we determine that Petitioner has shown, by
`a preponderance of the evidence, that claims 1–3, 5, 6, and 12–16 are
`unpatentable under § 103(a) as obvious over Suda. We begin our analysis
`with a brief overview of Suda, and then we address the parties’ contentions
`with respect to the challenged claims.
`
`1.
`
`Suda
`
`Suda discloses a “memory management device for managing a
`nonvolatile semiconductor memory.” Ex. 1003, code (57). Figure 1 of Suda,
`reproduced below, is a block diagram illustrating this device. Ex. 1003,
`2:58–60.
`
`
`6 Petitioner presents evidence of simultaneous invention as an objective
`indicium of obviousness. Pet. 62–63. UTL does not address this in its
`Response, and does not otherwise present evidence of objective indicia of
`non-obviousness. Because Petitioner has shown obviousness based on the
`other Graham factors, and any objective indicia of obviousness could only
`further support Petitioner’s arguments, we need not consider this evidence in
`our decision.
`
`
`
`17
`
`

`

`IPR2021-00345
`Patent 9,632,727 B2
`
`
`
`
`As shown above, Figure 1 depicts host device 2, which may be a digital
`camera, in communication with memory card 1 comprising host interface
`section 12, random access memory (RAM) 13, and flash memory 14 (e.g., a
`NAND type nonvolatile memory), each of which is connected to flash
`memory controlling section 11. Id. at 2:61–3:3.
`“[F]lash memory controlling section 11 manages data erasure and a
`table indicating a relationship between logical blocks and physical blocks of
`the flash memory 14.” Ex. 1003, 3:13–15. Logical and physical address table
`13a, stored in RAM 13, “manages logical addresses and physical addresses
`allocated to physical blocks in which data items are written, of the physical
`blocks in the flash memory 14, in association with each other.” Id. at 3:41–
`47.
`
`According to Suda, when memory controlling section 11 erases a
`subset of pages of a physical block, “the time required for data erasure is
`
`
`
`
`18
`
`

`

`IPR2021-00345
`Patent 9,632,727 B2
`
`long” because the non-erased pages must be read and “written to another
`physical block.” Ex. 1003, 4:60–67; see also id. at 1:19–23. Suda discloses
`an improved process that instead writes “erasure area pointer[s]” to erasure
`area pointer storage area 13b in RAM 13. Id. at 5:14–16. These pointers
`indicate that pages in a particular address range are in a “virtual erased state
`. . . in which the flash memory controlling section 11 does not actually erase
`data items to be erased, i.e., they are subjected to virtual erasure, in response
`to an access command from the host device 2.” Id. at 5:19–27.
`Specifically, when host device 2 issues a data read command with a
`logical block address, flash memory controlling section 11 obtains the
`corresponding physical block address from logical and physical address
`table 13a, then looks to erasure area pointer storage area 13b to determine
`whether the requested data is within “an area indicated by the erasure area
`pointer or pointers”; if so, flash memory controlling section 11 outputs
`“initial-value” (i.e., empty) data. Ex. 1003, 9:52–62. As a result, “it is not
`necessary to transfer data . . . and the time for erasing data can be greatly
`shortened.” Id. at 9:63–65.
`Figure 8 of Suda, reproduced below, is a flowchart depicting the
`process for erasing data on the memory device. Ex. 1003, 2:38–40.
`
`
`
`
`19
`
`

`

`IPR2021-00345
`Patent 9,632,727 B2
`
`
`
`As indicated above in step S1, host device 2 issues an erase command to
`erase particular pages of data stored in a physical block. Id. at 7:11–19. In
`step S2, flash memory controlling section 11 refers to logical and physical
`address table 13a and “detects the physical address of a physical block
`related to a logical block given an address design[at]ed in the erasure
`command.” Id. at 7:30–34.
`
`
`
`
`20
`
`

`

`IPR2021-00345
`Patent 9,632,727 B2
`
`
`In step S3, flash memory controlling section 11 “determines whether
`an address range corresponding to an area in which the data items to be
`erased in response to the erase command are stored is already stored in the
`erasure area pointer storage area 13b.” Ex. 1003, 7:38–42. If not, in step S4
`it stores erasure area pointers (i.e., a “start pointer” for the first page address
`and “end pointer” for the last page address) in erasure area pointer storage
`area 13b. Id. at 5:36–46, 7:43–55, Figs. 3–5.
`In step S5, flash memory controlling section 11 then “determines
`whether or not the address range indicated by the erasure area pointer[s] . . .
`is coincident with the size of a physical block to be subjected to data
`erasure.” Ex. 1003, 7:56–63. If it is coincident (i.e., the entire physical block
`is already in a “virtual erased state”), in step S6 the block may be put into an
`“unused state” by, for example, erasing the associated address information in
`logical and physical address table 13a. Id. 5:54–6:3, 6:34–41, 7:64–8:2, Figs.
`4, 6 (physical block B). If it is not coincident, in step S7 flash memory
`controlling section 11 writes the data items written to erasure area pointer
`storage area 13b to flash memory 14 so that “even if a power supply to the
`memory card 1 is turned off, the information of the erasure area pointer is
`maintained, and thus a virtual erased state is also maintained.” Id. at 8:3–12,
`Figs. 3, 5, 6 (physical blocks A and C).
`
`2.
`
`Independent Claim 1
`
`For independent claim 1, Petitioner maps the claim limitations to Suda
`as shown in Petitioner’s annotated version of Suda’s Figure 1, reproduced
`below:
`
`
`
`
`21
`
`

`

`IPR2021-00345
`Patent 9,632,727 B2
`
`
`
`
`Pet. 39. In the annotated figure above, red labels indicate the parts of Suda’s
`system that, according to Petitioner, correspond to various elements of claim
`1, including the recited “solid-state storage medium” (flash memory 14), the
`“solid-state storage controller” (flash memory cont

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