(12) United States Patent
`Stancil
`
`USOO6272584B1
`(10) Patent No.:
`US 6,272.584 B1
`(45) Date of Patent:
`Aug. 7, 2001
`
`(54) SYSTEM BOARD WITH CONSOLIDATED
`EEPROM MODULE
`
`(75) Inventor: Charles J. Stancil, Tomball, TX (US)
`(73) Assignee: Compaq Computer Corporation,
`Houston, TX (US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(*) Notice:
`
`(21) Appl. No.: 09/150,804
`(22) Filed:
`Sep. 10, 1998
`
`(51) Int. Cl." ...................................................... G06F 13/14
`
`(52) U.S. Cl. .............................. 710/241; 710/10; 710/36;
`711/150; 711/147; 714/784
`
`(58) Field of Search ................................ 710/241, 10,36;
`711/150, 147; 714/784
`References Cited
`U.S. PATENT DOCUMENTS
`
`(56)
`
`5,101,490 * 3/1992 Getson, Jr. et al..
`5,416,909 * 5/1995 Long et al. ............................ 710/36
`5,557,621 * 9/1996 Nakano et al. ...
`... 714/784
`5,692,111 * 11/1997 Marbry et al. ...
`... 395/114
`5,765,036 * 6/1998 Lim ...............
`... 711/147
`5,812,867
`9/1998 Basset ...................................... 712/1
`5,815,167
`9/1998 Muthal et al. ....................... 34.5/512
`5,872,998 * 2/1999 Chee .............
`... 395/876
`5,911,149 * 6/1999 Luan et al.....
`... 711/147
`6,014,729
`1/2000 Lannan et al. ....................... 711/150
`OTHER PUBLICATIONS
`Phillips Semiconductors; The 1°C-bus and how to use it;
`Apr. 1995; (pp. 1-24).
`Xicor(R); Serial E PROM; 1991; (pp. 1-16).
`Xicor(R); Serial EProm; 1994 (pp. 1-14).
`
`National Semiconductor Corporation; (Microwave"M Bus
`Interface) 256–/1024–/2048–/4096-Bit Serial EEPROM
`with Data Protect and Sequential Read; 1996 (pp. 1-14).
`* cited by examiner
`Primary Examiner Thomas Lee
`ASSistant Examiner Abdelmoniem Elamin
`(74) Attorney, Agent, or Firm-Conley, Rose & Tayon,
`P.C.; Michael F. Heim; Jonathan M. Harris
`(57)
`ABSTRACT
`A computer System is provided with a non-volatile memory
`module that is shared by a plurality of System components
`during System initialization. In one embodiment, the com
`puter System comprises a processor for executing program
`instructions, a memory device for Storing data and program
`instructions, a number of integrated System components for
`carrying out Specialized functions, a bridge logic device for
`communication between the processor, memory, and System
`components, and a shared non-volatile memory module for
`Storing configuration information for each of the System
`components. Each of the integrated System components is
`configured to retrieve its associated configuration informa
`tion from the Shared non-volatile memory module during
`initialization, rather than from a dedicated non-volatile
`memory as is conventionally done. This consolidation of
`multiple non-volatile memories into a single memory mod
`ule provides numerous advantages including reduction of
`cost and required Space on the motherboard. The non
`volatile memory module may include an arbiter for resolv
`ing memory access conflicts, and may further include a bus
`protocol translator for converting between interfaces imple
`mented by the System components and the interface of a
`chosen non-volatile memory array where the configuration
`information is actually Stored. In one contemplated
`embodiment, the non-volatile memory module may be
`incorporated into the non-volatile System memory where the
`BIOS is stored. In this embodiment, the non-volatile system
`memory might be coupled to a System bus through a System
`interface, and coupled to a number of Serial buSSes through
`a Second interface.
`28 Claims, 2 Drawing Sheets
`
`
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`TO
`COMPONENTS
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`

`

`U.S. Patent
`
`Aug. 7, 2001
`
`Sheet 1 of 2
`
`US 6,272.584 B1
`
`CPU
`
`102
`
`MEMORY HERE EEPROM
`
`MEMORY
`
`NORTH
`
`104
`
`106
`
`GRAPHICS
`CONTROLLER
`
`108
`
`SLOTS
`
`SOUTH
`
`AUDIO
`
`1394
`
`NC
`
`110
`
`112
`BUSB
`slots || HARD || FLASH || SUPER
`DISK
`ROM
`I/O
`120
`122
`124
`126
`
`128
`
`FOPY
`KEYBRD 30
`MOUSE 92 FIG.1
`
`(PRIOR ART)
`
`PARALLEL SERIAL
`
`
`
`404
`
`NON-VOLATILE
`MEMORY ARRAY
`
`BRIDGE JEEPROMEEPROMEEPROM
`
`114
`
`116
`
`118
`
`

`

`U.S. Patent
`
`Aug. 7, 2001
`
`Sheet 2 of 2
`
`US 6,272.584 B1
`
`CPU
`
`102
`
`EEPROM
`204
`
`MEMORY
`104
`
`NORTH
`BRIDGE
`106
`
`GRAPHICS
`CONTROLLER
`108
`
`EEPROML
`CNTRL
`202
`
`SLOTS
`
`110
`
`SOUTH
`BRIDGE
`112
`BUSB
`
`AUDIO
`
`114
`
`
`
`NC
`
`- Pl
`128
`
`KEYBRD 30
`SE 32
`MOUSE
`
`FIG. 2
`
`SLOTS
`
`120
`
`HARD
`DISK
`122
`
`SUPER
`I/O
`
`FLASH
`ROM
`126
`1241
`PARALLEL SERIAL
`
`
`
`TO
`COMPONENTS
`
`

`

`1
`SYSTEM BOARD WITH CONSOLIDATED
`EEPROM MODULE
`
`US 6,272.584 B1
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`2
`different buses. Such a Scheme permits components coupled
`to one bus to exchange data with components coupled to
`another bus.
`FIG. 1 illustrates an example of a configuration of various
`computer components that may be found in a representative
`prior art computer System. The computer System of FIG. 1
`includes a CPU 102 coupled to a bridge logic device 106 via
`a CPU bus. The bridge logic device 106 is sometimes
`referred to as a “North bridge” for no other reason than it
`often is depicted near the top of a computer System drawing.
`The North bridge 106 also couples to a main memory array
`104 by a memory bus, and may further couple to a graphics
`controller 108 via an accelerated graphics port (AGP) bus.
`The North bridge 106 couples CPU 102, memory 104, and
`graphics controller 108 to the other peripheral devices in the
`System through a primary expansion bus (BUSA) Such as a
`PCI bus or an EISA bus. Various components that under
`stand the bus protocol of BUSA may reside on this bus, such
`as an audio device 114, an external bus adapter (e.g. an IEEE
`1394 interface device) 116, and a network interface card
`(NIC) 118. These components may be integrated onto the
`motherboard, as Suggested by FIG. 1, or they may be
`plugged into expansion slots 110 that are connected to BUS
`A. AS technology evolves and higher-performance Systems
`are increasingly Sought, there is a greater tendency to
`integrate many of the devices into the motherboard which
`were previously Separate plug-in components.
`If other Secondary expansion buses are provided in the
`computer System, as is typically the case, another bridge
`logic device 112 is used to couple the primary expansion bus
`(BUS A) to the secondary expansion bus (BUS B). This
`bridge logic 112 is sometimes referred to as a “South bridge”
`reflecting its location vis-a-vis the North bridge 106 in a
`typical computer System drawing. An example of Such
`bridge logic is described in U.S. Pat. No. 5,634,073,
`assigned to Compaq Computer Corporation. Various com
`ponents that understand the bus protocol of BUS B may
`reside on this bus, Such as hard disk controller 122, Flash
`ROM 124, and Super I/O (input/output) controller 126. Slots
`120 may also be provided for plug-in components that
`comply with the protocol of BUS B.
`The Super I/O controller 126 typically interfaces to basic
`input/output devices such as a keyboard 130, a mouse 132,
`a floppy disk drive 128, a parallel port, a Serial port, and
`Sometimes various other input Switches Such as a power
`Switch and a suspend Switch. The Super I/O controller 126
`often has the capability to handle power management func
`tions Such as reducing or terminating power to components
`Such as the floppy drive 130, and blocking the clock signals
`that drive components such as the bridge devices 106, 112
`thereby inducing a sleep mode in the expansion buses. The
`Super I/O controller 126 may further assert System Man
`agement Interrupt (SMI) signals to various devices Such as
`the CPU 102 and North bridge 106 to indicate special
`conditions pertaining to input/output activities Such as Sleep
`mode. The Super I/O controller 126 may incorporate a
`counter or a Real Time Clock (RTC) to track the activities
`of certain components Such as the hard disk 122 and the
`primary expansion bus, inducing a Sleep mode or reduced
`power mode after a predetermined time of inactivity. The
`Super I/O controller 126 may also induce a low-power
`Suspend mode if the Suspend Switch is pressed, in which the
`power is completely shut off to all but a few selected
`devices. Exempted devices might be the Super I/O controller
`126 itself and NIC 118.
`Many of the peripheral components may include a pro
`grammable read-only memory (PROM) of some form for
`
`25
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates generally to a System and
`method for consolidating separate initialization EEPROMs
`from various integrated components on a circuit board into
`a single EEPROM module. More particularly, the present
`invention relates to an EEPROM module that may include
`an arbiter and protocol translator configured to allow a
`shared EEPROM to appear as a dedicated EEPROM to more
`than one component.
`2. Background of the Invention
`Early computer Systems included a processor (or CPU),
`random access memory (RAM), and certain peripheral
`devices Such as a floppy drive, a keyboard and a display.
`These components were typically coupled together using a
`network of address, data and control lines, commonly
`referred to as a “bus.” AS computer technology evolved, it
`became common to connect additional peripheral devices to
`the computer through ports (such as a parallel port or a serial
`port), or by attaching the peripheral devices to Sockets on the
`main system circuit board (or “motherboard”) which were
`connected to the System bus. One early bus that Still is in use
`today is the Industry Standard Architecture (ISA) bus. The
`ISAbuS, as the name implies, was a bus Standard adopted by
`computer manufacturers to permit the manufacturers of
`peripheral devices to design devices that would be compat
`ible with most computer systems. The ISA bus includes 16
`data lines and 24 address lines and operates at a clock Speed
`of 8 MHz. A large number of peripheral components have
`been developed over the years to operate with the ISA
`protocol.
`35
`The components which connect to a given bus receive
`data from the other components on the same bus via the bus
`Signal lines. Selected components may operate as “bus
`masters' to initiate data transferS over the bus. Each com
`ponent on the bus circuit operates according to a bus
`40
`protocol that defines the purpose of each buS Signal and
`regulates Such parameters as buS Speed and arbitration
`between components requesting bus mastership. AbuS pro
`tocol also determines the proper Sequence of bus signals for
`transferring data over the bus. AS computer Systems have
`continued to evolve, new bus circuits offering heightened
`functionality have replaced older bus circuits, allowing
`existing components to transfer data more effectively.
`One way in which the system bus has been made more
`effective is to permit data to be exchanged in a computer
`system without the assistance of the CPU. To implement this
`design, a new bus architecture called Extended Industrial
`Standard Architecture (EISA) was developed. The EISAbus
`protocol permits System components residing on the EISA
`bus to obtain mastership of the bus and to run cycles on the
`55
`bus independently of the CPU. Another bus that has become
`increasingly popular is the Peripheral Component Intercon
`nect (PCI) bus. Like the EISAbus, the PCI bus provides bus
`master capabilities to devices connected to the PCI bus. The
`PCI bus operates at clock speeds of 33 MHz or faster.
`Current designs contemplate implementing a 100 MHz PCI
`bus.
`To ensure that existing components continue to remain
`compatible with future generations of computer Systems,
`new computer designs often include many different types of
`buses. Because different buses operate according to different
`protocols, bridge devices are used to interface, or bridge, the
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`3
`initializing configuration registers and providing Serial num
`bers or unique identifiers of one form or another. This
`technique is popular because the use of PROMs to store
`device Settings advantageously reduces the number of com
`ponents and reduces design effort. Some bus protocols, Such
`as PCI, require that components be provided with configu
`ration information including a vendor id, a Serial number,
`perhaps a Subsystem Vendor id, revision numbers, and the
`like. Typically, PCI peripherals will retrieve this information
`from the PROMs at power-up and store it in internal
`configuration registers reserved for this purpose. Electrically
`erasable PROMs (EEPROMs) are often used with config
`urable peripheral components Since they allow a device's
`configuration information to be modified and retained
`indefinitely. Examples of components which would likely
`include an EEPROM are graphics accelerators, audio
`devices, NICs, modems, and external bus interfaces (e.g.
`IEEE 1394, SCSI).
`Most EEPROMs have a capacity of at least 128 bytes and
`support a serial interface such as the Inter IC bus (IC),
`Microwire TM bus or the Serial Peripheral Interface (SPI).
`Normally, less than /3to /2Of the full storage capacity of
`these EEPROMs is used, and in most cases these EEPROMs
`are only used during the devices initialization phase (i.e.
`during power-up). This results in numerous EEPROMs each
`having exceSS capacity when peripheral components are
`integrated onto the motherboard. It would be desirable to
`have a shared, central EEPROM module that appears as an
`individual dedicated EEPROM to each of several compo
`nents in the System, thus minimizing the number of com
`ponents required on the System board.
`SUMMARY OF THE INVENTION
`Accordingly, there is provided herein a computer System
`having a non-volatile memory module that is shared by a
`plurality of System components. In one embodiment, the
`computer System comprises a processor for executing pro
`gram instructions, a memory device for Storing data and
`program instructions, a number of integrated System com
`ponents for carrying out Specialized functions, a bridge logic
`40
`device for communication between the processor, memory,
`and System components, and a shared non-volatile memory
`module for Storing configuration information for each of the
`System components. Each of the integrated System compo
`nents is configured to retrieve its associated configuration
`information from the shared non-volatile memory module
`during initialization, rather than from a dedicated non
`Volatile memory as is conventionally done. This consolida
`tion of multiple non-volatile memories into a single memory
`module provides numerous advantages including reduction
`of cost and required Space on the motherboard. The non
`Volatile memory module may include an arbiter for resolv
`ing memory acceSS conflicts, and may further include a bus
`protocol translator for converting between interfaces imple
`mented by the System components and the interface of a
`chosen non-volatile memory array where the configuration
`information is actually Stored. In one contemplated
`embodiment, the non-volatile memory module may be
`incorporated into the non-volatile System memory where the
`BIOS is stored. In this embodiment, the non-volatile system
`memory might be coupled to a System bus through a System
`interface, and coupled to a number of Serial buSSes through
`a Second interface.
`One embodiment as claimed contemplates a System board
`for a computer that comprises a System bus, a number of
`system components, and a shared EEPROM module. The
`System bus is configured to couple a processor to the System
`
`4
`components, and each of the System components is config
`ured to access an EEPROM to retrieve configuration infor
`mation. The shared EEPROM module couples to each of the
`System components and Stores the configuration information
`for each of the of System components.
`Another embodiment as claimed contemplates a method
`for initializing a computer System that comprises: (i) storing
`configuration information for a number of System devices in
`a shared non-volatile memory module; (ii) asserting and
`releasing a reset Signal coupled to a processor and the System
`components; (iii) and Servicing the information requests to
`the shared non-volatile memory module. When the reset
`Signal is released in Step (ii), the System components initiate
`information requests to the shared non-volatile memory
`module for configuration information.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`A better understanding of the present invention can be
`obtained when the following detailed description of the
`preferred embodiment is considered in conjunction with the
`following drawings, in which:
`FIG. 1 is a block diagram of a prior art computer System
`that comprises various System components coupled together
`by buS logic,
`FIG. 2 is a block diagram of a computer System according
`to the present invention with a shared central EEPROM
`module,
`FIG. 3 is a block diagram of a first embodiment of a
`shared central EEPROM module; and
`FIG. 4 is a block diagram of second embodiment of a
`shared central EEPROM module.
`While the invention is susceptible to various modifica
`tions and alternative forms, specific embodiments thereof
`are shown by way of example in the drawings and will
`herein be described in detail. It should be understood,
`however, that the drawings and detailed description thereto
`are not intended to limit the invention to the particular form
`disclosed, but on the contrary, the intention is to cover all
`modifications, equivalents and alternatives falling within the
`Spirit and Scope of the present invention as defined by the
`appended claims.
`In addition, certain terms are used throughout the follow
`ing description and claims to refer to particular System
`components. This document does not intend to distinguish
`between components that differ in name but not function. In
`the following discussion and in the claims, the terms
`“including” and “comprising are used in an open-ended
`fashion, and thus should be interpreted to mean “including,
`but not limited to . . .
`. Also, the term “couple” or “couples”
`is intended to mean either an indirect or direct electrical
`connection. Thus, if a first device couples to a Second device,
`that connection may be through a direct electrical connec
`tion or through an indirect electrical connection via other
`devices and connections.
`
`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENTS
`Referring now to FIG. 2, an exemplary computer System
`constructed in accordance with a preferred embodiment
`generally includes an EEPROM controller 202 and a central,
`shared EEPROM 204, in addition to the various other
`Standard computer System components, Such as CPU 102,
`main memory 104, north bridge 106, graphics controller
`108, primary expansion bus slots 110, South bridge 112,
`audio device 114, external bus adapter 116, NIC 118, sec
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`S
`ondary bus slots 120, hard disk controller 122, flash ROM
`124, Super I/O module 126, floppy disk 128, keyboard 130,
`and mouse 132. As one of skill in the art will understand,
`many alternate configurations of Some or all of the Standard
`System components shown may be employed without vio
`lating the Spirit of the present invention. Graphics controller
`108, audio device 114, external bus adapter 116, and NIC
`118 are illustrative of peripheral components that may be
`provided as part of a Standard computer System mother
`board. AS technology evolves and manufacturers become
`more Sophisticated, the number of peripheral components
`integrated into the motherboard will probably increase, and
`it will become common to integrate various other System
`components. In the prior art, exemplary components 108
`(graphics controller), 114 (audio controller), 116 (external
`bus adapter), 118 (network interface) would conventionally
`include a dedicated EEPROM for storing configuration
`information for retrieval during System initialization. In the
`present invention shown in FIG. 2, these devices preferably
`do not include a dedicated EEPROM. In accordance with a
`preferred embodiment an EEPROM controller 202 couples
`to a graphics controller 108, audio controller 114, external
`bus adapter 116, and NIC 118. The EEPROM controller 202
`also preferably couples to an integrated EEPROM 204.
`Together controller 202 and EEPROM 204 form a central,
`shared EEPROM module. All the information which nor
`mally would be stored Separately in the various dedicated
`EEPROMs is stored in EEPROM 204, and EEPROM con
`troller 202 operates to service all EEPROM access requests
`from the various System components. In this manner the
`number of EEPROM chips on a system motherboard can be
`reduced, thereby reducing costs and the amount of Space
`required on the motherboard. A time Savings may also be
`realized since it is necessary to program only a single
`EEPROM, and the motherboard assembly time may be
`reduced Since fewer components need to be placed. Again
`in reliability may also be realized by the presence of fewer
`components.
`AS the various components may each expect a dedicated
`EEPROM, the EEPROM controller 202 may have to emu
`late a different EEPROM interface for each component. For
`example, the graphics controller 108 may use a Microwire TM
`bus for communicating with the EEPROM controller 202,
`while the NIC 118 could be using an SPI (Serial Peripheral
`Interface) bus and the external bus adapter 116 could be
`using an IC bus. Since the EEPROM 204 preferably uses
`only one bus standard, one embodiment of the EEPROM
`45
`controller 202 provides translation between bus protocols.
`One of skill in the art will understand that as the computer
`System exits the reset mode, the various System components
`will undergo an initialization process. During the initializa
`tion process the components coupled to the EEPROM
`50
`controller 202 will, in no particular order and generally in
`parallel, begin making EEPROM information requests to
`controller 202.
`In one embodiment, EEPROM controller 202 and
`EEPROM 204 operate at a sufficiently high speed to service
`all information requests concurrently, without having to
`resort to an arbitration process that forces one or more
`components to wait while another is being Serviced. For
`example, if at most four information requests may be
`simultaneously received by the EEPROM controller 202 on
`12 kHz busses, the EEPROM controller 202 may use a 1
`MHz bus to retrieve the first reply byte for each request from
`EEPROM 204 and place the reply information in outgoing
`buffers within one clock cycle of the slower busses. For this
`embodiment, a high-speed (1 MHz) extension of the SPI bus
`65
`may be used for coupling the controller 202 to the EEPROM
`204.
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`In another embodiment, at most one System component is
`wait-state intolerant (for example, a component which
`couples to the controller 202 via a Microwire TM bus), and the
`controller 202 employs an arbitration scheme to determine
`the order in which information requests get Serviced.
`Understandably, the wait-state intolerant device would be
`given the highest priority, while the other devices that
`tolerate wait-states take turns receiving EEPROM access.
`Illustratively, when an information request from a wait-State
`intolerant component and three information requests from
`other components are simultaneously received by EEPROM
`controller 202, the EEPROM controller 202 places the other
`components in a wait State until the information request
`from the wait-State intolerant component has been Serviced.
`The three pending information requests may then be Ser
`Viced on a round-robin basis.
`In a hybrid embodiment, the EEPROM module operates
`fast enough to Support multiple wait-State intolerant
`components, but must Still employ wait-States on those
`devices which will tolerate them in order to service all
`information requests. For example, if at most two informa
`tion requests from wait-State intolerant components and two
`more information requests are received from other
`components, the controller 202 may place the wait-State
`tolerant components into wait States, and retrieve the first
`reply bytes and place them in the outgoing buffers for the
`wait-State intolerant components within one clock cycle of
`the slower busses. Advantageously, the bus speed between
`the controller 202 and EEPROM 204 does not have to
`operate at as high a speed as the first described embodiment,
`and multiple wait-State intolerant components can be Ser
`Viced.
`Components which couple to the controller 202 by SPI or
`I°C busses may be tolerant of wait states. The SPI bus and
`I°C bus standards provide a means by which the EEPROM
`controller 202 may force components coupled to the con
`troller by these busses to enter a wait-state. This preferably
`allows the controller 202 to arbitrate between concurrent
`information requests from different components. The I°C
`buS Standard, in particular, is now described.
`The IC bus standard employs a signal data line (SDA)
`and a signal clock line (SCL). Both these lines are driven in
`open-collector fashion with pull-up resistors for raising the
`Signal logic level high when none of the devices is actively
`pulling the line down to a low Signal logic level. A device
`which initiates a data transfer on the bus becomes a bus
`master, and begins by driving the SDA line low followed by
`the SCL line. If everything proceeds normally, all Subse
`quent transitions on the SDA line take place during the
`upswing of the SCL line. Any other device coupled to the
`bus can “stall” the transfer of data by holding the SCL line
`low, i.e. not allowing an upSwing to occur. In this manner,
`an EEPROM access request by system components that
`employ the I°C bus can be put “on hold” by controller 202
`if the controller 202 is providing access to a different
`component. More details on the I°C bus and the other bus
`Standards can be found be referring to the published speci
`fications and much of the EEPROM product literature. The
`I°C bus specifically is discussed in “The IC-bus and how to
`use it (including specifications) publication by Philips
`Semiconductors (April 1995), which is hereby incorporated
`by reference.
`EEPROM 204 may be pre-programmed with configura
`tion information for the various System components before
`the EEPROM is installed on the board, or after installation
`during in-circuit test (ICT) of the motherboard. The
`EEPROM 204 stores the configuration information for all
`
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`the system components coupled to the controller 202. Each
`component is allotted storage space in the EEPROM 204,
`and the controller 202 is provided with a corresponding
`address map. The mapping Scheme for the various compo
`nent allotments may use fixed block sizes for simplicity or
`variable length blocks for better efficiency (in terms of
`Smaller required EEPROM capacity). In addition to the
`configuration information for the System components, the
`EEPROM may include information about the serial interface
`type being used by each of the System components and their
`tolerance of wait-States.
`In addition to the data that would normally be stored in the
`dedicated EEPROMs, the EEPROM 204 may also include
`configuration information for EEPROM controller 202. For
`example, the address or identification that the EEPROM
`controller 202 is expected to respond to for each bus may be
`stored in EEPROM 204. In one embodiment, controller 202
`is a general purpose microcontroller that may store Software
`in EEPROM 204.
`FIG. 3 shows a functional block diagram of one embodi
`ment of EEPROM controller 202. The controller 202 is
`shown comprising the functional blocks of configuration
`logic 302, arbiter 304, protocol translator 306, and option
`ally buffer 308. It should be understood that controller 202
`may be implemented using a general purpose microcontrol
`ler that executes Special purpose Software, and may alter
`natively be implemented using an application-specific inte
`grated chip (ASIC). Also, although the EEPROM 204 is
`shown as an external device, it is contemplated that the
`EEPROM 204 and the controller 202 may be integrated onto
`the same chip.
`In the embodiment of FIG.3, each bus to which the arbiter
`304 is coupled is provided with a set of configuration pins.
`By tying the configuration pins to high or low logic levels,
`the Systems engineer may “program” the controller with the
`characteristics of each of the incoming busses. These char
`acteristics may include the bus type (e.g. SPI, I°C,
`Microwire", etc.) and wait-State tolerance (e.g. wait-State
`allowed, no wait-state allowed). The configuration logic 302
`processes the pin States and alters the function of the arbiter
`304 as appropriate. The configuration pins may be elimi
`nated if the corresponding configuration information is
`stored in EEPROM 204. In any case, it may be desired to
`provide a set of configuration pins for Specifying the bus
`interface employed by EEPROM 204, particularly if
`EEPROM 204 is a separate chip.
`The arbiter 304 preferably monitors the bus transactions
`initiated by the integrated components and handles all
`information requests as they occur. The handling preferably
`includes (1) receiving an information request, (2) determin
`50
`ing if the request is material (i.e. directed to an EEPROM
`location within the central EEPROM module), (3) determin
`ing the priority of material requests, (4) placing requests in
`a queue according to priority and possibly interrupting
`ongoing information transactions of lower priority, (5) plac
`ing requests in the queue “on hold”(6) retrieving a request
`from the top of the queue and conducting an information
`transaction in response to the information request if no other
`transaction is being conducted and the queue is not empty.
`The conducting of the information transaction preferably
`takes the form of providing the information request to
`protocol translator 306 and receiving the response in ready
`to-transmit form. Then the arbiter 304 preferably transmits
`the response to the requesting component. When the con
`troller 202 uses a high-Speed bus to communicate with
`EEPROM 204, the arbiter 304 is preferably provided with a
`buffer 308 for buffering responses to information requests.
`
`55
`
`40
`
`45
`
`60
`
`65
`
`8
`In this embodiment, the arbiter 304 preferably begins ser
`vicing the next information request while the response to the
`previous information request is still being transmitted.
`Protocol translator 306 is coupled to EEPROM 204 to
`make information requests and to receive responses from
`EEPROM 204. In a preferred embodiment, an SPI bus
`couples translator 306 to EEPROM 204. The arbiter 304
`transfers an information request to translator 306 to be
`translated and relayed to EEPROM 204. The translator 306
`preferably converts the information request from the incom
`ing bus protocol into the SPI protocol. Similarly, translator
`306 preferably converts the response from the SPI protocol
`back into the original bus protocol. It is expected that in an
`ASIC, the translator 306 could be implemented using a
`relatively simple State machine. It should also be understood
`that other bus protocols including IC and Microwire"M
`could be used to communicate between the controller 202
`and the EEPROM 204.
`Referring now to FIG. 4, an alternate embodiment is
`shown in which the central EEPROM module is incorpo
`rated into flash ROM 124. In the embodiment of FIG. 4, the
`non-volatile memory array of Flash ROM 124 is divided
`into a BIOS area 406 and an EEPROM DATA area 408. The
`BIOS area 406 is accessed by the CPU 102 in the normal
`fashion, i.e. via a System bus and a System interface 402.
`System components are coupled to the EEPROM DATA
`area 408 via an EEPROM interface 404. Since it is not
`unlikely that CPU 102 would be accessing the BIOS at
`roughly the same time the various System components are
`trying to access their EEPROM information, the system
`interface 402 and the EEPROM interface 404 may be
`configured to coordinate their accesses to the non-volatile
`memory array. As the CPU 102 is normally wait-state
`tolerant, EEPROM interface 404 may control the overall
`arbitration for access to the non-volatile memory array. It is
`expected that this embodiment would result in the greatest
`Savings of Space on the motherboard.
`Hence, a central, shared EEPROM module has been
`disclosed which provides advantages in terms of cost and
`Space Savings when various System components are inte
`grated onto the System board. In particular, an embodiment
`has been disclosed which perm