(12) United States Patent
`Us 6,345,330 B2
`(10) Patent N0.:
`Chu
`(45) Date of Patent:
`*Feb. 5, 2002
`
`US006345330B2
`
`(54)
`
`COMMUNICATION CHANNEL AND
`INTERFACE DEVICES FOR BRIDGING
`COMPUTER INTERFACE BUSES
`
`Inventor:
`
`(75)
`
`William W. Y. Chu, Los Altos, CA
`(US)
`
`(73)
`
`Assignee:
`
`Acqis Technology, Inc., Mountain
`View, CA (US)
`
`Notice:
`
`This patent issued on a continued pros-
`ecution application filed under 37 CFR
`1.53(d), and is subject to the twenty year
`patent
`term provisions of 35 U.S.C.
`154(a)(2).
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21)
`
`(22)
`
`(60)
`
`(51)
`
`(52)
`(58)
`
`(56)
`
`EP
`
`Appl. No.:
`Filed:
`
`09/149,882
`
`Sep. s, 1998
`
`Related US. Application Data
`Provisional application No. 60/083,886, filed on May 1,
`1998, and provisional application No. 60/092,706, filed on
`Jul. 14, 1998.
`
`Int. Cl.7 ........................... G06F 3/00; G06F 13/12;
`G06F 13/28; G06F 13/00
`............................ 710/65; 710/29; 710/101
`US. Cl.
`Field of Search ............................ 375/244; 710/29,
`710/62, 65, 70, 71, 101, 128, 129, 69, 106;
`708/100
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`................. 375/249
`4,700,362 A * 10/1987 Todd et al.
`4,890,282 A
`12/1989 Lambert et al.
`.............. 370/79
`
`(List continued on next page.)
`FOREIGN PATENT DOCUMENTS
`0 722 138 A
`
`7/1996
`
`JP
`
`06 289953 A
`
`10/1994
`
`(List continued on next page.)
`OTHER PUBLICATIONS
`
`Digital Semiconductor, 21152 PCI—to—PCI Bridge Product
`Brief (02/96).
`
`(List continued on next page.)
`
`Primary Examiner—Thomas Lee
`Assistant Examiner—Chun Cao
`
`Agent,
`(74) Attorney,
`Townsend&CreW LLP
`
`or
`
`Firm—Townsend&
`
`(57)
`
`ABSTRACT
`
`The present invention encompasses an apparatus for bridg-
`ing a first computer interface bus and a second computer
`interface bus, Where each of the first and second computer
`interface buses have a number of parallel multiplexed
`address/data bus lines and operate at a clock speed in a
`predetermined clock speed range having a minimum clock
`speed and a maximum clock speed. The apparatus comprises
`an interface channel having a clock line and a plurality of bit
`lines for transmitting bits; a first interface controller coupled
`to the first computer interface bus and to the interface
`channel to encode first control signals from the first com-
`puter interface bus into first control bits to be transmitted on
`the interface channel and to decode second control bits
`received from the interface channel
`into second control
`signals to be transmitted to the first computer interface bus;
`and a second interface controller coupled to the interface
`channel and the second computer interface bus to decode the
`first control bits from the interface channel into third control
`signals to be transmitted on the second computer interface
`bus and to encode fourth control signals from the second
`computer interface bus into the second control bits to be
`transmitted on the interface channel.
`
`In one embodiment, the first and second interface controllers
`comprise a host interface controller (HIC) and a peripheral
`interface controller (PIC), respectively, the first and second
`computer interface buses comprise a primary PCI and a
`secondary PCI bus, respectively, and the interface channel
`comprises an LVDS channel.
`
`15 Claims, 57 Drawing Sheets
`
`530
`
`Primary PCI Bus
`
`PCI Clock
`
`Asynchronous
`
`é
`
`515
`
`Asynchronous
`
`é
`
`IO Control
`PCI Bus
`
`1
`
`Controller
`
`
`
`
`
`XPBus
`510/__l—L_ 525
`PLL
`Controller
`
`
`Clock
`
`
`F520
`----+----- —
`i I PDR[3' a], PCNR
`I
`XPBus \\\\\\
`
`Rasarw '
`
`
`‘l 592
`590
`—595 l 594
`Fun 0], PCN :
`__2
`
`
`
`Controller
`575
`
`
`
`
`
`PCI Bus
`
`\
`IO
`
`
`
`5 Controller
`
`560
`Control
`
`
`
`
`PCI Clock
`
`
`Secondary
`PCI
`PCI Bus
`
`
`Device
`
` 580
`
`
`
`
`
`
`Host
`Interface
`Controller
`
`505
`
`Peripheral
`Interiaoe
`Controller
`
`
`
`555
`
`Samsung
`
`Ex. 1005 - Page 1
`
`Samsung
`Ex. 1005 - Page 1
`
`

`

`US 6,345,330 132
`
`Page 2
`
`US. PATENT DOCUMENTS
`
`......... 714/798
`
`........... 361/687
`
`7/1990 Fredericks et al.
`4,939,735 A *
`1/1994 Haynes et a1.
`5,278,509 A
`1/1994 Kikinis
`5,278,730 A
`3/1994 Free
`5,293,497 A
`7/1994 Kikinis
`5,331,509 A
`10/1994 Horowitz et 81.
`5,355,391 A
`10/1995 Kobayashi
`.................. 395/281
`5,463,742 A
`7/1996 Kikinis
`5,539,616 A
`8/1996 Rahamim et al.
`5,550,710 A
`11/1996 Dillon et 81.
`5,578,940 A
`1
`3133; Elms f; ‘11-
`3:82:93 2
`/
`79‘.”
`et a ‘
`’
`’
`6/1997 Klkmls
`5’640’302 A
`8/1997 Huynh etal.
`5,659,773 A
`9/1997 Dillon et a1.
`5,663,661 A
`10/1997 Kikinis
`5,680,126 A
`.............. 395/281
`2/1998 Kikinis et al.
`5,721,837 A
`10/1998 Boehling et al-
`395/284
`5,819,050 A
`
`3’332’3132 3313/33? 261196th3 al‘
`" 313/153
`..............
`ar us e a .
`,
`,
`1/1999 Prentice ...................... 348/469
`5,859,669 A *
`5/1999 Benson et a1.
`.
`5,907,566 A *
`714/798
`
`9/1999 Jenkins et a1.
`.
`5,948,047 A
`708/141
`
`5,960,213 A *
`9/1999 Wilson ......
`710/2
`5,968,144 A * 10/1999 Walker et a1.
`.
`709/100
`
`5,991,844 A * 11/1999 Khosrowpour
`710/129
`.............. 708/100
`5,999,952 A
`12/1999 Jenkins et al.
`
`6,029,183 A
`6,040,792 A *
`6,052,513 A *
`6,216,185 B1
`
`708/100
`2/2000 Jenkins et al.
`..
`
`341/100
`3/2000 Watson et al.
`..
`
`395/294
`4/2000 MacLaren
`4/2001 Chu ........................... 710/101
`
`FOREIGN PATENT DOCUMENTS
`
`W0
`W0
`W0
`
`92 18924 A
`94 00970 A
`95 13640 A
`
`10/1992
`1/1994
`5/1995
`
`OTHER PUBLICATIONS
`Intel Corporation, Intel 430TX PCISET: 82439TX System
`Controller (MTXC) Architectural Overview (02/97).
`I
`1C
`‘
`I
`182371AB PCI
`IS
`DE XCEL
`me
`orporanom me .
`‘10— M
`ERATOR (PHX4) Architectural OVCI‘VICW (04/97).
`Intel Corporation, Intel 440LX AGPSET: 82443LX PCI
`A.G.P. Controller (PAC) Advance Information (08/97).
`National Semiconductor, DS90CR215/DS90CR216 General
`““9110“ (07/97)
`.
`.
`Nf‘nonal semlcf’nducmr’ 1359092217 PrOduCt FOIder‘
`Video Electronics Standards Assocratlon (VESA), Plug and
`Display(P&D) Standard, P&D and Digital Transition Mini-
`mized Differential Signaling (TMDS) Video Transmission
`Overview, Version 1, Revision 0, pp. 1 & 31—34 (1997).
`
`'
`
`* cited by examiner
`
`Samsung
`
`Ex. 1005 - Page 2
`
`Samsung
`Ex. 1005 - Page 2
`
`

`

`US. Patent
`
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`
`Ex. 1005 - Page 3
`
`Samsung
`Ex. 1005 - Page 3
`
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 2 0f 57
`
`US 6,345,330 B2
`
`com\
`
`28:3.2233;a;2x
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`
`Ex. 1005 - Page 4
`
`Samsung
`Ex. 1005 - Page 4
`
`
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 3 0f 57
`
`US 6,345,330 B2
`
`Computing System
`
`CPU/NB
`signals
`
`North Bride 3 Primer PCI Bus
`
`Host
`Interface
`Controller
`
`l
`
`PCl Bus Bridge
`A’ with
`Interface Dev.
`Pair And PBus
`
`on Board 2
`
`Peripheral System
`
`Peripheral
`South
`Interface
`,
`Controller
`Bridge CPU/NB'
`signals lL _____
`
`Secondar PCl Bus
`
`PCI
`Device1
`
`PCI Add-
`
`FIG. 3
`
`Samsung
`
`Ex. 1005 - Page 5
`
`Samsung
`Ex. 1005 - Page 5
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 4 0f 57
`
`US 6,345,330 B2
`
`Computing System
`
`.
`
`Integrated
`Host
`Interface
`
`PCIBusI —————————— 4
`
`Subsystem
`
`North Bridge
`
`Integrated
`Peripheral
`Interface
`Cntlr. &
`8. Bridge
`
`I
`
`405
`
`410
`
`FIG. 4
`
`Samsung
`
`Ex. 1005 - Page 6
`
`Samsung
`Ex. 1005 - Page 6
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 5 0f 57
`
`US 6,345,330 B2
`
`530
`
`Primary PCI Bus
`
`PCI Clock
`
`Host
`
`Interface
`
`
`Controller
`
`505
`
`As nchronous
`y
`
`6:
`
`51 5
`
`
`
`
`XPBus \\\\\
`woe/41
`PD[3::0]. PCN I
`
`
`
`Peripheral
`Interface
`
`Asynchronous
`
`Controller
`
`555
`
`Samsung
`
`Ex. 1005 - Page 7
`
`Samsung
`Ex. 1005 - Page 7
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 6 0f 57
`
`US 6,345,330 B2
`
`Flash Memory
`3105/
`Configuration
`
`XPBus
`
`AD[31::0] our
`
`Serial
`Par?"e' '0
`Convener
`
`I * I 0
`
`PCN
`
`Control
`Decoder &
`Separate
`Data Path
`
`Encoder 8.
`Merge
`Data Path
`........
`
`RESET#
`
`Serial to Parallel
`Converter
`
`PCNR
`
`PDR3
`l . D .
`
`Serial lo
`Parallel
`
`Host
`PCI
`
`RESET#S
`
`RDNVR
`Control
`
`CPU CNTL
`& GPIO
`Latch/Driver
`
`Con vener
`
`Video Port Data [0:215]
`
`Serial to
`Parallel
`Video Port Control
`Convener
`Graphics
`
`Controller
`
`a I a
`
`X‘
`
`..-.--..---..--..
`
`FIG. 6
`
`Samsung
`
`Ex. 1005 - Page 8
`
`Samsung
`Ex. 1005 - Page 8
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 7 0f 57
`
`US 6,345,330 B2
`
`
`
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`Ex. 1005 - Page 9
`
`Samsung
`Ex. 1005 - Page 9
`
`
`
`
`
`

`

`US. Patent
`
`2B033,543a6SU
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`
`Ex. 1005 - Page 10
`
`Samsung
`Ex. 1005 - Page 10
`
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 9 0f 57
`
`US 6,345,330 B2
`
`Primary PCI Bus
`
` FRM
`
`IIIIIl :I
`
`Samsung
`
`Ex. 1005 - Page 11
`
`Secondary PCI Bus
`
`
`
`Cable
`Delay
`PCI CLK
`
`::I z :
`
`II
`
`
`
`FIG. 9
`
`AD
`
`CIB Eff
`
`TRDXII
`
`DSEUI
`STOW
`
`POO-3
`
`PDRO-3
`
`Samsung
`Ex. 1005 - Page 11
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 10 0f 57
`
`US 6,345,330 B2
`
`Primary PCI Bus
`
`”‘3' EL" .
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`FIG. 10
`
`Samsung
`
`Ex. 1005 - Page 12
`
`Samsung
`Ex. 1005 - Page 12
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 11 0f 57
`
`US 6,345,330 B2
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`=§§=-'Ifl"
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`
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`
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`
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`
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`
`South
`Bride
`
`RESE'W
`
`Control
`Encoder &
`Merge
`Data Path
`
`CPU CNTL
`8. GPlO
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`
`ParaHel
`Convener
`
`......................
`
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`
`Video
`Clock
`
`Video Port Data [0:215]
`
`Video Port Control
`
`Parallel
`to Serial
`Convene
`
`
`
`Samsung
`
`Ex. 1005 - Page 13
`
`Samsung
`Ex. 1005 - Page 13
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 12 0f 57
`
`US 6,345,330 B2
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`Ex. 1005 - Page 14
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`Samsung
`Ex. 1005 - Page 14
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`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 13 0f 57
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`US 6,345,330 B2
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`Ex. 1005 - Page 15
`
`Samsung
`Ex. 1005 - Page 15
`
`
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 14 0f 57
`
`US 6,345,330 B2
`
`1400
`
`1410
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`
`FIG. 14
`
`Samsung
`
`Ex. 1005 - Page 16
`
`Samsung
`Ex. 1005 - Page 16
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 15 0f 57
`
`US 6,345,330 B2
`
`1550
`
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`
`1555
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`1582
`
`1581
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`
`Samsung
`
`Ex. 1005 - Page 17
`
`1500
`
`Samsung
`Ex. 1005 - Page 17
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 16 0f 57
`
`US 6,345,330 B2
`
`
`
`1605
`
`1610
`
`FIG. 16
`
`Samsung
`
`Ex. 1005 - Page 18
`
`Samsung
`Ex. 1005 - Page 18
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 17 0f 57
`
`US 6,345,330 132
`
`VLOCDNCOOOFN
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`
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`
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`
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`
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`
`
`
`
`Samsung
`
`Ex. 1005 - Page 19
`
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`Samsung
`Ex. 1005 - Page 19
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 18 0f 57
`
`US 6,345,330 B2
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`Samsung
`
`Ex. 1005 - Page 20
`
`Samsung
`Ex. 1005 - Page 20
`
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 19 0f 57
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`US 6,345,330 B2
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`Ex. 1005 - Page 21
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`Samsung
`Ex. 1005 - Page 21
`
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 20 0f 57
`
`US 6,345,330 B2
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`Samsung
`
`Ex. 1005 - Page 22
`
`Samsung
`Ex. 1005 - Page 22
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 21 0f 57
`
`US 6,345,330 B2
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`
`Ex. 1005 - Page 23
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`Samsung
`Ex. 1005 - Page 23
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 22 0f 57
`
`US 6,345,330 B2
`
`
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`Samsung
`
`Ex. 1005 - Page 24
`
`Samsung
`Ex. 1005 - Page 24
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 23 0f 57
`
`US 6,345,330 B2
`
`PCK
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`FIG. 23
`
`Samsung
`
`Ex. 1005 - Page 25
`
`Samsung
`Ex. 1005 - Page 25
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 24 0f 57
`
`US 6,345,330 B2
`
`Primary PCI Bus
`
`
`
`Host
`
`Interface
`
`Controller
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`Peripheral
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`Controller
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`Samsung
`
`Ex. 1005 - Page 26
`
`Samsung
`Ex. 1005 - Page 26
`
`

`

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`Graphics
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`
`US. Patent
`
`Feb. 5, 2002
`
`Sheet 25 0f 57
`
`US 6,345,330 B2
`
`2501
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`Flash Memory
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`Samsung
`
`Ex. 1005 - Page 27
`
`Samsung
`Ex. 1005 - Page 27
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 26 0f 57
`
`US 6,345,330 B2
`
`2601
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`Samsung
`
`Ex. 1005 - Page 28
`
`Samsung
`Ex. 1005 - Page 28
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 27 0f 57
`
`US 6,345,330 B2
`
`
`
`2710
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`2705
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`FIG. 27
`
`Samsung
`
`Ex. 1005 - Page 29
`
`Samsung
`Ex. 1005 - Page 29
`
`

`

`US. Patent
`
`6
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`Ex. 1005 - Page 30
`
`Samsung
`Ex. 1005 - Page 30
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 29 0f 57
`
`US 6,345,330 B2
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`Ex. 1005 - Page 31
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`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 30 0f 57
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`US 6,345,330 B2
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`Ex. 1005 - Page 32
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`Samsung
`Ex. 1005 - Page 32
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`
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`US. Patent
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`Feb. 5, 2002
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`Sheet 31 0f 57
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`US 6,345,330 B2
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`Ex. 1005 - Page 33
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`Samsung
`Ex. 1005 - Page 33
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`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 32 0f 57
`
`US 6,345,330 B2
`
`PCK
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`
`Ex. 1005 - Page 34
`
`Samsung
`Ex. 1005 - Page 34
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 33 0f 57
`
`US 6,345,330 B2
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`Ex. 1005 - Page 35
`
`Samsung
`Ex. 1005 - Page 35
`
`
`

`

`US. Patent
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`75M
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`Samsung
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`Ex. 1005 - Page 36
`
`Samsung
`Ex. 1005 - Page 36
`
`
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 35 0f 57
`
`US 6,345,330 B2
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`Samsung
`
`Ex. 1005 - Page 37
`
`Samsung
`Ex. 1005 - Page 37
`
`
`
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 36 0f 57
`
`US 6,345,330 B2
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`Samsung
`
`Ex. 1005 - Page 38
`
`Samsung
`Ex. 1005 - Page 38
`
`
`
`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 37 0f 57
`
`US 6,345,330 B2
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`Ex. 1005 - Page 39
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`

`US. Patent
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`Feb. 5, 2002
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`Sheet 38 0f 57
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`Ex. 1005 - Page 40
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`Ex. 1005 - Page 40
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`

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`US. Patent
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`Feb. 5, 2002
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`Sheet 39 0f 57
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`US 6,345,330 B2
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`transaction:
`
`33MhzPCIRead
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`FIG.39
`
`
`
`Samsung
`
`Ex. 1005 - Page 41
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`Samsung
`Ex. 1005 - Page 41
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`

`

`US. Patent
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`Feb. 5, 2002
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`Sheet 40 0f 57
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`US 6,345,330 B2
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`transaction:
`
`33MhzPCIWrite
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`FIG.40
`
`Samsung
`
`Ex. 1005 - Page 42
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`Samsung
`Ex. 1005 - Page 42
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`

`

`US. Patent
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`Feb. 5, 2002
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`Sheet 41 0f 57
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`US 6,345,330 B2
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`
`Ex. 1005 - Page 43
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`Samsung
`Ex. 1005 - Page 43
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`
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`US. Patent
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`Feb. 5, 2002
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`Sheet 42 0f 57
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`US 6,345,330 B2
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`Ex. 1005 - Page 44
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`Ex. 1005 - Page 44
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`

`US. Patent
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`Feb. 5, 2002
`
`Sheet 43 0f 57
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`US 6,345,330 B2
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`Ex. 1005 - Page 45
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`Samsung
`Ex. 1005 - Page 45
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`
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`

`

`US. Patent
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`Feb. 5, 2002
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`Sheet 44 0f 57
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`US 6,345,330 B2
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`Ex. 1005 - Page 46
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`Samsung
`Ex. 1005 - Page 46
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`US. Patent
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`Feb. 5, 2002
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`Sheet 45 0f 57
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`US 6,345,330 B2
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`Ex. 1005 - Page 47
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`Samsung
`Ex. 1005 - Page 47
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`
`

`

`US. Patent
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`Feb. 5, 2002
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`Sheet 46 0f 57
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`US 6,345,330 B2
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`
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`
`Ex. 1005 - Page 48
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`
`Samsung
`Ex. 1005 - Page 48
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`
`
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`US. Patent
`
`Feb. 5, 2002
`
`Sheet 47 0f 57
`
`US 6,345,330 B2
`
`Name
`
`Type Pins Description
`
`AD[31 ::o1
`C/BE[3::0]#
`
`FRAME#
`
`|RDY#
`
`TRDY#
`
`DEVSEL#
`
`STS 1
`
`STS 1
`
`32 Multiplexed Address/Data. AD is driven to a valid state when GNT# is asserted.
`TS
`T84
`Multiplexed Command/Byte Enables. For a two-address transaction. 1st
`address phase carries the command, and the 2nd address phase carries the
`transaction type. C/BE is driven to a valid state when GNT# is asserted.
`Indicates beginning and duration of a PCI transaction. When the bus is idle,
`FRAME# is driven to High for 1 cycle. A pull-up resistor sustains STS signal.
`Initiator Ready. IRDY# is driven High for 1 cycle if bus is idle, and the state is
`sustained by a pull-up resistor.
`Target Ready. When bus is idle, TRDY# is driven High for 1 cycle it bus is idle.
`An external pull-up resistor sustains STS signal.
`Device Select. DEVSEL# is asserted by target to indicate it is ready to accept
`the transaction. HIC decodes address of a transaction to decide the need to
`
`STS 1
`
`STS 1
`
`assert DEVSEL#. As an initiator, HIC waits for 5 cycles to detect assertion of
`DEVSEL# by the target; otherwise HIC terminates with a master abort.
`DEVSEL# is driven High for 1 cycle when bus is idle, and the state is sustained
`by a pull-up resistor.
`Target request to stop transaction. There are 3 cases:
`STOP#, TRDY# & DEVSEL# asserted: disconnect with data transfer
`Only STOP# & DEVSEL# asserted: request initiator to retry later
`Only STOP# asserted: target abort
`STOP# is driven High for 1 cycle when bus is idle, and the state is sustained by
`a pull-up resistor.
`Even parity for 36 bits of AD & C/BE#. PAR is sent one cycle after address or
`data is valid.
`In write transaction, initiator sends PAR one cycle after write data
`is valid.
`In read transaction, target sends PAR one cycle after read data is valid.
`Initiator request lock on target downstream. LOCK# is asserted 1 clock cycle
`after address phase by an initiator wanting to perform an atomic operation that
`take more than one transaction to complete. HIC passes the LOCK# request to
`the secondary PCI bus. HIC does not drive LOCK# or propagate LOCK#
`upstream.
`Chip Select for Type 0 configuration access. During a Type 0 configuration
`transaction, the initiator asserts IDSEL# during the address phase to select HIC.
`HIC responds by asserting DEVSEL#.
`Data Parity Error on all transactions except Special Cycle. PERR# is driven one
`clock cycle after PAR. PERR# is asserted by target during write transactions,
`and by initiator during read transactions.
`System Error. HIC asserts SERR# under the following conditions:
`Address parity error, Secondary bus SERR# asserted,
`Posted write transaction: data parity error on target bus. Posted write transaction discarded,
`Master abort, Target abort
`Delayed read or write transaction discarded, and
`Delayed transaction master timeout.
`Request for bus.
`If a target retry or disconnect is received in response to
`initiating a transaction, HIC deasserts REQ# for at least 2 cycles before
`asserting it again.
`Bus is granted to HIC. HIC can initiate transaction if GNT# is asserted and the
`bus is idle. When HIC is not requesting bus and GNT# is asserted, HIC must
`drive AD, C/BE. and PAR to valid logic levels.
`Input indicating clock status. HIC can request the central clock resource to start,
`speed up or maintain the PCI clock. There are 3 clocking states:
`Clock running, Clock about to stop/slow down, and Clock stopped/slowed.
`PCI Clock. All inputs are sampled on the rising edge of PCICK. Frequency
`
`STOP#
`
`STS 1
`
`PAR
`
`T81
`
`LOCK#
`
`Input
`
`1
`
`IDSEL#
`
`Input
`
`1
`
`PERR#
`
`STS 1
`
`SERR#
`
`OD1
`
`REQ#
`
`T81
`
`GNT#
`
`Input 1
`
`CLKRUN#
`
`l/OD 1
`
`PCICK
`
`Input 1
`
`FIG. 47
`
`Samsung
`
`Ex. 1005 - Page 49
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`Samsung
`Ex. 1005 - Page 49
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`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 48 0f 57
`
`US 6,345,330 B2
`
`mamaxEotSac.:mn._mcm_w$35520x020Ewcatmn.lg;
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`
`Ex. 1005 - Page 50
`
`Samsung
`Ex. 1005 - Page 50
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`
`
`

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`US. Patent
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`Feb. 5, 2002
`
`Sheet 49 0f 57
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`US 6,345,330 B2
`
`
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`Ex. 1005 - Page 51
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`Samsung
`Ex. 1005 - Page 51
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`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 50 0f 57
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`US 6,345,330 B2
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`
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`Samsung
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`Ex. 1005 - Page 52
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`Samsung
`Ex. 1005 - Page 52
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`

`

`US. Patent
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`Samsung
`Ex. 1005 - Page 53
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`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 52 0f 57
`
`US 6,345,330 B2
`
`Signals
`
`stDataInTestDataOut
`
`9
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`
`TestModeSelect
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`FIG.52
`
`Samsung
`
`Ex. 1005 - Page 54
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`Samsung
`Ex. 1005 - Page 54
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`

`

`US. Patent
`
`Feb. 5, 2002
`
`Sheet 53 0f 57
`
`US 6,345,330 B2
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`Ex. 1005 - Page 55
`
`Samsung
`Ex. 1005 - Page 55
`
`

`

`US. Patent
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`Ex. 1005 - Page 56
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`Samsung
`Ex. 1005 - Page 56
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`

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`US. Patent
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`Ex. 1005 - Page 57
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`Samsung
`Ex. 1005 - Page 57
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`

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`US. Patent
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`Feb. 5, 2002
`
`Sheet 56 0f 57
`
`US 6,345,330 B2
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`Ex. 1005 - Page 58
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`Samsung
`Ex. 1005 - Page 58
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`

`

`US. Patent
`
`Feb.5,2002
`
`Sheet57 0f57
`
`US 6,345,330 B2
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`Samsung
`Ex. 1005 - Page 59
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`
`

`

`US 6,345,330 B2
`
`1
`COMMUNICATION CHANNEL AND
`INTERFACE DEVICES FOR BRIDGING
`COMPUTER INTERFACE BUSES
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application claims any and all benefits as provided
`by law of US. Provisional Application No. 60/083,886 filed
`May 1, 1998 and of US. Provisional Application No.
`60/092,706 filed on Jul. 14, 1998.
`This application is being filed concurrently with the
`application of William W. Y. Chu for “Personal Computer
`Peripheral Console With Attached Computer Module”, filed
`on Sep. 8, 1998 now US. Pat. No. 6,216,185, and incorpo-
`rates the material therein by reference.
`BACKGROUND OF THE INVENTION
`
`The present invention generally relates to computer inter-
`faces. More specifically, the present invention relates to an
`interface channel
`that
`interfaces two computer interface
`buses that operate under protocols that are different from that
`used by the interface channel.
`Interfaces coupling two independent computer buses are
`well known in the art. Ablock diagram of a computer system
`utilizing such a prior art interface is shown in FIG. 1. In FIG.
`1, a primary peripheral component interconnect (PCI) bus
`105 of a notebook PC 100 is coupled to a secondary PCI bus
`155 in a docking system 150 (also referred to as docking
`station 150) through high pin count connectors 101 and 102,
`which are normally mating connectors. The high pin count
`connectors 101 and 102 contain a sufficiently large number
`of pins so as to carry PCI bus signals between the two PCI
`buses without any translation. The main purpose for inter-
`facing the two independent PCI buses is to allow transac-
`tions to occur between a master on one PCI bus and a target
`on the other PCI bus. The interface between these two
`
`i