(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2001/0011312 A1
`(43) Pub. Date:
`Aug. 2, 2001
`CHU
`
`US 20010011312A1
`
`(54) COMMUNICATION CHANNEL AND
`INTERFACE DEVICES FOR BRIDGING
`COMPUTER INTERFACE BUSES
`
`(75) Inventor: WILLIAM W. Y. CHU, LOS ALTOS,
`CA (US)
`
`Correspondence Address:
`RICHARD TOGAWA
`TOWNSEND AND TOWNSEND AND CREW
`LLP
`TWO EMBARCADERO CENTER
`8TH FLOOR
`SAN FRANCISCO, CA 94111-3834 (US)
`
`(73) Assignee: ACQISTECHNOLOGY, INC.
`(*)
`Notice:
`This is a publication of a continued pros
`ecution application (CPA) filed under 37
`CFR 1.53(d).
`
`(21) Appl. No.:
`
`09/149,882
`
`(22) Filed:
`
`Sep. 8, 1998
`Related U.S. Application Data
`
`(63) Non-provisional of provisional application No.
`60/083,886, filed on May 1, 1998. Non-provisional of
`provisional application No. 60/092,706, filed on Jul.
`14, 1998.
`
`Publication Classification
`
`(51) Int. Cl." ............................ G06F 13/12; G06F 13/38
`(52) U.S. Cl. ................................................................ 710/64
`(57)
`ABSTRACT
`The present invention encompasses an apparatus for bridg
`ing a first computer interface bus and a Second computer
`interface bus, where each of the first and Second computer
`interface buses have a number of parallel multiplexed
`address/data bus lines and operate at a clock Speed in a
`predetermined clock Speed range having a minimum clock
`Speed and a maximum clock Speed. The apparatus comprises
`an interface channel having a clock line and a plurality of bit
`lines for transmitting bits, a first interface controller coupled
`to the first computer interface bus and to the interface
`channel to encode first control Signals from the first com
`puter interface bus into first control bits to be transmitted on
`the interface channel and to decode Second control bits
`received from the interface channel into Second control
`Signals to be transmitted to the first computer interface bus,
`and a Second interface controller coupled to the interface
`channel and the Second computer interface bus to decode the
`first control bits from the interface channel into third control
`Signals to be transmitted on the Second computer interface
`buS and to encode fourth control Signals from the Second
`computer interface bus into the Second control bits to be
`transmitted on the interface channel.
`In one embodiment, the first and Second interface controllers
`comprise a host interface controller (HIC) and a peripheral
`interface controller (PIC), respectively, the first and second
`computer interface buses comprise a primary PCI and a
`Secondary PCI bus, respectively, and the interface channel
`comprises an LVDS channel.
`
`
`
`25
`
`Samsung
`Ex. 1013 - Page 1
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 1 of 57
`
`US 2001/0011312 A1
`
`Notebook PC
`
`
`
`
`
`Secondary PC Bus
`
`loo
`
`High Pin Count
`Connectors
`
`Samsung
`Ex. 1013 - Page 2
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 2 of 57
`
`US 2001/0011312 A1
`
`
`
`Gu RE 2
`
`Samsung
`Ex. 1013 - Page 3
`
`

`

`Patent Application Publication Aug. 2, 2001 Sheet 3 of 57
`
`US 2001/0011312 A1
`
`Computing System
`
`
`
`PC Bus Bridge with
`interface Dev. Pair
`41And PBus
`
`Peripheral System
`
`Peripheral
`E.
`interface
`fidge CPU/NB
`Controller
`signals - - - as as
`Secondary PC Bus
`
`f Gut 3
`
`Samsung
`Ex. 1013 - Page 4
`
`

`

`Patent Application Publication Aug. 2, 2001 Sheet 4 of 57
`
`US 2001/0011312 A1
`
`Computing System
`
`
`
`Graphics
`Subsystem
`
`integrated
`Host
`interface
`Cntlr &
`North Bridge
`
`405
`
`Peripheral System
`
`Integrated
`Peripheral
`interface
`Cntir. &
`
`H O
`
`Samsung
`Ex. 1013 - Page 5
`
`

`

`Patent Application Publication Aug. 2, 2001 Sheet 5 of 57
`
`US 2001/0011312 A1
`
`
`
`Samsung
`Ex. 1013 - Page 6
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 6 of 57
`
`US 2001/0011312 A1
`
`
`
`Flash Memory
`BIOS
`Configuration
`
`all RDMR
`
`AD MUX Cnt
`
`-
`
`Parallel to
`Serial
`Converter
`
`Parallel
`Converter
`
`CPUCNT
`& GPO
`Latch.Driver
`
`Video Port Data (0:15
`
`Video Port Control
`
`Serial to
`Parallel
`Converter
`
`FGu RE G
`
`Samsung
`Ex. 1013 - Page 7
`
`

`

`Patent Application Publication Aug. 2, 2001 Sheet 7 of 57
`
`US 2001/0011312 A1
`
`
`
`Samsung
`Ex. 1013 - Page 8
`
`

`

`Patent Application Publication Aug. 2, 2001 Sheet 8 of 57
`
`US 2001/0011312 A1
`
`BC as Master
`FRAME #
`IRDY#
`TRDY #
`DEVSEL H.
`STOP #
`PAR
`IDSEL
`PERR #
`SERRA
`REQ#
`GNT #
`RST
`
`
`
`Local
`Local
`Local
`Encode
`Local
`Encode
`
`Encode
`
`Decode
`Decode
`
`Decode
`Decode
`Decode
`Decode
`
`Transaction Active
`Initiator Ready
`Receive from Target
`Receive from Target
`retry handles locally
`Parity for A/C, DBE
`Used locally for config. 0
`Data Parity Error
`Address/System Parity Error
`HIC continue to be Master
`Arbiter grant bus to HIC
`
`
`
`PCI device can end REQi
`Arbiter can deassert GNTH
`Independent signal
`
`FGuRE 8
`
`Samsung
`Ex. 1013 - Page 9
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 9 of 57
`
`US 2001/0011312 A1
`
`
`
`Samsung
`Ex. 1013 - Page 10
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 10 of 57 US 2001/0011312 A1
`
`Poos e
`
`>1
`se
`
`RI
`Secondary PC Bus.
`CKA\ A\ A\ A\ A\ A\ .
`2 clocks s
`
`Gu RB | O
`
`Samsung
`Ex. 1013 - Page 11
`
`

`

`Patent Application Publication Aug. 2, 2001 Sheet 11 of 57 US 2001/0011312 A1
`
`
`
`Flash Memory
`(Optional)
`
`C. C.
`
`Earl DWR
`
`R
`UX C
`
`N
`
`- AD31:0) out
`
`Parallel to Serial *
`Converter
`
`Serial to
`Parallel
`
`O r
`
`Video Port Data (0:15)
`
`Video Port Control
`
`Samsung
`Ex. 1013 - Page 12
`
`

`

`Patent Application Publicati
`on Aug. 2, 2001 Sheet 12 of 57 US 2001/0011312 A1
`
`
`
`PIC as Target
`
`Signal
`FRAME #
`IRDY#
`TRDY H.
`DEVSEL i
`
`Encode (BSO)
`Encode (BS)
`Local
`Local
`
`IDSEL
`
`Local
`
`
`
`Transaction Active
`Initiator Ready
`PIC Generates
`PIC Accepts Command
`PC requests to ret
`Used locally for config. 0
`
`Positive decode, medium
`Host can stop trans,
`
`Encode
`
`Decode
`
`PC requests to be master
`PC grants bus to itself
`
`P. Bus device requests bus
`Independent signal
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`f Gu RE 12
`
`Samsung
`Ex. 1013 - Page 13
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 13 of 57 US 2001/0011312 A1
`
`
`
`PC as Master (Default
`
`Address/System Parity Error
`
`Arbiter grant bus to PIC
`
`FGuf E 3
`
`Samsung
`Ex. 1013 - Page 14
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 14 of 57 US 2001/0011312 A1
`
`
`
`Samsung
`Ex. 1013 - Page 15
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 15 of 57 US 2001/0011312 A1
`
`As oo
`
`
`
`5SO
`
`AC
`
`Samsung
`Ex. 1013 - Page 16
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 16 of 57 US 2001/0011312 A1
`
`
`
`Samsung
`Ex. 1013 - Page 17
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 17 of 57 US 2001/0011312 A1
`
`ACM's XISBUS Coastector Pius PIN Fosition (83 pin):
`
`
`
`\G use \
`
`Samsung
`Ex. 1013 - Page 18
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 18 of 57 US 2001/0011312 A1
`
`
`
`POR1 --
`POR -
`
`P40
`
`PCN
`
`LVDS
`
`3.3v or GND
`3.3v or GND
`
`Description
`Peripheral data reverse 0 +
`Peripheral data reverse 0 -
`Peripheral data reverse +
`Peripheral data reverse
`-
`Peripheral data reverse 2 -
`Peripheral data reverse 2 -
`Peripheral clock reverse +
`Peripheral clock reverse -
`Peripheral data reverse 3 +
`Peripheral data reverse 3 -
`Peripheral control reverse +
`Peripheral control reverse -
`Peripheral data 0 +
`Peripheral data 0 -
`Peripheral data 1 +
`Peripheral data 1 -
`Peripheral data 2 --
`Peripheral data 2 -
`Peripheral clock +
`
`Peripheral data 3 +
`Peripheral data 3 -
`Peripheral control
`Peripheral Control -
`Configuration bit 0
`Configuration bit
`
`F. Gu RE
`
`3
`
`Samsung
`Ex. 1013 - Page 19
`
`

`

`Patent Application Publication Aug. 2, 2001 Sheet 19 of 57
`
`US 2001/0011312 A1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`V16
`
`V28
`
`v33
`
`V38
`V41
`V13
`V35
`
`Symbol |
`Red Video
`Green Video
`
`Signal
`
`5.
`
`P
`This
`Super Video
`SVC/CNTL2
`VESAP & D
`VESA P&D
`VESAP & D
`VESA P& D
`
`TMD
`S
`TMDS
`CLK-T TMDS
`
`TMDS
`LVDS
`LVDS
`VDS
`LVDS
`
`D2 +
`D2 -
`WPCK+
`VPCK -
`VPD -
`Config 2
`Config3
`
`VESA P & D
`
`33v or GND
`3.3v or GND
`3.3v or GND
`
`
`
`
`
`
`
`
`
`video
`Horizontal Sync
`Vertical Sync
`
`TV Composite Video
`
`Clock -
`
`Data2+
`
`Video Port Pixel Clock -
`Video Port Pixel Data
`Video Port Pixel Data -
`Configuration bit 2
`
`Samsung
`Ex. 1013 - Page 20
`
`

`

`Patent Application Publication Aug. 2, 2001 Sheet 20 of 57 US 2001/0011312 A1
`
`Signal
`
`Data Rate
`
`Synch. To PCK
`
`3
`4
`6
`7
`8
`9
`10
`12
`13
`
`Description
`Symbol
`GND
`PD0RTN
`Computer to Peripheral LVDS Data 0 +
`Computer to Peripheral LVDS Data O -
`PD0 -
`GND
`PD RTN
`Computer to Peripheral LVDS Data 1 +
`Computer to Peripheral LVDS Data 1 -
`PD -
`GND
`PD2 RTN
`PD2 + Synch. To PCK 10x clock rate Computer to Peripheral LVDS Data2
`PD2 -
`Computer to Peripheral LVDS Data2
`PD3 RTN
`GND
`Computer to Peripheral LVDS Data 3 +
`PD3 -
`Computer to Peripheral LVDS Data 3 -
`PCKRTN
`GND
`PCK -
`Computer to Peripheral LVDS Clock -
`PCN RTN
`GND
`PCN -
`Computer to Peripheral LVDS Control -
`PDRORTN
`GND
`PDRO -
`Peripheral to Computer LVDS Data 0
`21
`22 PDR RTN
`GND
`24
`PDR1 -
`Peripheral to Computer LVDS Data 1 -
`25
`PDR2 RTN
`GND
`27
`PDR2 -
`Peripheral to Computer LVDS Data2
`PDR3 RTN
`GND
`PDR3 + Synch. To PCKR
`PDR3 -
`Peripheral to Computer LVDS Data 3
`30
`31 PCKRRTN
`GND
`32
`PCKR+Reverse Dir. Clock
`PCKR -
`Peripheral to Computer LVDS Clock
`34 PCNRRTN
`GND
`36
`PCNR -
`Peripheral to Computer LVDS Control
`RESETH
`Reset
`
`16
`18
`
`Synch. To PCKR
`
`Synch. To PCKR
`
`Synch. To PCKR
`
`Asynchronous
`
`Gu RE 20
`
`Samsung
`Ex. 1013 - Page 21
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 21 0f 57
`
`US 2001/0011312 A1
`
`
`CK+ CK+ CK"- CK+ OK+ dK- CK~ CK- CK- CK-
`OMM A00 A01 A02 A03 A04 A05 A06 A07
`
`1 6M1! A06 A09 A10 A11 A12 A13 A14 A15
`CMZS A16 A17 A18 A19 A20 A21 A2 A23
`
`cm A24 A25 A26 A27 A28 A29 A30 A31
`ON1
`ONZ CNS 0N1 0N5 0N6 ONT CN8 0N9
`
`CK- CK- CK- CK-
`CK+ CKé OK+ CK“> CK+ CK-
`004
`005
`006
`007
`830 BE” 000 001
`002
`003
`012
`013
`014
`015
`BS1
`BE1# 008 009
`010
`011
`020
`021
`022
`023
`882 3-: 016 017
`018
`019
`023
`029
`030
`031
`BS3 BBS 02% 025
`026
`027
`ONO 0N1
`CNZ 0N3 0N4 0N5 0N6 0N7 0N8 CNS
`
`1 Fiwka 1‘
`
`Samsung
`
`Ex. 1013 - Page 22
`
`Samsung
`Ex. 1013 - Page 22
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 22 of 57 US 2001/0011312 A1
`
`PCK
`
`PCK-
`
`PCK
`
`
`
`ea.
`
`EE
`
`PCK-
`
`PCK-
`
`PCK
`
`PCK
`
`BSO
`
`D
`
`BS2 EE2.
`3S3 3S
`
`
`
`C
`
`SS
`
`DA
`
`s
`
`N4
`
`N17
`
`Samsung
`Ex. 1013 - Page 23
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 23 of 57 US 2001/0011312 A1
`
`PCK
`
`PDO
`
`PD1
`
`PO2
`
`PCN
`
`. PCK
`
`>> ={ Receiver
`
`es
`
`PDO
`
`PD1
`
`PD2
`
`
`
`PCN
`
`s
`
`\GWR 27
`
`Samsung
`Ex. 1013 - Page 24
`
`

`

`Patent Application Publication Aug. 2, 2001 Sheet 24 of 57 US 2001/0011312 A1
`
`Primary PC Bus
`
`Asynchronous
`K.
`
`XPBUS -----
`
`PD(3:0)
`
`
`
`Asynchronous
`
`Race
`Controller
`
`Peripheral
`interface
`Controller
`
`Gu RE 2'
`
`Samsung
`Ex. 1013 - Page 25
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 25 of 57 US 2001/0011312 A1
`
`
`
`25,
`
`hi
`
`role 1
`
`52
`
`as
`
`Master
`Control
`
`Contro
`Merge
`
`EEE -
`Enc Life
`Matt Data Path a |E
`REET"
`253o
`Decode s DataP
`s E. s.
`Erath
`
`also
`
`Control
`
`N
`
`Samsung
`Ex. 1013 - Page 26
`
`

`

`Patent Application Publication Aug. 2, 2001 Sheet 26 of 57 US 2001/0011312 A1
`
`
`
`Msir Data Path'
`
`C
`
`is ".
`
`ics
`
`Transmitter
`
`CPU CNTL
`& GPO
`LatchDriver
`
`2410
`
`Video Port Data 0:15
`
`Wideo Port Control
`
`Samsung
`Ex. 1013 - Page 27
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 27 of 57 US 2001/0011312 A1
`
`
`
`(, u :
`
`)
`
`Samsung
`Ex. 1013 - Page 28
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 28 of 57 US 2001/0011312 A1
`
`ACM's CMIBUS Connector Plug PIN Position (83 pin):
`
`
`
`Samsung
`Ex. 1013 - Page 29
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 29 of 57 US 2001/0011312 A1
`
`Pin No.
`
`Symbol
`
`Signal
`
`Standard
`
`
`
`EEE LVDS
`PDR1 +
`LVDS
`P6
`PDR) -
`LVDS
`P8
`LVDS
`P9
`LVDS
`Pll
`LVDS
`P2
`LVDS
`P15
`LVDS
`P16
`LVDS
`P24
`LVDS
`P25
`LVDS
`P27
`LVDS
`P28
`LVDS
`P30
`LVDS
`P31
`LVDS
`P33
`LVDS
`P34
`LVDST
`P37
`LVDS
`P38
`LVDS
`P13
`Static
`
`PDR3 +
`PDR3 -
`PD0 + I
`PDO -
`PD1 +
`PD1 -
`PD2 -
`PD2 -
`PCK+
`PCK -
`PD3 +
`PD3 -
`Config O
`
`3.3v or GND
`
`Description
`--
`Peripheral data reverse 0 +
`Peripheral data reverse 0 -
`Peripheral data reverse 1 +
`Peripheral data reversel -
`Peripheral data reverse 2 +
`Peripheral data reverse 2 -
`Peripheral clock reverse +
`Peripheral clock reverse -
`Peripheral data reverse 3 +
`Peripheral data reverse 3
`Peripheral data 0
`Peripheral data.0 -
`Peripheral data 1 +
`Peripheral data 1 -
`Peripheral data2+
`Peripheral data 2 -
`Peripheral clock +
`Peripheral clock -
`Peripheral data 3 +
`Peripheral data 3 -
`Configuration bit 0
`
`Analog
`Analog
`Analog
`TTL
`TTL
`
`Red Video
`Green Video
`HSYNC
`VSYNC
`
`DDC2 SDA
`GND
`
`P18
`P40
`P42
`
`
`
`Pl,P4P7, Pio,
`P14,P19P21,
`P23,P26,P29,
`P32,P36P41
`
`Reset and Parity Error from console to ACM
`Reset and Parity Error from ACM to console
`video
`Video
`Video
`Horizontal Sync
`Wertical Sync
`
`GND
`
`DDC Data
`Ground
`
`F. Gu RE 21
`
`Samsung
`Ex. 1013 - Page 30
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 30 of 57 US 2001/0011312 A1
`
`TMDS
`TMDS
`CLK-T TMDS
`TMDS
`TMDS
`
`E5
`E6
`
`l
`E19
`
`
`
`
`
`
`
`
`
`
`
`
`
`ES"Elvis Hvar. E.
`Video capture port data or 1394
`LVDS or 1394
`Video capture port data or 1394
`LVDS or 1394
`VPCK-TPA+
`LVDS or 1394
`Video capture port data or 1394
`LVDS or 1394
`Video capture port data or 394
`VPCK/TPA-
`VESAP & D
`
`s
`
`VESAP & D
`veSAP&D
`VESA P&D
`VESAP & D
`
`
`
`
`
`Clock +
`clock
`Data -
`Data 1
`
`Configuration bit 2
`Configuration bit 3
`
`Reserved
`Reserved
`Reserved
`SW Luminance or reserved
`SW Chrominance or reserved
`
`
`
`GWKE 3 O
`
`Samsung
`Ex. 1013 - Page 31
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 31 of 57 US 2001/0011312 A1
`
`Data Rate
`
`6 x clock rate
`
`PD1
`
`Synch. To PCK
`
`6 x clock rate
`
`S ch. T O PC K
`6 x clock rate
`-
`Synch. To PCK
`6 x clock rate
`
`GND
`
`
`
`
`
`G GND
`Computer to Peripheral LVDS Data 3 -
`GND
`Computer to Peripheral LVDS Cock +
`Computer to Peripheral LVDS Clock -
`GND
`
`
`
`PD3 RTN
`10
`11
`PD3 -
`12
`PCKRTN
`13
`PCK -
`15
`16 PDRORTN
`PDRO -
`D R l R
`
`:
`22
`24
`
`PDR -
`PDR2 RTN
`PDR2 -
`DR3 RTN
`
`
`
`
`
`
`
`.
`Synch. To PCKR
`Fl
`Synch. To PCKR
`6 x clock rate Peripheral to Computer LVDS Data 1 -
`Peripheral to Computer LVDS Data 1 -
`GND
`Peripheral to Computer LVDS Data2
`
`Synch. To PCKR
`
`RTN
`PCK.-- Reverse Dir. Clock
`C
`EE
`TEHi Host to Peripheral
`TEP# Peripheral to Host
`
`
`
`6x clock rate
`
`Clock rate
`
`asynchronous
`asynchronous
`
`Peripheral to Computer LVDS Data 3 -
`GND
`GND
`Peripheral to Computer LVDS Clock +
`Peripheral to Computer LVDS Clock -
`Reset & Error signal
`Reset & Error signal
`
`PGu RE 3
`
`Samsung
`Ex. 1013 - Page 32
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 32 of 57 US 2001/0011312 A1
`
`PCK >>={ Receiver
`
`PCK
`
`th
`
`PDO S)-( : Receiver
`
`PDO
`
`t
`
`
`
`PO1
`
`PO2 B>)-(D PO2
`
`ro-GY)-( D-re
`
`F. Gu RE 32
`
`Samsung
`Ex. 1013 - Page 33
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 33 of 57 US 2001/0011312 A1
`
`
`
`Ty
`
`3" to 6"
`
`XX00 (PCI
`CBE
`PCI AD 1 seg. PCI AD 2" seg
`I
`HTD2
`Control bits
`Control bits
`PCID 2" seg.
`
`C2
`1001 (Control) 101 (Control)
`ontrol bits
`ontrol 2" seg.
`HTC2
`010 (Control
`Control bits
`Control 2" seg.
`
`HTC
`C
`
`X011
`
`111
`
`Resrd NOOP
`
`Void
`
`Gu RE 33
`
`Samsung
`Ex. 1013 - Page 34
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 34 of 57 US 2001/0011312 A1
`
`
`
`
`
`
`
`XO1 T 1111
`X001Control) X101Control)
`XX10 (PC)
`XX00 (PCI)
`1 nibble
`Control bits
`Control bits
`Control bits
`2" nibble CBE
`Other void
`Control 1seg. Control 2" seg.
`PCI AD 2" seg.
`3" to 6"
`PCIA/D 1 seg.
`-I-T-I-H TT
`1 nibble XX00
`XX10
`X001Control) X10 (Control) TX011
`BE
`Control bits
`Control bits
`Control bits
`PCD seg.
`PCD 2" seg.
`Control
`seg. Control 2" seg. Other Void
`
`
`
`
`
`Gu RE 3
`
`Samsung
`Ex. 1013 - Page 35
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 35 of 57 US 2001/0011312 A1
`
`
`
`F. Gu RE 3s
`
`Samsung
`Ex. 1013 - Page 36
`
`

`

`Patent Application Publication Aug. 2, 2001 Sheet 36 of 57 US 2001/0011312 A1
`
`
`
`' contro/ID (HMA or MD1.
`
`Gu Re 66
`
`Samsung
`Ex. 1013 - Page 37
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 37 of 57 US 2001/0011312 A1
`
`PD OPD2
`PDO
`1 controllid (PMA1 or PMD) FRAME IRDYAO: data seg.
`CBEO
`CBE:
`CBE2:
`2 control
`AD8
`AD6
`
`Data Segment
`t
`
`
`
`
`
`D
`
`E.
`
`:
`
`PD3
`O: PC; Other
`CIBE3A
`AMD24
`
`
`
`
`
`
`
`
`
`PC Ot hers
`
`:
`
`F (-uk,E 3
`
`Samsung
`Ex. 1013 - Page 38
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 38 of 57 US 2001/0011312 A1
`
`CPDOPD
`1"control D (ETD1 or PTD)
`1
`reserved
`reserved
`2"control
`DataSegment
`D8
`Do
`DataSegment
`D1
`D9
`"DataSegment
`D2
`D10
`Data Segment --
`D3
`D
`3 control D (HTD2 or PTD2)
`PAR (PCI)
`reserved
`4"control
`GNT,
`reserved
`2-Disegment
`D5
`D3
`E; 7
`D14
`
`
`
`PD3
`0: PC; Other
`datases.
`0:
`reserved
`reserved
`D24
`D16
`D25
`D7
`D26
`D18
`D27
`D19
`1:2"data seg. 0:PC; Other
`reserved
`Cat PARCM)
`D29
`
`
`
`
`
`G. WKE is 8
`
`Samsung
`Ex. 1013 - Page 39
`
`

`

`Patent Application Publication Aug. 2, 2001 Sheet 39 of 57 US 2001/0011312 A1
`
`33Mhz. PCI Read transaction:
`
`Samsung
`Ex. 1013 - Page 40
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 40 of 57 US 2001/0011312 A1
`
`
`
`33MhzPCI Write transaction:
`EPEMAEMA2 NOOP NOOP. EMD E-MD2 NOOP NOOP MDIBMD2 NOOP
`P> H NOOP NOOPPTC, NOOP NOOPINOOPPTC2 NOOP NOOPINOOP IPTC
`
`Samsung
`Ex. 1013 - Page 41
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 41 of 57 US 2001/0011312 A1
`
`
`
`
`
`
`
`d(PTC) Co. FC
`
`1:2 control ses.
`
`0: Control. Other
`
`SUSSIATA
`SUSCK
`NB Control Segment
`GRO Contro Segment. GROO GPO ().
`
`PHOLD:
`GPO(2)
`
`
`
`
`
`
`
`GPO(3) T
`
`
`
`Samsung
`Ex. 1013 - Page 42
`
`

`

`Patent Application Publication Aug. 2, 2001 Sheet 42 of 57 US 2001/0011312 A1
`
`packets without PC response :
`Peripheral to Host: PCT
`get (on XPBus) Control data
`PDO
`PD
`PD2
`:No PC
`0:
`0: Control
`control seg
`D(PTC)
`reserved
`reserved
`reserved
`PC Control Segment
`CPURST
`INTT
`reserved
`CPU Contro Segment
`CPU2Control Segment TNR
`NM
`A2OME
`
`PD3
`1: Other
`reserved
`reserved
`IGNNEE
`
`
`
`
`
`GPO 1 Control Segment
`GPO2Control Segment
`
`GPIO (0)
`GPIO(4)
`
`GPIO ()
`GPO (5)
`
`GPO (2)
`reserved
`
`GPO (3)
`PARCnt Packet
`
`Samsung
`Ex. 1013 - Page 43
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 43 of 57 US 2001/0011312 A1
`
`Peripheral to Host: PCI Master (on XPBus) Control data packets with PCI response:
`PDO
`PD1
`PD2
`0: PCI
`PERRE
`SERR:
`I reserved
`CPURST
`INIT
`reserved
`NTR
`NMI
`A20MH.
`INTR
`
`PCI Control segment
`CPU 1 Control Segment
`CPU 2"Control Segment
`
`PD3
`reserved
`reserved
`IGNNEA
`
`
`
`
`
`
`
`
`
`NB 1' Control Segment
`GPIO 1 Control Segment
`GPIO 2" Control Segment
`
`SUSCLK
`PIO (O
`GPIO (4
`
`SUSSTAT if
`GPO (
`GPIO (5
`
`PHOLDi
`GPIO (2
`resew
`
`GPO (3
`PAR (Cntl Packet
`
`FGu RE
`
`3
`
`Samsung
`Ex. 1013 - Page 44
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 44 of 57 US 2001/0011312 A1
`
`Peripheral to Host: PCI Master (on XPBus) Control data packets without PCI response:
`pDo
`PD
`PD2
`: C
`
`CPU l' Control Segment
`CPU 2"Control segment
`CPU 3' Control Segment
`
`
`
`
`
`
`
`
`
`
`
`r
`
`CPURST
`NTR
`SMIf
`
`CM PERRif
`
`Buffer Full #
`NM
`
`A20Mt.
`
`
`
`
`
`
`
`PHOLDi
`
`Guk E
`
`H
`
`Samsung
`Ex. 1013 - Page 45
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 45 of 57 US 2001/0011312 A1
`
`
`
`Host to Peripheral: Target Control data packet:
`O
`DTC1
`0: PCI Target
`PC Control Segiment
`SERRE
`CMI Control Segment
`uffer Fu i
`CPU 1 Control Segment
`
`REQA
`CMI REQi
`
`HTC2 is reserved for future use.
`
`FGu RE '9
`
`Samsung
`Ex. 1013 - Page 46
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 46 of 57 US 2001/0011312 A1
`
`Host to Peripheral: Master Control data packet:
`
`
`
`CPU Control Segment
`
`HMC2 is reserved for future use.
`
`Gu RE
`
`e.
`
`Samsung
`Ex. 1013 - Page 47
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 47 of 57 US 2001/0011312 A1
`
`Host PCI Bus Signal (50 pins)
`Name
`Type
`Pins
`AD(31:0
`TS
`32
`C/BE3:Oil
`
`FRAME
`
`TROYi
`
`STS
`
`DEVSELi
`
`STS
`
`| 1
`
`STOPi
`
`STS
`
`PAR
`
`TS
`
`1
`
`Input
`
`Input
`
`STS
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`1
`
`toCK#
`
`EbSEL#
`
`FERR#
`
`PCCK
`
`Description
`Multiplexed Address/Data. AD is driven to a valid state when GNTH is asserted
`Multiplexed Command/Byte Enables. For a two-address transaction, 1" address
`phase carries the command, and the 2" address phase carries the transaction type.
`C/BE is driven to a valid state when GNTi is asserted.
`Indicates beginning and duration of a PCI transaction. When the bus is idle,
`FRAMEii is driven to High for 1 cycle. A pull-up resistor sustains STS signal.
`Initiator Ready. RDY# is driven High for 1 cycle if bus is idle, and the state is
`sustained by a pull-up resistor.
`Target Ready. When bus is idle, TRDY# is driven High for 1 cycle if bus is idle.
`An external pull-up resistor sustains STS signal.
`Device Select. DEVSEL# is asserted by target to indicate it is ready to accept the
`transaction. HIC decodes address of a transaction to decide the need to assert
`DEVSEL#. As an initiator, HIC waits for 5 cycles to detect assertion of
`DEVSEL# by the target; otherwise HIC terminates with a master abort.
`DEVSEL# is driven High for 1 cycle when bus is idle, and the state is sustained
`by a pull-up resistor.
`Target request to stop transaction. There are 3 cases:
`STOPil, TRDYi & DEVSELi asserted: disconnect with data transfer
`Only STOP# & DEVSEL# asserted: request initiator to retry later
`Only STOP# asserted: target abort
`STOP# is driven High for 1 cycle when bus is idle, and the state is sustained by a
`pull-up resistor.
`Even parity for 36 bits of AD & C/BE#. PAR is sent one cycle after address or
`data is valid. In write transaction, initiator sends PAR one cycle after write data is
`valid. In read transaction, target sends PAR one cycle after read data is valid.
`Initiator request lock on target downstream. LOCK# is asserted 1 clock cycle
`after address phase by an initiator wanting to perform an atomic operation that
`take more than one transaction to complete. HIC passes the LOCK request to the
`secondary PCI bus. HIC does not drive LOCK# or propagate LOCK# upstream.
`Chip Select for Type 0 configuration access. During a Type 0 configuration
`transaction, the initiator asserts IDSELi during the address phase to select HIC.
`HIC responds by asserting DEVSEL#.
`Data Parity Error on all transactions except Special Cycle. PERR# is driven one
`clock cycle after PAR PERR# is asserted by target during write transactions, and
`by initiator during read transactions.
`System. Error. HIC asserts SERRif under the following conditions:
`Address parity error, Secondary bus SERRA asserted,
`Posted write transaction: data parity error on target bus, Posted write transaction
`discarded, Master abort, Target abort
`Delayed read or write transaction discarded, and
`Delayed transaction master timeout.
`Request for bus. If a target retry or disconnect is received in response to initiating
`a transaction, HIC deasserts REQ# for at least 2 cycles before asserting it again.
`Bus is granted to HIC. HIC can initiate transaction if GNThis asserted and the
`bus is idle. When HIC is not requesting bus and GNT# is asserted, HIC must
`drive AD, CBE, and PAR to valid logic levels.
`Input indicating clock status. HIC can request the central clock resource to start,
`speed up or maintain the PCI clock. There are 3 clocking states:
`Clock running, Clock about to stop/slow down, and Clock stopped/slowed.
`PCI Clock. All inputs are sampled on the rising edge of PCICK. Frequency range
`from 0 to 33Mhz.
`
`
`
`
`
`FGu RE I)
`
`Samsung
`Ex. 1013 - Page 48
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 48 of 57 US 2001/0011312 A1
`
`XPBus Signals
`
`
`
`
`
`
`
`
`
`PCKRt
`PCNR
`
`LVDS outputs
`LVDs input 2
`8
`
`Peripheral Data Differential Signal Pair output to XPBus
`Peripheral Clock Differential Signal Pair input fromxPBus
`Peripheral Data Differential signal Pair input fromXPBus
`Peripheral Control Differential Signal Pair Input from XPBus
`
`
`
`
`
`
`
`
`
`Samsung
`Ex. 1013 - Page 49
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 49 of 57 US 2001/0011312 A1
`
`XIS Bus Video Port Signals
`
`
`
`LVDS Output
`
`Description
`Video Port Clock Differential Signal Pair Input, 2x Video clock rate
`Video Port Data Differential Signal Pair input, 10 bit/clock period
`
`FGu RE 41
`
`Samsung
`Ex. 1013 - Page 50
`
`

`

`Patent Application Publication Aug. 2, 2001 Sheet 50 of 57 US 2001/0011312 A1
`
`Video Port Signals
`Name
`Type
`Output
`
`
`
`
`
`Video Port Data Output
`
`VRDY
`
`Output
`
`1
`
`Video Source Ready
`
`Samsung
`Ex. 1013 - Page 51
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 51 of 57 US 2001/0011312 A1
`
`Flash Memory Interface Signals
`Name
`Type
`A180
`output
`DQ70
`IO
`CEF.
`To
`| WEF:
`O
`OEH
`o
`writ
`To
`
`
`
`Pins
`19
`8
`1
`1
`1
`
`Description
`Address for up to 512Kx 8 Memory
`Data input/Output
`Chip Enable
`Write Enable
`output Enable
`write protect
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Samsung
`Ex. 1013 - Page 52
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 52 of 57 US 2001/0011312 A1
`
`Test Port (JTAG) Signals
`
`
`
`Samsung
`Ex. 1013 - Page 53
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 53 of 57 US 2001/0011312 A1
`
`CPU Signals
`Name
`CPURST
`FERR:
`IGNNEH
`NIT
`INTR
`A2OME
`NMI
`SMIt
`
`Type
`IoD
`I
`OD
`oD
`TOD
`OD
`OD
`OD
`
`Pins
`1
`1
`1
`1
`1
`1
`1
`1
`
`Description
`CPUReset and PCIRSTH
`Numeric Coprocessor Error
`ignore Numeric Exception
`Initialization
`CPUInterrupt, Pentium: active high, PI active low
`Address 20 Mask, Keyboard Interface
`Non-Maskable Interrupt
`System Management Interrupt
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`F. Gu R. S3
`
`Samsung
`Ex. 1013 - Page 54
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 54 of 57 US 2001/0011312 A1
`
`North Bridge Signals
`Type
`
`
`
`
`
`Pins
`
`1
`
`Description
`Suspend Clock from South Bridge. 32.768Khz for maintenance of
`DRAMRefresh.
`Suspend Status Planel
`PCIHold
`PCI Hold Acknowledge
`
`
`
`
`
`
`
`Samsung
`Ex. 1013 - Page 55
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 55 of 57 US 2001/0011312 A1
`
`GPIO Signals
`
`
`
`GPIO(1)
`GPIOI7:2)
`
`o
`o
`to
`
`
`
`1
`1
`6
`
`CPUSTPH-CPU Clock stop (optional)
`PC STPl - PC Clock stop (optional)
`General Purpose input/output signals
`
`
`
`Samsung
`Ex. 1013 - Page 56
`
`

`

`Patent Application Publication Aug. 2, 2001 Sheet 56 of 57 US 2001/0011312 A1
`
`ERROR/RESET Signals
`
`
`
`Signal uses for: Reset from Host, Parity error for PIC transmission, &
`no connect detection
`Signal uses for: Reset from Peripheral, Parity error for HIC
`transmission, No connect detection
`
`Samsung
`Ex. 1013 - Page 57
`
`

`

`Patent Application Publication
`
`Aug. 2, 2001 Sheet 57 of 57 US 2001/0011312 A1
`
`Powerforound/OSC input Signals
`
`VCC (LVDS)
`vcC(VP)
`vccoPCI)
`vccFlash)
`GND (core)
`GND (LVDS)
`GND (PC)
`GND (Flash)
`Reserved
`
`
`
`2
`1
`2
`1
`2
`2
`2
`1
`
`LVDs VCC-33v
`video port: all output signals, vCC =3.3v
`PCIVCC=5v tolerant or 3.3v
`Flash memoryvcc=sv tolerant or 3.3v
`core ground
`LVDS ground
`PCI ground
`Flash memory ground
`Reserved pins
`
`
`
`
`
`
`
`
`
`Samsung
`Ex. 1013 - Page 58
`
`

`

`US 2001/0011312 A1
`
`Aug. 2, 2001
`
`COMMUNICATION CHANNEL AND INTERFACE
`DEVICES FOR BRIDGING COMPUTER
`INTERFACE BUSES
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`0001. This application claims any and all benefits as
`provided by law of U.S. Provisional Application No. 60/083,
`886 filed May 1, 1998 and of U.S. Provisional Application
`No. 60/092,706 filed on Jul 14, 1998.
`0002 This application is being filed concurrently with the
`application of William W. Y. Chu for “Personal Computer
`Peripheral Console With Attached Computer Module”, filed
`on Sep. 8, 1998 and incorporates the material therein by
`reference
`
`BACKGROUND OF THE INVENTION
`0003. The present invention generally relates to computer
`interfaces. More specifically, the present invention relates to
`an interface channel that interfaces two computer interface
`buses that operate under protocols that are different from that
`used by the interface channel.
`0004 Interfaces coupling two independent computer
`buses are well known in the art. A block diagram of a
`computer System utilizing Such a prior art interface is shown
`in FIG. 1. In FIG. 1, a primary peripheral component
`interconnect (PCI) bus 105 of a notebook PC 100 is coupled
`to a secondary PCI bus 155 in a docking system 150 (also
`referred to as docking station 150) through high pin count
`connectors 101 and 102, which are normally mating con
`nectors. The high pin count connectors 101 and 102 contain
`a sufficiently large number of pins so as to carry PCI bus
`signals between the two PCI buses without any translation.
`The main purpose for interfacing the two independent PCI
`buses is to allow transactions to occur between a master on
`one PCI bus and a target on the other PCI bus. The interface
`between these two independent PCI buses additionally
`includes an optional PCI to PCI bridge 160, located in the
`docking Station 150, to expand the add on capability in
`docking station 150. The bridge 160 creates a new bus
`number for devices behind the bridge 160 so that they are
`not on the same bus number as other devices in the System
`thus increasing the add on capability in the docking Station
`150.
`0005. An interface such as that shown in FIG. 1 provides
`an adequate interface between the primary and Secondary
`PCI buses. However, the interface is limited in a number of
`ways. The interface transferS Signals between the primary
`and secondary PCI buses using the protocols of a PCI bus.
`Consequently, the interface is Subject to the limitations
`under which PCI buses operate. One such limitation is the
`fact that PCI buses are not cable friendly. The cable friend
`liness of the interface was not a major concern in the prior
`art. However, in the context of the computer System of the
`present invention, which is described in the present inven
`tor's (William W.Y. Chu's) application for “Personal Com
`puter Peripheral Console With Attached Computer Module”
`filed concurrently with the present application on Sep. 8,
`1998 and incorporated herein by reference, a cable friendly
`interface is desired for interfacing an attached computer
`module (ACM) and a peripheral console of the present
`invention. Furthermore, as a result of operating by PCI
`
`protocols, the prior art interface includes a very large
`number of Signal channels with a corresponding large num
`ber of conductive lines (and a similarly large number of pins
`in the connectors of the interface) that are commensurate in
`number with the number of signal lines in the PCI buses
`which it interfaces. One disadvantage of an interface having
`a relatively large number of conductive lines and pins is that
`it costs more than one that uses a fewer number of conduc
`tive lines and pins. Additionally, an interface having a large
`number of conductive lines is bulkier and more cumberSome
`to handle. Finally, a relatively large number of Signal chan
`nels in the interface renders the option of using differential
`Voltage Signals less viable because a differential Voltage
`Signal method would require duplicating a large number of
`Signal lines. It is desirable to use a low Voltage differential
`Signal (LVDS) channel in the computer System of the present
`invention because an LVDS channel is more cable friendly,
`faster, consumes less power, and generates leSS noise,
`including electromagnetic interferences (EMI), than a PCI
`channel. The term LVDS is herein used to generically refer
`to low Voltage differential signals and is not intended to be
`limited to any particular type of LVDS technology.
`
`BRIEF SUMMARY OF THE INVENTION
`0006 The present invention overcomes the aforemen
`tioned disadvantages of the prior art by interfacing two PCI
`or PCI-like buses using a non-PCI or non-PCI-like channel.
`In the present invention, PCI control Signals are encoded
`into control bits and the control bits, rather than the control
`Signals that they represent, are transmitted on the interface
`channel. At the receiving end, the control bits representing
`control signals are decoded back into PCI control signals
`prior to being transmitted to the intended PCI bus.
`0007. The fact that control bits rather than control signals
`are transmitted on the interface channel allows using a
`Smaller number of Signal channels and a correspondin