2,799,449
`A. M., TURNG ETA
`July 16, 1957
`DATA STORAGE TRANSFER MEANS FOR A DIGITAL COMPUTER
`Siled April 23, 195l
`4. Sheets-Sheet l
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`2,799,449
`A. M. TURNG E.T A.
`July 16, 1957
`DATA STORAGE TRANSFER MEANS FOR A DIGITAL COMPUTER
`Siled April 23, 1951
`4. Sheets-Sheet 2
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`2,799,449
`A. M. TURING ETAL
`July 16, 1957
`DATA STORAGE TRANSFER MEANS FOR A DIGITAL COMPUTER
`Filed April 23, 195l.
`4. Sheets-Sheet 3
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`2,799,449
`A. M. TURING ETAL
`July 16, 1957
`DATA STORAGE TRANSFER MEANS FOR A DIGITAL COMPUTER
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`Filed April 23, 195l.
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`4. Sheets-Sheet 4
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`United States Patent Office
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`2,799,449
`Patented July 16, 1957
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`O
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`2
`the specification of co-pending application Serial No.
`202,615, now Patent No. 2,686,632, granted August 17,
`1954.
`The present invention will be more readily understood
`if a concrete example is considered. Consider, therefore,
`a computing engine working with a major cycle of 32
`minor cycles each of which comprises 40 digits, suppose
`such a machine has 256 possible sources of words to
`be transferred of which 32 are possible instruction sources,
`256 possible destinations for words to be transferred and
`16 possible circuits through which words have to pass
`during the transfer and in which arithmetical or logical
`operations are performed on the words. These circuits
`will be referred to hereinafter as function boxes. Further
`suppose that such an engine has to operate with instruc
`tion words of the following kind:
`“Transfer words from source a and source b through
`function box c to destination d and take the next instruc
`tion from source e."
`In the engine specified the instruction word will require
`8 binary digits to define each of a, b and d, 4 binary digits
`to define c and 5 binary digits can define e; that is to say
`33 binary digits in all. This leaves only 7 binary digits
`to define the timing of the transfer since each instruction
`word comprises altogether 40 digits.
`Now it has previously been proposed to time trans
`fers by specifying the first and last minor cycles included
`in the transfer. In the engine now being considered
`this would require two timing numbers each of five binary
`digits and clearly this method of timing the transfer is
`not possible because only 7 digits are left. We propose
`to overcome this difficulty in this particular case by using
`5 of the 7 digits as a timing number and the remaining 2
`digits as a "characteristic' code which determines that the
`transfer shall be one of four predetermined species. For
`example, the four predetermined species of transfer may
`be the four transfers specified below. In these transfers
`the minor cycle in which the current instruction is set
`up is counted as minor cycle zero and the timing number
`S
`(1) A transfer which starts in minor cycle one and
`continues for (n+1) minor cycles, the next instruction
`being set up in minor cycle (n+2).
`(2) A transfer which starts in minor cycle one and
`continues for (n-1-33) minor cycles, the next instruction
`being set up in minor cycle (n-1-34).
`(3) A transfer which takes place in minor cycle (n+1)
`(that is to say one that lasts for only one minor cycle
`after a waiting time of n minor cycles), the next instruc
`tion being set up in minor cycle (n-2).
`(4) A transfer which takes place in minor cycle (n+1),
`the next instruction being set up in minor cycle 33,
`It will be noticed that the timing number is not always
`used in the same way; thus in transfers 1 and 2 it deter
`mines the end and incidentally the duration of the trans
`fer while in transfers 3 and 4 it determines the start of
`the transfer which lasts for only one minor cycle.
`According to the present invention, therefore, a method
`of transferring information from one part of a digital
`computing engine to another part thereof, comprises the
`steps of setting up a transfer route in accordance with
`
`1.
`2,799,449
`DATA STORAGE TRANSFER MEANS FOR A
`DIGITAL COMPUTER
`Alan Mathison Turing, Wilmslow, Donald Watts Davies,
`Southsea, and Michael Woodger, Ashtead, England, as
`signors to National Research Development Corpora
`tion, London, England
`Application April 23, 1951, Serial No. 222,366
`Claims priority, application Great Britain May 4, 1950
`5 Claims. (C. 235-61)
`This invention relates to electrical digital computing
`engines which employ stores in which stored words (num
`bers and instructions) are incident at the output terminals
`of the stores sequentially so that if a particular word, or
`sequence of words, is to be read out the instants of open
`ing and closing gates connected to the output terminals
`must be exactly defined by the circuit controlling the
`transfer of the word, or sequence of words, read out.
`A convenient form of such a storage device is the well
`known acoustic delay line which consists essentially of a
`straight cylindrical tube filled with mercury and with a
`piezo-electric crystal at each end. If an electrical pulse
`is applied to the crystal at one end of the line an ultrasonic
`wave travels down the line at the velocity of sound in
`mercury and at the other end is reconverted into an elec
`trical pulse by the other crystal. This new pulse may be
`amplified, reshaped and fed back to the input crystal and
`in this way the pulse or a whole pattern of pulses may be
`preserved indefinitely.
`Another example of such a storage device is the mag
`netic recording store in which parts of a moving ferro
`magnetic member are magnetised to record digits repre
`senting numbers in the binary scale of notation. Mag
`netic stores of this kind are described, for example, in
`the specifications of co-pending applications Serial Nos.
`146,445, now Patent No. 2,652,554, granted September 15,
`1953, 146,446, now Patent No. 2,734,186, 195,042, now
`Patent No. 2,700,555 and 196,776, now Patent No. 2,694,-
`192.
`In digital computing engines calculations are made by
`transferring words from one part of the machine to an
`other and it will be appreciated that with a storage device
`of the kind described above the words are continuously
`circulating in the store and the transfers have to be care
`fully timed in order to transfer the right word or words.
`The present invention is concerned with methods of trans
`ferring words from one part of a computing engine to an
`other part and to apparatus for effecting such methods.
`The invention is particularly concerned with the timing
`of such transfers.
`The invention does not, of course, apply to the trans
`fer of information from a store in which any word can
`be read out at any time, such a store is the well-known
`Williams' tube.
`The terms used in this specification and the Symbols
`used in the accompanying drawings are well-known to
`those skilled in this art and are defined and explained in
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`address signals and timing the transfer in accordance with
`a timing number and a characteristic code of at least two
`digits which determines that the transfer shall be one of
`a number of predetermined species of transfer.
`In a preferred embodiment a single timing number n
`is used in conjunction with a two digit characteristic code
`which determines that the transfer shall be one of the
`following species:
`(1) A transfer which starts immediately following the
`setting up of a transfer route defined by the instruction
`word and continues for (n-1) minor cycles.
`(2) A transfer which starts immediately following the
`setting up of a transfer route defined by the instruction
`word and continues for a major cycle and (n-1) minor
`cycles.
`(3) A transfer which lasts for one minor cycle and
`commences after a wait of n minor cycles after the setting
`up of a transfer route defined by the instruction word;
`and
`(4) A transfer which lasts for one minor cycle and
`commences after a wait of n minor cycles after the
`setting up of a transfer route defined by the instruction
`word and in which the next instruction is set up at some
`predetermined time which is independent of the timing
`number, e. g. after a wait of one major cycle after the
`setting up of a transfer route defined by the instruction
`word.
`In the case of species 1, 2 and 3 the next instruction
`may be set up at a predetermined time which does depend
`on the timing number and in the particular embodiment
`described below the next instruction is set up in the minor
`cycle following the end of the transfer. In all cases the
`setting up of the next instruction may be delaved by a
`discriminating trigger in accordance with well known
`methods of operating these machines.
`The four species of transfer specified above will be
`found to be very suitable for practical computations and
`for convenience these species 1, 2, 3 and 4 will be here
`inafter referred to as immediate, long, deferred and serial
`respectively.
`A particular embodiment of the invention comprising
`a computing engine having the characteristics specified
`in the example set out above will now be described with
`reference to the accompanying drawings in which:
`Figure 1 shows the circuit arrangement for routing
`transfers in a machine according to the invention;
`Figure 2 shows a block diagram with legends of the
`circuit arrangement for routing transfers in a machine
`according to the invention;
`50
`Figure 3 shows a circuit for timing transfers in a ma
`chine according to the invention and
`Figure 4 shows an alternative circuit for timing trans
`fers in a machine according to the invention.
`In Figure 1 TN is a typical storage element and BN
`is a typical function box. For example TN may be a
`long delay line with its usual circulating path and BN
`may be an adder.
`Outputs may be taken from
`TN to common lines or buses H1, H2 and IN through
`gates 1, 2 and 3 respectively. The buses H1 and H2
`(called highway 1 and highway 2) are common to all
`the sources in the engine and to all the inputs of the
`function boxes but include between the sources and the
`function boxes two gates 4 and 5 respectively. These
`gates are conditioned by a trigger TT in the timing cir
`65
`cuit to be hereinafter described. The tank TN also com
`prises the usual destination gates 6 and 7 which are con
`ditioned by destination pulses DN applied through a
`further gate 8 which is also conditioned by TT. The
`destination gate 6 is fed from a common line or bus H
`(called highway) which is common to all destination
`gates and also to output gates from the function boxes
`such as the gate 9 which is conditioned by a pulse FN.
`The bus IN is common to the 32 instruction sources
`and feeds a short tank INST which is arranged to contain
`
`2,799,449
`4.
`the next instruction to be obeyed at the end of the trans
`fer, When the timing circuit shown in Figure 3 is con
`sidered it will be seen that the instruction in the short
`tank NST at the end of the transfer flows into the con
`trol circuit to set up and time the next transfer. Conse
`quently it is arranged in the progress of the computation
`that the instruction occurring in INST at the end of
`the transfer is the next instruction to be obeyed. There
`are two exceptions to this rule which will become clear
`when the control circuit has been studied. One relates
`to the effect of the discriminating trigger D in Figure 3
`which when operated causes not the instruction in INST
`at the end of the transfer but the next following instruc
`tion to flow into the control unit. The other exception
`occurs when a serial transfer is made, in which case the
`next instruction is taken from INST one whole major
`cycle later. The gate 3 is conditioned by a pulse ISN.
`The instruction word ordering the transfer will con
`tain, as already explained, digits which will be decoded
`to open two source gates such as gates 1 and 2, a destina
`tion gate such as gate 6, a function box such as gate 9
`and a next instruction gate such as gate 3. There will be
`32 possible instruction scurces and the five digits specify
`ing the next instruction source in the instruction word
`will be staticised and applied to a tree 10 of order five,
`the 32 outputs of which will condition the gates such as
`gate 3 as indicated in the drawing.
`Similarly three other trees each of order eight act as
`follows. The first source address digits P1-P8, are
`staticised and sent to the first source address tree (having
`256 output lines) which decodes the digits and gives a
`signal on the output line which corresponds to the digits
`P1-P8; for example, if these digits are 10010100 (the
`least significant digit being in the left-hand position),
`corresponding to first source address No. 41, then the
`corresponding output line will be excited, and this will
`open the gate such as the gate 1 corresponding to storage
`tank such as TN No. 41. In exactly the same way the
`second source address digits P9-P16 are staticised and
`sent to a tree of order eight, one of the 256 outputs of
`which is used to open a second source gate such as the
`gate 2, and the destination address digits P17-P24 are
`staticised and sent to a tree of order eight, one of the 256
`outputs of which is sent to a destination gate such as the
`gate 8, so that when the timing trigger TT, referred to
`above, is put on, a gate such as the gate 6 is opened and
`a gate such as the gate 7 closed and the word emerging
`from a function box such as the function box BN is
`allowed to flow into a destination tank such as the tank
`TN. In the same way the function digits P25-P23 are
`staticised and sent to a tree of order four, one of the
`sixteen outputs of which is used to open a function gate
`such as the gate 9 to allow the result of the operation
`which has taken place in the function box to flow through
`a destination gate such as the gate 6, opened as pre
`viously described, into a destination tank Such as the
`tank TN. Staticisors and trees are well known in the
`art and are described in U. S. Patent No. 2,686,632,
`aforesaid. For the sake of clarity these trees are omitted
`from the drawing.
`During the set-up minor cycle the source, destination,
`function box and next instruction gates are conditioned
`and the circuit is ready for a transfer to take place. How
`ever, owing to the presence of the gates 4, 5 and gates
`such as 8 the transfer does not take place until the trig
`ger TT is put on and ends when the trigger TT goes off.
`The present invention is shown diagrammatically in
`Figure 2. The instruction word to be obeyed flows into
`the temporary instruction store 102 which is preferably
`tapped at intermediate points so that parts of the instruc
`tion words may be staticised by the staticisor 104 be
`fore the whole word passes to the control circuit proper.
`A suitable staticisor is fully described in the U. S. Patent
`No. 2,686,632 aforesaid with reference to Figure 12 of
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`5
`the drawings, and in the text. The use of a tapped delay
`line is described below with reference to Figure 4 of
`the present specification.
`Among the digits of the instruction word that are
`staticised are the digits of the characteristic code which
`are here referred to as a and B. These two staticised
`signals are passed to the characteristic code interpreter
`106.
`The output from the temporary store 102 passes to
`a double counting circuit 108 which gives an output pulse
`Z at the end of the set-up minor cycle and another output
`pulse N at the end of the nth minor cycle after the set
`up minor cycle, where n is the value of the timing num
`ber. The counting circuit is arranged so that both Z.
`and N occur again each major cycle later than their
`first appearance unless in the meanwhile the counting
`circuit has been reset.
`The pulses Z and N are arranged indirectly, and not
`necessarily respectively, to put on and off a timing trig
`ger 110 which gives the signal TT in Figure 1 and is
`shown as TT in Figures 3 and 4. The way in which the
`pulses Z and N put the timing trigger 110 on and off is
`controlled by the characteristic code interpreter 106 in
`a way which is different for different permutations of
`values of the characteristic digits c and 3 supplied to
`the interpreter 166, and the result is that the timing trig
`ger goes on and off at the exact instants to give one of
`the four species of transfers described above correspond
`ing to the values of ox and 8 at the time.
`Two forms of the present invention are described be
`low. That shown in Figure 3 employs a minor-cycle
`counter in which the negation of the timing number is
`set up to begin with, and in which one is added to this
`negation of the timing number every minor cycle until
`the result becomes 2, when an N pulse occurs. A minor
`cycle counter is also employed in which the negation of
`zero, i. e. 1 111, is set up, and in which one is added to
`this negation every minor cycle. Whenever the result
`becomes 2, a Z pulse occurs. These N and Z pulses
`recur every major cycle. It will also become apparent
`that an N pulse occurs at the end of the nth minor cycle
`after the set-up minor cycle (n being the timing number),
`and a Z pulse occurs at the end of the set-up minor
`cycle. This embodiment also uses an un-tapped tem
`45
`porary instruction store. On the other hand the em
`bodiment shown in Figure 4 uses a tapped temporary
`instruction store (see the chain of delays 55-66) and
`separate counters for the generation of the Z and N
`pulses. These counters each comprise a cascade of trig
`gers counting in a scale of 32 (the number of minor cycles
`in a major cycle). The Z counter starts with a trigger
`setting of zero (which yields a Z pulse) and the N
`counter starts with a trigger setting corresponding to
`the negation of the timing number.
`The two embodiments illustrated also differ in the
`means employed in the characteristic code interpreter to
`modify the action of the Z and N pulses on the timing
`trigger in accordance with the current values of or and B.
`The way in which Figure 2 is related to the other fig
`ures, and the construction of the elements of Figure 2
`are as follows. The temporary instruction store, 102, is
`the same as the store INST in Figures 1 and 3, and the
`store 55-60 in Figure 4. A suitable store would be the
`well-known acoustic delay line, and those skilled in the
`art are acquainted with many other useful devices for
`storing such elements.
`The staticisors, 104, have been described above; in
`Figure 3 the element STA is a staticisor, and in Figure 4
`the triggers I6 to 140 and their associated gates provide
`another such staticisor. A typical form of tree is de
`scribed in, for instance, U. S. Patent No. 2,686,632
`aforesaid, and a typical tree in the present invention is
`the tree 10 in Figure 1. Four other trees, as explained
`above, influence gates like the gate 1, the gate 2, the
`gate 8 and the gate 9 in Figure 1.
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`6
`The characteristic code interpreter, 106, corresponds
`to that portion of Figure 3 below the line XX, with the
`exception of the timing trigger TT. In Figure 4, the
`characteristic code interpreter corresponds to the ele
`ments 75 to 100 with the triggers D, E, I, L., X, and Y,
`the switch S, and the connections therebetween.
`The double counter, 108, corresponds to the elements
`20 to 26 of Figure 3 together with triggers C and H, the
`delay line CO and their interconnections; it also corre
`sponds to the triggers N1 to N5 and Z1 to Z5 together
`with their associated gates and interconnections in Fig
`ure 4.
`The trigger 110 is represented by the trigger TT in
`both Figures 3 and 4. This trigger gives the TT pulse
`which opens gates 4 and 5 and gates such as the gate 8
`in Figure 1.
`The circuit shown in Figure 3 may conveniently be
`considered in two parts, the part above the line XX being
`mainly concerned with timing of the operation of the
`circuit in accordance with the timing number and the
`part below the line XX being mainly concerned with the
`interpretation of the two characteristic digits in the in
`struction word. At this stage it is necessary to consider
`the actual position of the digits in the instruction word.
`The first 33 digits may be used for indicating the first
`and second source, the destination, the function and the
`next instruction source. The characteristic digits will be
`P34 and P40 and the timing number will be the five digits
`P35 to P39. The characteristic digits at P34 and P40
`will be referred to as or and 8 respectively.
`The digits of the instruction word are allocated as
`follows:
`
`First Source: P1-P8 --------------------------- 8
`Second source: P9-P16 ------------------------ 8
`Destination: P17-P24 ------------------------- 8
`Function: P2S-P28---------------------------- 4
`Next instruction source: P29-P33 --------------- 5
`Characteristic: P34 and P40 -------------------- 2
`Timing number: P35-P39 ---------------------- 5
`
`Total --------------------------------- 40
`
`The characteristic code for determining the species of
`transfer to be effected will be as follows:
`
`Species of Transfer
`--------
`Nanne
`
`No.
`
`8
`
`Duration Transfer Next set
`of wait
`in minor
`up in
`in minor cycle(s)
`minor
`cycles
`cycle
`
`mined late-
`Long--------
`Defered.----
`Serial-...--
`
`O
`O
`
`O
`1.
`O
`1.
`
`1 to --1
`O
`O 1 to --33
`--
`--1
`
`--2
`n-34
`n-2
`33
`
`In this table the current set up occurs in minor cycle 0.
`This programme will be slightly modified if the trigger
`D in Figure 3 is operated because then the next set-up
`will be in the minor cycle following the minor cycle set
`out in the table above. This will become clear when
`the operation of the circuit is explained. The trigger D
`is of course the discriminating trigger and its function
`is to modify the course of the computation when a cer
`tain criterion is reached. Its use is well-known to those
`skilled in preparing programmes for computing engines
`and, therefore, need not be set out at length here.
`It is convenient to consider the circuit in Figure 3 by
`assuming first that the gate 41 produces a pulse, called
`SN and indicated as such in the drawing at P40. That
`this is so, will be seen when the circuit has been fully
`explained.
`Normally SN will stimulte the trigger SU through the
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`2,799,449
`8
`The two numbers represented by P29 to P34 and P35
`half delay 11 at P40%. If, however, D has been stimu
`to P40 are very important, for each increases by one
`lated during the previous transfer SN is stopped at the
`every minor cycle, until it becomes 32, when a "one"
`gate 12. The trigger E is set by SN at P1 through the
`digit appears in the P34 or P40 position, as the case may
`unit delay 13 and since D has been stimulated is not
`be. This digit is gated out at one of the gates 24 or
`reset at P29 owing to the inhibited gate 14. Thus the
`2S. in the next minor cycle the digit is prevented from
`next P40 applied to the gate 15 sets the trigger SU and
`repeating this by the inhibiting gate 22. The P34 pulse
`incidentally puts D off. The next P29 puts E off, thus,
`puts on a trigger H which allows the next P40 through
`as stated above, stimulating D has the effect of delaying
`the gate 26 and is then put off in the following P29.
`the putting on of the trigger SU by one minor cycle.
`Thus the upper part of the circuit in Figure 3 generates
`It will be explained below that the trigger SU is on for
`from the timing number part of the instruction word
`one minor cycle during which the incoming signal is set
`two pulses occurring at N and Z which pass to the lower
`up. The consequence of stimulating the trigger D there
`part of the circuit. These pulses N and Z are P40 pulses
`fore is to delay the set-up of the next instruction by one
`and are repeated at each major cycle until the next set
`minor cycle.
`When SU is put on it conditions the gate 16 through
`tip occurs.
`it will be seen, by considering the signal at the point
`the unit delay 17 and is thus put off in the next P40/,
`(iv), that the first Z pulse occurs at the end of the set-up
`by P40 applied through the gate 16 and the haif unit
`minor cycle so that Z pulses occur in minor cycles 0,
`delay 18. During the minor cycle in which SU is on the
`32, 64 etc. until the next set-up. The N pulses are n
`gate 19 is conditioned and the instruction in the tank
`minor cycles behind the Z pulses. Of course, when the
`INST (which is of course the tank INST shown in Fig
`timing number is zero the pulses N and Z coincide in
`ure 1), flows to the staticiser STA which decodes the
`minor cycles 0, 32, 64, etc.
`two source codes, the destination code, the function code
`The lower part of the circuit in Figure 3 which is con
`the next instruction source and conditions the correspond
`cerned with the interpretation of the characteristic code
`ing gates such as those shown at 1, 2, 8, 9 and 3 in Fig
`pulses a and 3 may now be considered. The output from
`ure 1.
`this circuit consists of a gate pulse from the trigger TT
`Staticisors are very well known in the art, and the
`operational details of a suitable staticisor may be found
`which conditions the gates 4 and 5 and the gate such as
`8 shown in Fig. 1 for the purpose of timing the transfer,
`in U. S. Patent No. 2,686,632 aforesaid.
`and P40 pulses at SN to operate the upper part of the
`STA has, of course, been cleared by the same pulse
`circuit in Fig. 3 as already explained. It will be assumed
`that puts the trigger SU on. In addition STA staticises
`at first that the switch S is closed so that the part of the
`the a and g digits of the characteristic code. The instruc
`circuit across this switch may be neglected and further
`tion word also flows to a gate 20 which is conditioned
`that at the beginning of the set-up minor cycle the trig
`by a trigger C which is on from P34% to P394. Thus
`only the timing number (i. e. digits P35 to P39) passes
`gers TT, I and L are off. When the circuit has been ex
`plained it will be appreciated that this last condition
`the gate 20. This timing number is negated at the gate
`automatically obtains. The trigger D will also be as
`2 because SU is on during the set-up cycle. That is to
`say, the digits of the timing number are replaced by their
`sumed off.
`If it has been put on its effect will be as
`complements, so that if the timing number 11 is 01 011,
`described above.
`The effect of all the possible combinations of the
`the output of gate 21 is 10100. For if a timing number
`characteristic code may be considered in order.
`digit at a certain time is one, then the gate 21 is in
`hibited by it, so that the gate 21 gives a zero output. If,
`Consider first an "immediate' transfer in which as:0
`and 6=0. The Z pulse at the end of minor cycle 0 puts
`on the other hand, the timing number digit is zero, then
`the trigger TT on at P40% in this minor cycle through
`the gate 21 is open and the output from the trigger SU
`the gates 27, 28 the switch S and the half delay 29. The
`is allowed to get through, giving a "one" output from
`next N pulse (which can coincide with a Z pulse) is
`the gate 21.
`Since the only digits passing through the gate 20 are at
`stopped at the gate 30 but passes via the unit delay 31
`and the gates 32 and 34 to put the trigger I on at the
`P35 to P39 time, the gate 21 is inhibited only at this
`time, so that the signal appearing at the gate 22 during
`beginning of minor cycle (n+1) and a P40 via the gate
`38 and the half unit delay 49 puts the trigger TT off at
`the set-up minor cycle consists of 34 ones, followed by
`the end of this minor cycle. The trigger I also gates a
`the negated timing number, followed by a one. The
`P40 (coming via gates 39 and 40) through the gate 41
`gate 22 is inhibited at P34 and P40 times, so that its
`and this pulse delayed at 11 is the pulse which puts SU
`output will be the same as its input except during P34
`on for the next set-up. The P40 going through the gate
`and P40 times when its output will always be zero.
`This output appears at the binary adder 23 where digits
`41 also puts the trigger I off via the delay 42.
`Consider now a long transfer in which oc=0 and 3=1.
`are added in at P29 and P35 times. A suitable adder is
`In this case the first Z pulse puts the trigger TT on at
`described in U. S. Patent No. 2,686,632 aforesaid. The
`P40% in the set-up minor cycle and the first N pulse
`output of the adder 23 is sent to the counting tank CO.
`passing through the unit delay 31 and the gates 32 and 35
`The digits appearing at the points (i), (ii), (iii), and (iv)
`puts the trigger L on the second N pulse (occurring a
`of the circuit during the P29 to P40 times of the set-up
`major cycle later) is gated by L at the gate 36 to put the
`minor cycle are, therefore, as follows:
`trigger I on via the 2 unit delay 37. Thus I goes on and
`puts L off and also allows the next P40 via the gate 38 and
`the delay 49 to put TT off. In addition as before I gates a
`P40 through the gate 41 to put itself off and to put SU
`on again.
`Consider now a deferred transfer in which as 1 and
`B=0. The Z pulse is stopped at the gate 27 but the first
`N pulse delayed half a unit at 29 puts TT on, via the
`gates 30 and 28, at P402 in minor cycle n. Half a unit
`later (owing to the unit delay 31) it puts the trigger I on
`through the gates 32 and 34. When I goes on it has the
`same effect as before.
`Consider finally a serial transfer in which ot-1 and
`a=1. The Z pulses are stopped at 27 the first N pulse
`
`(i) All ones
`1111.
`(ii) P29 to P34-still ones
`P35 to P39-negated timing
`e.g. 111111101001
`number 31-7
`P40-still one
`(iii) As (ii), with P34 and PAO made
`Zero.
`P29 to P34 gives 111110, which
`is 3 in binary notation, while)ili11010100
`P35 to P40 gives 101000, which
`is the negated tinning uTaber
`31-n
`(iv) A P29 and a P35 are added to
`the nurnber at (iii)
`P29 to P34 gives 00000, which
`100,000
`(i)
`represents 32,
`while P35 to PAO gives 011000, P29 & P35--100000i 00000
`which represents 32-n
`(iv)
`00000000
`
`s
`
`SO
`
`75
`
`Samsung
`Ex. 1022 - Page 8
`
`

`

`10
`from a manual press button source 43 sets the trigger X
`at an arbitrary time. X conditions the gate 44 and allows
`the trigger Y to be set by the next P29. Y resets X and
`conditions the gate 46 through the unit delay 45. The
`next Z or N pulse thus passes through the gate 46 to set
`TT, and also to reset Y through the unit delay 47. This
`occurs an integral number of major cycles after TT would
`have been set in normal operation because N and Z pulses
`occur once per major cycle. From this point the opera
`tion up to the next setting of TT is the same in push
`button operation as in normal operation. The separate
`operations of a table may be carried out one by one with
`the push button and the hiatus of an integral number of
`major cycles between successive operations of the press
`button will not disturb the calculation, provided freely
`running devices (e.g. multipliers or dividers) are designed
`so that their results may be retained and passed back to
`the main storage after an integral number of major cycles.
`An alternative embodiment of the invention is illus
`trated in Figure 4. In this case the short tank INST is
`replaced by a series of delay units 55, 56, 57, 58, 59 and
`60 having delay times of 10, 7, 4, 8, 8 and 3 units respec
`tively.
`As in the embodiment described above, when a setup
`minor cycle starts the instruction contained in the delay
`units 55-60 is the next instruction to be obeyed. When
`this arrangement is used the forty digits of the instruction
`word are allocated as follows:
`
`5
`
`20
`
`25
`
`30
`
`2,799,449
`9
`puts TT on at P40% in minor cycle in and half a unit
`later puts the trigger I on as in a deferred transfer.
`However, in a serial transfer the only