(12) United States Patent
`Gulick
`
`USOO6690676B1
`(10) Patent No.:
`US 6,690,676 B1
`(45) Date of Patent:
`Feb. 10, 2004
`
`(54) NON-ADDRESSED PACKET STRUCTURE
`CONNECTING DEDICATED END POINTS
`ON A MULTI-PIPE COMPUTER
`INTERCONNECT BUS
`
`(75) Inventor: Dale E. Gulick, Austin, TX (US)
`(73) Assignee: Advanced Micro Devices, Inc.,
`Sunnyvale, CA (US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(*) Notice:
`
`(21) Appl. No.: 09/330,635
`(22) Filed:
`Jun. 11, 1999
`Related U.S. Application Data
`(60) Provisional application No. 60/109.589, filed on Nov. 23,
`1998.
`(51) Int. Cl. ................................................ G06F 13/14
`(52) U.S. Cl. ........................... 370/458; 709/101; 710/5;
`710/33
`(58) Field of Search ......................... 370,458; 709/101;
`710/5, 33
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,621,898 A 4/1997 Wooten ...................... 395/297
`5,640,392 A 6/1997 Hayashi ...................... 370/395
`5,742,847. A 4/1998 Knoll et al. ................ 395/866
`5,761,430 A 6/1998 Gross et al. ........... 395/200.55
`5.948,080 A 9/1999 Baker .......................... 710/37
`6,081,860 A * 6/2000 Bridges et al. ............. 710/110
`6,421,751 B1
`7/2002 Gulick ....................... 710/107
`6,457,081 B1
`9/2002 Gulick ....................... 710/305
`6,457,084 B1 * 9/2002 Gulick et al. ............... 710/305
`6,470.410 B1 * 10/2002 Gulick et al. ............... 710/305
`6,499,079 B1 * 12/2002 Gulick ....................... 710/305
`* cited by examiner
`
`Primary Examiner Melvin Marcelo
`(74) Attorney, Agent, or Firm Zagorin, O'Brien &
`Graham, LLP
`ABSTRACT
`(57)
`The protocol of a multi-pipe interconnection buS includes
`the ability to Send a non-addressed read or write transaction
`request over one of the pipes of a multiple-pipe computer
`interconnect bus. The multiple pipes carry transactions on a
`packet multiplexed basis. The transaction request is Sent
`over one of the pipes from a source to a target and includes
`a non-addressed transaction command. The transaction is
`performed in a predetermined location in response to the
`did
`d
`d. A
`p
`non-addressed transactOn COmmand. A transactOn reSDOnSe
`is returned upon completion of the transaction.
`
`5,450,411 A
`
`9/1995 Heil .......................... 370/94.2
`
`17 Claims, 35 Drawing Sheets
`
`
`
`
`
`
`
`
`
`PPEO
`SOURCE
`LOGC
`
`PPE
`SOURCE
`LOGIC
`
`213
`
`PPEN
`SOURCE
`OGIC
`
`
`
`
`
`FUNCTION X
`
`SAMSUNG
`EX 1004, PAGE 1
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 1 of 35
`
`US 6,690,676 B1
`
`1
`
`CACHE
`
`CPU
`
`MEMORY
`MEM BUS
`NORTH BRIDGE
`A
`
`103
`109
`/ VIDEO,
`GRAPHICS
`
`MONITOR
`
`1394
`
`PC / 101
`
`FRAME BUFFER
`
`HARD DISK
`CONSUMER-
`ELECTRONICS
`
`PERIPHERALS
`DEVICE BAY
`CONTROLLER
`
`105
`
`
`
`12C
`
`OPTIONAL SYSTEM
`MANAGEMEN
`CONTROLLER
`
`AT LOGIC
`RIC
`ACP
`APIC
`GPIO
`DDMA
`
`
`
`USB
`
`SIO
`
`PERIPHERALS
`KYBD
`MOUSE
`FLOPPY
`PRINTER
`MAGE
`HD
`
`115
`
`9
`ISA-X BUS
`
`PERIPHERALS
`Y ARD DISK
`
`IDE
`
`DVD
`
`CARDS
`
`SDN
`
`2
`
`PERIPHERALS
`SPEAKERS
`MICROPHONE
`TELEPHONE
`JOYSTICK
`KEYBOARD
`MOUSE
`LAN
`MODEM
`SON
`AUDO
`HID (MONITOR)
`
`BIOS ROM
`
`AUDO
`(SOUND BLASTER)
`
`MODEM
`ISDN
`
`JOYSTICK
`
`MUSIC
`KEYBOARD
`
`SPEAKER
`MCROPHONE
`
`FIG.
`(Prior Art)
`
`SAMSUNG
`EX 1004, PAGE 2
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 2 of 35
`
`US 6,690,676 B1
`
`- - - - - - - - - - - -
`
`/
`
`I PIPEO
`
`SOURCE
`LOGIC
`
`PIPE
`SOURCE
`LOGIC
`
`27
`
`
`
`
`
`
`
`213
`
`as or
`
`is s r. or ur
`
`up up voes s
`
`-s a
`
`u.
`
`p
`W
`
`as
`
`
`
`PPEN
`SOURCE
`LOGIC
`
`SAMSUNG
`EX 1004, PAGE 3
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 3 of 35
`
`US 6,690,676 B1
`
`
`
`PROCESSORMODULE (SIDEA)
`
`LINK
`INTERFACE
`
`LINK
`INTERFACE
`
`SYSTEM
`MEMORY
`CONTROLLER
`
`GRAPHCSIF
`
`FIG. 3
`
`SAMSUNG
`EX 1004, PAGE 4
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 4 of 35
`
`US 6,690,676 B1
`
`
`
`RECEIVE
`CONTROLLER
`
`NK INTERFACESIDEA
`305
`
`f
`
`205
`
`LINK NERFACESIDE B
`3O7
`
`FIG. 4
`
`SAMSUNG
`EX 1004, PAGE 5
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 5 of 35
`
`US 6,690,676 B1
`
`NKAYER
`
`50
`
`GLOBAL
`CONFIGURATION
`REGISTERS
`
`LOCAL-REQUEST
`ARBER
`
`CHANNELS (E.G., RGB
`DATA, 1394, PC,
`SYSTEMMEMORY,
`GRAPHCS, OTHER
`LINKS)
`
`PROTOCOLLAYER
`
`TIME-DOMAINSYNCHRONIZER
`
`
`
`RECEIVE
`CONTROLLER
`
`WHOLE-BUS
`MODE ARBER
`
`TRANSMIT
`CONTROLLER
`
`
`
`
`
`PHYSICAL LAYER
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FE 0100 0000
`
`RESERVED
`FEFFFFFFFF
`FE OFFFFFF CONFIGURATION
`FE OOFFFFFF
`RESERVED
`FE OOOOFFFF x86 /O
`FE0000 0000
`OOOOOOOOOO FDFFFFFFFF NORMAL MEMORY
`
`
`
`
`
`24-BIT CONFIGURATION SPACE
`
`16-BIT x86 l/O ADDRESS SPACE
`DRAMADDRESS SPACE
`2-B PC ADDRESS SPACE
`
`FIG. 6
`
`SAMSUNG
`EX 1004, PAGE 6
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 6 of 35
`
`US 6,690,676 B1
`
`MEMORY WRITE PACKE :
`
`PIPED
`# (5)
`
`PKT
`TYPE
`(6)
`
`AG
`(5)
`
`BUF
`AVAIL
`(4)
`
`SPECIALCYCLE WRITE PACKET:
`
`PIPED
`# (5)
`
`PKT
`TYPE
`(6)
`
`AG
`(5)
`
`BUF
`AVAIL
`(4)
`
`RSRVD
`(4)
`
`FIG.
`7A
`
`RSRVD
`(4)
`FIG.
`7B
`
`ADDR
`(40)
`
`RSRVD
`(2)
`
`SIZE
`(6)
`
`DAA
`(1-64)
`
`ADDR
`(40)
`
`RSRVD
`(2)
`
`SIZE
`(6)
`
`DATA
`(4)
`
`
`
`
`
`NON-ADDRESSED WRITE PACKET
`
`PPED PKT TYPE
`# (5)
`(6)
`
`TAG
`(5)
`
`RSRVD
`BUF
`(4)
`AVAIL (4)
`FIG,
`7C
`
`WRITE ACK (ORNAK) PACKET
`
`RSRVD
`(2)
`
`SIZE
`(6)
`
`DATA
`(1-64)
`
`FLUSH PACKET
`
`FIG.
`7D
`
`FIG.
`
`SAMSUNG
`EX 1004, PAGE 7
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 7 of 35
`
`US 6,690,676 B1
`
`FENCE PACKET
`PIPEID # (5)
`PKT TYPE (6)
`m
`
`RSRVD (5)
`FIG.
`
`BUF AVAIL (4)
`
`RSRVD (4)
`
`(40)
`
`(2)
`
`(6)
`
`MEMORY READREQUESTPACKET
`
`# (5)
`
`(6)
`
`(5)
`
`(4)
`AVAIL (4)
`FIG.
`7G
`
`NON-ADDRESSED READREQUESTPACKET
`
`FIG.
`7H
`
`READ RESPONSE PACKET
`
`# (5)
`
`(6)
`
`(5)
`
`first site E,
`
`(2)
`
`(6)
`
`(1-64)
`
`(4)
`AVAIL (4)
`FIG.
`7
`
`NON ADDRESSED READ RESPONSE PACKET
`
`(5)
`
`(6)
`
`(1)
`
`(4)
`FIG.
`7
`
`(2)
`
`(6)
`
`(1-64)
`
`SAMSUNG
`EX 1004, PAGE 8
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 8 of 35
`
`US 6,690,676 B1
`
`READ REEC PACKET
`
`NOPPACKET
`
`FIG.
`7K
`
`FIG.
`
`SAMSUNG
`EX 1004, PAGE 9
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 9 of 35
`
`US 6,690,676 B1
`
`AVAILABLE
`AGS = OP
`
`YES
`
`LOAD NOTAGS FREE TIMER
`WTHTIMERVALUE
`
`
`
`FRAME
`COMPLEE?
`
`DECREMENT NOTAGS
`FREE TIMER
`
`
`
`
`
`
`
`AVAILABLE TAGS
`STL = O2
`
`
`
`81
`
`GENERATE INTERRUPT
`
`FIG, 8
`
`SAMSUNG
`EX 1004, PAGE 10
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 10 0f 35
`
`US 6,690,676 B1
`
`d
`Co
`O
`
`
`
`R
`
`
`
`ch
`
`SAMSUNG
`EX 1004, PAGE 11
`
`

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`SAMSUNG
`
`EX 1004, PAGE 12
`
`SAMSUNG
`EX 1004, PAGE 12
`
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 12 of 35
`
`US 6,690,676 B1
`
`
`
`TARGETFUNCTION
`
`1102
`
`
`
`
`
`TARGET ENDPOINT
`
`REQUESTPACKETS
`
`INTERCONNECT BUS
`PHYSICAL AND
`PROTOCOLLAYERS
`- S --
`
`
`
`
`
`
`
`PIPE ROUTER
`
`INTERCONNECT BUS
`- NK LAYER
`
`MSIDE
`- PM SIDE
`
`
`
`
`
`1 104
`RESPONSE PACKES
`
`PIPE ROUTER
`
`
`
`SOURCE ENDPOINT
`
`
`
`SOURCE FUNCTION
`
`10
`
`FIG. 11
`
`SAMSUNG
`EX 1004, PAGE 13
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 13 Of 35
`
`US 6,690,676 B1
`
`20
`
`PMSIDE
`PM-SIDE FUNCION
`GENERATES AWRITE TO AN
`|MFUNCTION
`
`
`
`LINK WRITE REQUEST
`PACKETBUILT (PIPEID AND
`TAGASSIGNED)
`
`2O3
`
`PACKESENT TOPM
`PROTOCOLLAYER
`
`own
`
`20
`
`PACKE RECEIVED BY PM
`PROTOCOLLAYER
`
`21
`ROUTED TO THE PM-SIDE
`FUNCION ENDPOINT
`(BASED ON PIPED)
`
`
`
`22
`
`TAG IS RETIRED
`
`
`
`
`
`
`
`- 204
`IMSIDE
`PACKETRECEIVED BYM
`PROTOCOLAYER
`
`1205
`PACKETROUTED TO THE IM
`SIDE FUNCTON ENDPOINT
`(BASED ON PIPEID)
`
`2O6
`
`PACKE IS DECONSTRUCTED
`
`DATAS WRITTEN TO THE
`TARGET FUNCTION
`
`1208
`RESPONSE PACKE BUILT
`(ACK) (SAME PIPED
`
`209
`
`PACKE SENT TOM
`PROTOCOLLAYER
`
`FIG, 12
`
`SAMSUNG
`EX 1004, PAGE 14
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 14 of 35
`
`US 6,690,676 B1
`
`1306
`
`308
`
`1310
`
`PCBRIDGE
`
`SLAVE PORT
`
`1303
`
`CPUPPETARGET
`DISTRIBUTOR
`(LINK TARGET)
`
`NERCONNECT BUS
`LINKAYER
`-
`
`PPE ROUTER
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`INTERCONNECT BUS
`PHYSICAL AND
`PROTOCOLLAYERS
`
`48 Se-
`X w.
`
`As 48 IMSIDE
`- - PM SIDE
`
`
`
`
`
`
`
`
`
`
`
`
`
`CPUREAD AND WRITE
`PIPE PAR
`
`CPU
`(FUNCTION)
`
`CPUSOURCE PPE
`(HOST BUS
`INTERCONNEC
`BUSBRIDGE)
`CPU HOS BUS
`
`
`
`FIG. 13
`
`SAMSUNG
`EX 1004, PAGE 15
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 15 0f 35
`
`US 6,690,676 B1
`
`
`
`1407
`
`
`
`
`
`
`
`PACKET ROUTED TO CPU
`PPETARGET DISTRIBUTOR
`(BASED ON PIPED)
`408
`
`PACKET IS DECONSTRUCED
`
`409
`TARGET FUNCTION READ
`(FUNCTION IDENTIFIED BY
`PHYSICAL ADDRESS)
`40
`
`RESPONSE PACKETBULT
`(SAME PIPED ANDTAG)
`4
`
`PACKETSEN TOM
`PROTOCOLLAYER
`
`PM SIDE
`
`4O1
`
`CPU GENERATES AREAD TO
`
`1402
`
`
`
`
`
`HOST BUS - DT BRIDGE
`
`1403
`READ PACKETBUILT (CPU
`SOURCE PIPED AND AG
`ASSIGNED)
`
`
`
`404
`
`PACKE SENT TO PM
`PROTOCOLLAYER
`
`412
`
`PACKETRECEIVED BY PM
`PROTOCOLLAYER
`
`
`
`1413
`
`ROUTED TO HOST BUS-D
`BRIDGE (BASED ON PIPEID)
`1414
`
`
`
`TAGS RETIRED
`
`145
`
`
`
`READ IS COMPLETED TO CPU
`
`FIG. 14
`
`SAMSUNG
`EX 1004, PAGE 16
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 16 of 35
`
`US 6,690,676 B1
`
`PCI BRIDGE
`
`SLAVE PORT
`
`TARGET
`ENDPOINT
`
`ARGET
`TARGET
`ENDPON T ENDPOINT
`
`1504
`
`1506
`
`1505
`
`PPE ROUTER
`
`INTERCONNECT BUS
`- NK LAYER
`
`INTERCONNECT BUS
`PHYSICAL AND
`PROTOCOLLAYERS
`IMSEDE
`N.--------------- -- -
`- - - - --
`-- PM SIDE
`1504
`'' CPUREAD AND WRITE
`/ PIPE PAR
`
`SOURCE
`DISTRIBUTOR
`CPUSOURCE PIPE
`(HOST BUS
`NTERCONNECT
`BUSBRIDGE)
`503
`CPU HOST BUS
`
`
`
`1502
`
`FIG.15
`
`CPU
`(FUNCTION)
`
`50
`
`SAMSUNG
`EX 1004, PAGE 17
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 17 of 35
`
`US 6,690,676 B1
`
`1602
`
`604
`
`1606
`
`PC BRIDGE
`
`SLAVE PORT
`
`SOURCE
`ENDPOINT
`
`SOURCE
`ENDPOINT
`
`SOURCE
`ENDPON
`
`INTERCONNECT BUS
`PHYSICAL AND
`PROTOCOLLAYERS
`
`1605
`
`INTERCONNECT BUS
`N
`KAYER
`
`-
`
`e
`
`A -
`
`T -
`
`MSDE
`PM SIDE
`
`1616
`
`CPU READ AND WRITE
`PPE PAR
`*-1
`
`ARGET
`CONCENTRATOR
`
`MEMORY ROUTER
`
`63
`
`64
`
`
`
`AGP BRIDGE
`(FUNCTION)
`
`1609
`
`MEMORY
`CONTROLLER
`(FUNCTION)
`
`16
`
`FIG. 16
`
`SAMSUNG
`EX 1004, PAGE 18
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 18 of 35
`
`US 6,690,676 B1
`
`701
`
`MSEDE
`
`MFUNCTION GENERATES A
`READ TO PMMEMORY
`
`702
`READ PACKET BUIL (M
`FUNCONSOURCE PIPED
`AND TAGASSIGNED
`
`
`
`703
`
`PACKESENTIOM
`PROTOCOLLAYER
`
`17
`
`
`
`
`
`PACKE RECEIVED BY M
`PROTOCOLLAYER
`
`1712
`LAYERTO IMFUNCTION PIPE
`ENDPOINT (BASED
`ON PIPED)
`
`
`
`1713
`
`
`
`TAG IS RETIRED
`
`74.
`READ IS COMPLETED TOM
`FUNCTION
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(
`
`PM SIDE
`
`1704
`PACKET RECEIVED BY PM
`PROTOCOLLAYER
`
`PACKETROUTED TO
`MEMORY CONCENTRATOR
`(BASED ON PIPEID)
`17O6
`
`PACKE IS DECONSTRUCED
`
`707
`MEMORY ROUTER DIRECTS
`THE READ TO THE MEMORY
`CONTROLLERFUNCTION
`(IDENTIFIED BY PHYSICAL
`ADDRESS)
`
`
`
`1703
`READ DAARETURNED WA
`THE ROUTER TO THE
`CONCENTRATOR
`
`709
`RESPONSE PACKET BUIL
`(SAME PIPE ID AND TAG)
`1710
`PACKESENT TO PM
`PROTOCOLAYER
`
`FIG. 17
`
`SAMSUNG
`EX 1004, PAGE 19
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 19 of 35
`
`US 6,690,676 B1
`
`
`
`PROCESSOR
`MODULE
`
`18O
`
`1804
`
`
`
`1802
`
`
`
`
`
`
`
`1805
`
`18
`
`SAVEC
`
`
`
`1812
`
`FUNCIONS
`
`\
`
`LINK PORT 1
`
`SAVE IC
`
`1815
`
`FIG. 18
`
`SAMSUNG
`EX 1004, PAGE 20
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 20 of 35
`
`US 6,690,676 B1
`
`
`
`• • • • • • • • • • • • ? ? ? ? ? ? ? ? ? ? ? • • • • • • •
`
`• • • • • • • • • • • - ? ? ? ? • • • • • • • •
`
`SAMSUNG
`EX 1004, PAGE 21
`
`

`

`U.S. Patent
`
`Feb. 10, 2004
`
`Sheet 21 of 35
`
`US 6,690,676 B1
`
`| 102
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`3002
`
`OZ
`
`ZHW 008
`
`XOOTOXIN?T
`
`SAMSUNG
`EX 1004, PAGE 22
`
`

`

`U.S. Patent
`
`US 6,690,676 B1
`
`
`
`3dld 018B][108]
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`US. Patent
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`US 6,690,676 B1
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`U.S. Patent
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`US 6,690,676 B1
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`U.S. Patent
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`Feb. 10, 2004
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`Sheet 25 0f 35
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`US 6,690,676 B1
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`Feb. 10, 2004
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`Sheet 26 of 35
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`US 6,690,676 B1
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`US. Patent
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`Feb. 10, 2004
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`Sheet 28 0f 35
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`US 6,690,676 B1
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`U.S. Patent
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`Feb. 10, 2004
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`Sheet 29 of 35
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`US 6,690,676 B1
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`^T 2605
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`FUNCTION O
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`FIG. 26
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`U.S. Patent
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`Feb. 10, 2004
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`Sheet 30 of 35
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`US 6,690,676 B1
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`31:8
`RESERVED
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`HEADER REGISTERS
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`HEADER REGISTERS
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`FIG. 27
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`US. Patent
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`Feb. 10, 2004
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`Sheet 31 0f 35
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`US 6,690,676 B1
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`U.S. Patent
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`Feb. 10, 2004
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`Sheet 32 0f 35
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`US 6,690,676 B1
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`U.S. Patent
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`Feb. 10, 2004
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`Sheet 33 of 35
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`US 6,690,676 B1
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`OOh
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`TYPE
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`BASE ADDRESS REGISTERS
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`PRIMARYBUS
`SECONDARY BUS
`SECONDARYLATENCY SUBORDINATE BUS
`NUMBER
`NUMBER
`TIMER
`NUMBER
`I/O BASE
`I/O LIMIT
`SECONDARY STATUS
`MEMORYBASE
`MEMORY LIMIT
`PREFETCHABLE MEMORY BASE
`PREFETCHABLE MEMORY LIM
`PREFETCHABLE BASE UPPER 32 BIS
`PREFETCHABLE LMUPPER 32 BITS
`/O LIMIT UPPER 16 BIS
`I/O BASE UPPER 16 BITS
`CAPABILITIES
`POINTER
`
`RESERVED
`
`RESERVED
`EXPANSION ROM BASE ADDRESS
`BRIDGE CONTROL
`INTERRUPPEN
`FIG.
`29
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`NERRUPT LINE
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`Feb. 10, 2004
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`Sheet 34 0f 35
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`US 6,690,676 B1
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`PC TYPEO
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`DEVICE ID
`STATUS
`CLASS CODE
`HEADERYPE
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`COMMAND
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`SUBSYSTEMD
`EXPANSION ROM BASE ADDRESS
`RESERVED
`
`
`
`RESERVED
`NTERRUPT PIN
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`Feb. 10, 2004
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`Sheet 35 of 35
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`UPSTREAM-SIDE LINK BRIDGE REGISTERS
`
`POINTER
`ASYNCHRONOUS 256-BYTE COUNTER
`ISOCHRONOUS 256-BYTE COUNTER
`
`HEADERD
`
`COUNTER RELOAD
`
`SOCHRONOUS BYTE COUNT
`
`FREQUENCY
`
`FREQUENCY
`
`COUNER RELOAD
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`DOWNSTREAM-SIDE LINK BRIDGE REGISTERS
`RESERVED
`ASYNCHRONOUS 256-BYTE COUNER
`ISOCHRONOUS 256-BYTE COUNTER
`PM FRAME COUNTER
`
`COUNTERRELOAD
`
`SOCHRONOUS BYTE COUNT
`
`FREQUENCY
`
`FREQUENCY
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`RESERVED
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`1
`NON-ADDRESSED PACKET STRUCTURE
`CONNECTING DEDICATED END POINTS
`ON A MULTI-PIPE COMPUTER
`INTERCONNECT BUS
`
`RELATED APPLICATIONS
`This application claims benefit of provisional application
`60/109,589, filed Nov. 23, 1998, entitled COMPUTER
`COMMUNICATION LINK, which application is incorpo
`rated herein by reference.
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The invention relates to computer Systems and more
`particularly to a computer System having a high Speed
`communication link having multiple pipes operating on the
`communication link.
`2. Description of the Related Art
`Traditional personal computer architectures partition the
`computer System into the various blocks shown in the
`exemplary prior art system illustrated in FIG. 1. One central
`feature of this prior art architecture is the use of the
`Peripheral Component Interface (PCI) bus 101 as the con
`nection between the “north bridge' integrated circuit 103
`and the “south bridge' integrated circuit 105. The north
`bridge functions generally as a Switch connecting CPU 107,
`a graphics bus 109 such as the Advanced Graphics Port
`(AGP) bus, the PCI bus and main memory 111. The north
`bridge also contains the memory controller function.
`The South bridge generally provides the interface to the
`input/output (I/O) portion of the system with the possible
`exception of video output as illustrated in FIG. 1.
`Specifically, the south bridge 105 provides a bridge between
`the PCI bus and legacy PC-AT (Advanced Technology)
`logic. The South bridge also provides a bridge to the legacy
`ISA bus 115, the Integrated Device Electronics (IDE) disk
`interface 117 and the Universal Serial Bus (USB) 119. In the
`illustrated prior art architecture, PCI bus 101 also functions
`as the major input/output bus for add-in functions Such as
`network connection 121. The various buSSes and devices
`shown in FIG. 1 are conventional in the personal computer
`industry and are not described further herein unless neces
`Sary for an understanding of the present invention.
`In current and future personal computer Systems, two
`basic types of data are transferred between integrated cir
`cuits: isochronous data and asynchronous data. Isochronous
`data refers to data used in real-time data Streams Such as
`audio data or motion-picture video data. Asynchronous data
`is used for all other transfers, Such as central processing unit
`(CPU) accesses to memory and peripherals or bulk data
`transmissions from a hard drive into System memory.
`The PCI bus causes a lack of determinism in the system
`because any function on the PCI bus can become master of
`the bus and tie up the bus. Thus, the throughput available on
`the PCI bus for a particular transfer and the latency that is
`involved for that transfer is unknown. PCI bus load fluc
`tuations can result in uncertain and irregular quality of
`service. Therefore, having a PCI bus as the major input/
`output bus means that the major input/output bus of present
`day computer Systems does not provide proper Support for
`both isochronous and asynchronous data. If a computer
`System gives asynchronous data priority or treats isochro
`nous data as asynchronous data, then those functions relying
`on real time data, Such as motion-picture Video, may not
`function Satisfactorily. Alternatively, if a computer System
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`prioritizes isochronous data, then the performance of the
`computer System can Suffer Since the latency of asynchro
`nous data may become unacceptably long. AS computer
`Systems are called on to perform more and more real time
`activity, Such as real time Video, it becomes more critical that
`asynchronous and isochronous data be treated in a manner
`that prevents problems from occurring in the real time tasks
`without adversely effecting other aspects of computer per
`formance.
`In addition, as the number of functions integrated onto the
`integrated circuits of computer Systems increases, the need
`for additional integrated circuit package pins also increases.
`Supporting the hostbus, the memory interface, the PCI bus
`and a graphics interface results in a north bridge integrated
`circuit having a relatively large number of pins that is
`relatively unpopulated in terms of the number of transistors
`on the integrated circuit. The large number of pins requires
`the integrated circuit to be larger than would otherwise be
`necessary and therefore increases costs.
`It would be desirable therefore, to have a deterministic
`high Speed major interconnect bus providing improved
`quality of Service for both isochronous and asynchronous
`traffic classes. It would also be desirable to reduce the
`preSSure for additional pins on the integrated circuits making
`up the computer System.
`
`SUMMARY OF THE INVENTION
`Accordingly, an interconnection bus is provided in a
`computer System that carries transactions between functions
`in the computer System. The protocol of the interconnection
`buS includes the ability to Send a non-addressed transaction
`request over one of the pipes of a multiple-pipe computer
`interconnect bus, the multiple pipes carrying transactions on
`a packet multiplexed basis. In one embodiment, a method is
`provided for Sending a transaction request over the inter
`connect bus over one of the pipes from a Source to a target,
`the transaction request including a non-addressed transac
`tion command. The method further includes performing a
`transaction in a predetermined location in response to the
`non-addressed transaction command and returning a trans
`action response upon completion of the transaction. The
`transaction may be a read or write command.
`In another embodiment, the invention provides a first
`integrated circuit including a plurality of first functions. A
`command packet builder in the first integrated circuit
`responds to a request from one of the first functions to
`perform a non-addressed transaction to a Second function by
`providing a non-addressed transaction request packet indi
`cating a non-addressed transaction for the Second function.
`A transmit circuit is coupled to the command packet builder
`circuit and transmits the non-addressed transaction request
`packet Over an interconnect bus connected to the first
`integrated circuit. A Second integrated circuit is connected to
`the interconnect bus and includes the Second function. A
`command processing circuit in the Second integrated circuit
`decodes the command received over one of the pipes of the
`interconnect bus as a command to operate on a predeter
`mined memory area. A response packet builder circuit in the
`Second integrated circuit builds a response indicative of a
`result of performing the non-addressed transaction com
`mand.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The present invention may be better understood, and its
`numerous objects, features, and advantages made apparent
`to those skilled in the art by referencing the accompanying
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`3
`drawings, wherein, the use of the same reference signals in
`different drawings indicate Similar or identical items.
`FIG. 1 shows an exemplary prior art personal computer
`System.
`FIG. 2 shows a block diagram illustrating the pipe Struc
`ture according to one embodiment of the present invention.
`FIG. 3 is a high level block diagram of a portion of a
`personal computer System that utilizes an exemplary com
`munication link described herein.
`FIG. 4 shows a data bus and the interfaces of an exem
`plary communication link in greater detail.
`FIG. 5 illustrates the link layer, protocol layer and physi
`cal layer of the communication link.
`FIG. 6 shows an exemplary address map for the processor
`module-interface module for an x86 environment utilizing
`an embodiment of the present invention.
`FIGS. 7A-7L show exemplary packets used in various
`link transactions.
`FIG. 8 shows a flow diagram for determining a no tags
`free error condition.
`FIG. 9 shows one implementation of a circuit to detect the
`no tags free error condition.
`FIG. 10 shows common pipe configurations used in
`various embodiments of the present invention.
`FIG. 11 illustrates a point to point pipe configuration.
`FIG. 12 illustrates a flow diagram of a write transaction
`acroSS the link.
`FIG. 13 illustrates a target distributor pipe configuration.
`FIG. 14 illustrates a flow diagram of a read transactions
`acroSS the link.
`FIG. 15 illustrates a source distributor pipe configuration.
`FIG. 16 illustrates a target concentrator pipe configura
`tion.
`FIG. 17 illustrates a flow diagram of an interface module
`read transaction to memory.
`FIG. 18 illustrates the use of Subordinate links in a
`computer System.
`FIG. 19 illustrates a pipe structure and associated func
`tions of a typical computer System.
`FIG. 20 illustrates one implementation of the protocol
`layer transmit circuit.
`FIG. 21 illustrates one implementation of the protocol
`layer receive circuit.
`FIG.22 illustrates an exemplary pipe Source circuit Struc
`ture.
`FIG. 22A illustrates a pipe Source circuit Structure that
`includes a pass through queue.
`FIG. 23 illustrates an exemplary non-concentrated pipe
`target circuit Structure.
`FIG. 23A illustrates a pipe target circuit Structure that
`includes a pass through queue.
`FIG. 24 illustrates an exemplary concentrated pipe target
`circuit structure.
`FIG. 25 shows a block diagram of a target distributor and
`its connections to common logic and to functions.
`FIG. 26 illustrates additional logic used in the target
`concentrator to map accesses to appropriate functions.
`FIG. 27 illustrates the software structure for the capabili
`ties pointer.
`FIG. 28 (FIG. 28A and FIG. 28B) illustrates the basic
`configuration Structure and register addressing Strategy of a
`typical System according to one embodiment of the present
`invention.
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`FIG. 29 illustrates a type 1 (bridge) header.
`FIG. 30 illustrates a type 0 (function) header.
`FIG. 31 illustrates the upstream and downstream link
`registers used for link bridges.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT(S)
`FIG. 2, illustrates a generic System according to one
`embodiment of the present invention. The System includes
`module 201 and module 203 coupled by high speed link 205.
`High speed link 205 is in one embodiment a low pin count
`high speed point to point bus (generally referred to herein as
`a “link to distinguish the point to point interconnect bus
`from a multi-drop bus). The term “interconnect bus” is also
`used herein interchangeably with “link” to avoid confusion
`when discussing the “link layer of the communication link.
`Examples of Such a link are described in the following
`co-pending applications: application Ser. No.: 09/098,874,
`entitled BUS OPTIMIZED FOR PERSONAL COMPUTER
`TRAFFIC; application Ser. No. 09/099,227, filed Jun.
`17, 1998, entitled METHOD OF MODE CONTROL IN A
`BUS OPTIMIZED FOR PERSONAL COMPUTER TRAF
`FIC; application Ser. No. 09/098,874, filed Jun. 17, 1998,
`entitled BUS OPTIMIZED FOR PERSONAL COMPUTER
`TRAFFIC; application Ser. No. 09/098,360 filed Jun. 17,
`1998, entitled COMPUTER WITH HIGH VELOCITY
`LOW PIN COUNT NORTH BRIDGE SOUTH BRIDGE
`LINK, co-pending application Ser. No. 09/098,228 filed Jun.
`17, 1998, entitled CPU-NORTH BRIDGE INTEGRATION
`UTILIZING AN INTERCONNECTION BUS PROVID
`ING A HIGH SPEED-LOW PIN COUNT LINK; and appli
`cation Ser. No. 09/098,876 filed Jun. 17, 1998, entitled
`WRITE ONLY BUS WITH WHOLE AND HALF BUS
`MODE OPERATION; which applications are incorporated
`herein by reference in their entirety.
`Link 205 has a plurality of pipes 207-211. Each pipe (or
`channel), couples a function in module 201 to a function in
`module 203. Each pipe has a Source end and a target end. For
`example, source end 215 of pipe 207 couples function A on
`module 201 to the target end 221 of pipe 0. The target end
`221 of pipe 0 is in turn coupled to function D on module 203,
`thereby providing a path between function A and function D.
`A function is a circuit that provides a Specific function in
`the computer System. For example, a CPU and memory
`controller on a processor module are examples of functions.
`A PCI bridge and 1394 host controller are further examples
`of functions on an interface module. A function can have any
`combination of target and Source pipes. For example, in an
`exemplary System, the memory controller may only have
`targets, the CPU may only have sources, and the PCI bridge
`may have both targets and Sources as discussed further
`herein.
`Each pipe Source and pipe target communicate over bus
`205 on a packet multiplexed basis using packets uniquely
`asSociated with the respective pipe. Before various aspects
`of the pipe architecture are examined in greater detail,
`certain details of exemplary bus 205 will be discussed to
`provide the appropriate context for use of the pipes.
`The Link
`One way to achieve high Speed is to utilize a point-to
`point bus in which only two devices are present on the bus.
`A point-to-point bus can inherently run at higher speeds than
`a multi-drop buS Such as the PCI buS Since a point-to-point
`link has reduced electrical loading and reduced noise caused
`by reflections at tap points Such as connectors. It is possible
`to provide a point to point link that operates at, e.g., 25 times
`
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`the speed of the PCI bus. Given this, a 32-bit wide PCI bus
`can be replaced by a 16-bit (or even an 8-bit link) while still
`adding Significant transfer bandwidth.
`Referring to FIG. 3, a portion of a typical personal
`computer system is shown which utilizes link 205 to com
`municate between two integrated circuits 301 and 303. The
`computer System includes processor module 301 and inter
`face module 303. Processor module 301 includes link inter
`face 305 which is coupled to link interface 307 in interface
`module 303. Bus 205 provides guaranteed bandwidth and
`latency to each isochronous Stream Such as RAMDAC data,
`audio data, and 1394 isochronous Streams while also
`attempting to minimize latency to asynchronous accesses
`Such as CPU-initiated accesses and PCI-initiated accesses.
`One feature of the architecture shown in FIG. 3 is that the
`PCI bus no longer functions as the primary interface
`between the processor/memory controller 301 input/output
`functions. Link 205 has replaced the PCI bus as the primary
`interface and also carries both isochronous and asynchro
`nous data.
`The exemplary processor module 301 provides the major
`processing function in the computer System and includes
`System memory controller 309, a central processing unit
`(CPU) (such as the x86 processor AMD K6 TM) and graphics
`interface 306. Interface module 303 provides an interface
`between various input/output devices Such as Video
`monitors, hard drives, Scanners, printers, network
`connections, modems, and the processor module. The exem
`plary interface module 307 includes interface 310 providing
`an interface to the industry Standard architecture (ISA) bus,
`IEEE 1394 interface 312, peripheral component interface
`(PCI) 314, RAMDAC 316 and Intelligent Drive Electronics
`(IDE) controller 318.
`Exemplary link 205 connecting processor module (PM)
`301 and the interface module (IM)303 includes data portion
`DB. Data bus DB includes two data portions. In one
`embodiment, each data portion contains one byte (8bits) of
`data. However, the number of bits on the data bus may be of
`Size (2'-1:0), where n is an integer-0. Thus, a minimum
`implementation has one data bit in each direction. In the
`illustrated embodiment, n equals 4, with each data portion
`having one byte.
`The exemplary system is divided into two sides with