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`Provisional Application Cover Sheet
`
`This is a request for filing a PROVISIONAL APPLICATION under 37 CFR l.53(b)(2).
`
`
`
`BOX PROVISIONAL
`APPLICATION, ASSISTANT
`COMMISSIONER FOR PATENTS,
`WASHINGTON, DC. 20231
`
`Docket Number
`1001-0080—V-US
`
`Type a plus sign (+)
`inside this box
`
`INVENTOR(S) APPLICANT(S)
`
`at g.*
`
`LAST NAME
`
`FIRST NAME
`
`(City and Either State or Foreign Country)
`Austin, Texas
`Austin, Texas
`Austin, Texas
`Austin, Texas
`
`TITLE OF THE INVENTION 7
`280 Characters Maximum a
`
`“COMPUTER COMIVIUNICATION LINK”
`
`CORRESPONDENCE ADDRESS
`
`Please mail all correspondence concerning this application to:
`
`Mark Zagorin
`Zagorin, O'Brien & Graham, L.L.P.
`1120 South Capital of Texas Hwy.
`Building 3, Suite 208
`Austin, TX 78746—6460
`
`Tel.: (512) 347-9030
`Fax: (512) 347—9031
`
`(USA
`
`S ENCLOSED APPLICATION PARTS (Check airman apply)
`
`Specification
`
`Claims
`
`Drawings
`
`Small Entity Statement
`
`Other: (Specify)
`
`Number of Pages
`
`69
`
`Number of Pages __45_
`
`Number of Sheets ___3Q
`
`METHOD OF PAYMENT (Check one)
`
`credit Deposit Account Number101-03 65 Large Entity $150
`
`gigggéglgAL
`
`AMOUNT
`
`D Small Entity $75
`
`
`
`E] 112::“1‘ ormoney orderis enclosed to cover the Provisional filing
`
`E The Commissioneris hereby authorized to charge filing fees and
`
`The invention was made by an agency of the United State Government or under a contract with an agency of the United States
`Government.
`
`ENO
`D Yes, the name of the U.S. Government agency and the Government contract number are:
`
`Respectfully submitteMe%
`Signature: ‘g; 2/ 31:55::
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`Date: November 23, 1998
`
`Typed or Printed Name: Mark Zagorin
`
`Reg. No. 36,067
`
`E]
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`Additional inventors are being named on separately numbered sheets attached hereto.
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`PROVISIONAL APPLICATION FILING ONLY
`EXPRESS MAIL LABEL NO:
`EL151293014US
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`Attorney Docket No.2
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`1001-0080-V—US
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`“Express Mail” mailing label number: ELlSlE‘lEUlHUS
`
`COMPUTER COMMUNICATION LINK
`
`Dale E. Gulick
`
`Larry D. Hewitt,
`Alfred Hartmann,
`
`Geoffrey SS, Strongin
`
`Related Applications
`
`
`
`
`This application relates to co-pending application serial no. 09/099,227, filed
`
`June 17, 1998, entitled METHOD OF MODE CONTROL IN A BUS OPTIMIZED
`
`FOR PERSONAL COMPUTER TRAFFIC, by Larry Hewitt; co-pending application
`
`serial no. 09/098,874, filed June 17, 1998, entitled BUS OPTIMIZED FOR
`
`PERSONAL COMPUTER TRAFFIC, by Larry Hewitt and Dale E. Gulick; co~
`
`pending application serial no. 09/098,360 filed June 17, 1998, entitled COMPUTER
`
`WITH HIGH VELOCITY—LOW PIN COUNT NORTH BRIDGE SOUTH BRIDGE
`
`LINK, by Larry Hewitt and Dale E. Gulick; co-pending application serial no.
`
`09/098,228 filed June 17, 1998, entitled CPU—NORTH BRIDGE INTEGRATION
`
`UTILIZING AN INTERCONNECTION BUS PROVIDING A HIGH SPEED-LOW
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`PIN COUNT LINK by Dale E, Gulick and Larry Hewitt; and co—pending application
`
`serial no. 09/098,876 filed June 17, 1998, entitled WRITE ONLY BUS WITH
`
`WHOLE AND HALF BUS MODE OPERATION, by Larry D. Hewitt; which
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`applications are incorporated herein by reference in their entirety.
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`BACKGROUND OF THE INVENTION
`
`Field of the Invention
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`The invention relates to computer systems and more particularly to a computer
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`system having a high speed communication link having multiple pipes (channels)
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`25
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`operating on the communication link.
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`FINALAPP 0080
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`'l'I'2704-PROV
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`Attomey Docket No.:
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`lOOl-OOSO—V-US
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`Description of the Related Art
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`Traditional personal computer architectures partition the computer system into
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`the various blocks shown in the exemplary prior art system illustrated in Fig. 1. One
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`central feature of this prior art architecture is the use of the Peripheral Component
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`5
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`Interface (PCI) bus 101 as the connection between the “north bridge” integrated
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`circuit 103 and the “south bridge” integrated circuit 105. The north bridge functions
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`generally as a switch connecting CPU 107, a graphics bus 109 such as the Advanced
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`Graphics Port (AGP) bus, the PCI bus and main memory 111. The north bridge also
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`contains the memory controller function.
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`The south bridge generally provides the interface to the input/output (I/O)
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`portion of the system with the possible exception of video output as illustrated in
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`Figure 1. Specifically, the south bridge 105 provides a bridge between the PCI bus
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`and legacy PC—AT (Advanced Technology) logic. The south bridge also provides a
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`bridge to the legacy ISA bus 115, the Integrated Device Electronics (IDE) disk
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`interface 117 and the Universal Serial Bus (USB) 119. In the illustrated prior art
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`architecture, PCI bus 101 also functions as the major input/output bus for add—in
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`functions such as network connections. The various busses and devices shown in
`
`Figure 1 are conventional in the personal computer industry and are not described
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`further herein unless necessary for an understanding of the present invention.
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`In current and future personal computer systems, two basic types of data are
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`transferred between integrated circuits: isochronous data and asynchronous data.
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`Isochronous data refers to data used in real-time data streams such as audio data or
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`motion—picture video data. Asynchronous data is used for all other transfers, such as
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`central processing unit (CPU) accesses to peripherals or bulk data transmissions from
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`a hard drive into system memory.
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`The PCI bus causes a lack of determinism in the system because any function
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`on the PCI bus can become master of the bus and tie up the bus. Thus, the throughput
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`available on the bus for a particular transfer and the latency that is involved for that
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`transfer is unknown. Therefore, having a PCI bus as the major input/output bus
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`30
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`means that the major input/output bus of present day computer systems does not
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`provide proper support for both isochronous and asynchronous data. If a computer
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`Attorney Docket No:
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`system gives asynchronous data priority or treats isochronous data as asynchronous
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`data, then those functions relying on real time data, such as motion-picture video, may
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`not function satisfactorily. Alternatively, if a computer system prioritizes isochronous
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`data, then the performance of the computer system can suffer since the latency of
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`asynchronous data may become unacceptably long. As computer systems are called
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`on to perform more and more real time activity, such as real time Video, it becomes
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`more critical that asynchronous and isochronous data be treated in a manner that
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`prevents problems from occurring in the real time tasks without adversely effecting
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`other aspects of computer performance.
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`In addition, levels of integration continue to increase on as the number of
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`functions integrated onto the integrated circuits of computer systems increases, the
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`need for additional pins also increases. Supporting the host bus, the memory
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`interface, the PCI bus and a graphics interface results in a north bridge integrated
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`circuit having a relatively large number of pins that is relatively unpopulated in terms
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`of the number of transistors on the integrated circuit. The large number of pins
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`requires the integrated circuit to be larger than would otherwise be necessary and
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`therefore increases costs.
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`It would be desirable therefore, to have a deterministic high speed major
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`interconnect bus. It would also be desirable to reduce the pressure for additional pins
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`2O
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`on the integrated circuits making up the computer system.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`The present invention may be better understood, and its numerous objects,
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`features, and advantages made apparent to those skilled in the art by referencing the
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`accompanying drawings.
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`Fig. 1 shows an exemplary prior art personal computer system.
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`Fig. 2 shows a block diagram illustrating the pipe structure according to one
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`embodiment of the present invention.
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`Fig. 3 is a high level block diagram of a portion of an exemplary personal
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`computer system that utilizes the communication link described herein.
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`Fig. 4 shows an exemplary data bus and the interfaces of the communication
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`link in greater detail.
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`Fig. 5 illustrates the link layer, protocol layer and physical layer of the
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`communication link.
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`Fig. 6 shows an exemplary address map for the processor module-interface
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`module for an 'X86 environment utilizing an embodiment of the present invention.
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`Figs. 7A - 7L show the packets used in various link transactions.
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`Fig. 8 shows a flow diagram for determining a no tags free error condition.
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`Fig. 9 shows one implementation of a circuit to detect the no tags free error
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`10
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`condition.
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`Fig. 10 shows common pipe configurations used in various embodiments of
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`the present invention.
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`Fig. 11 shows a point to point pipe configuration.
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`Fig. 12 illustrates a flow diagram of a write transaction across the link.
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`Fig. 13 illustrates a target distributor pipe configuration.
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`a? r
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`Fig. 14 illustrates a flow diagram of a read transactions across the link.
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`Fig. 15 illustrates a source distributor pipe configuration.
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`Fig. 16 illustrates a target concentrator pipe configuration.
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`Fig. 17 illustrates a flow diagram of an interface module read transaction to
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`20 memory.
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`Fig. 18 illustrates the use of subordinate links in a computer system.
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`Fig. 19 illustrates a pipe structure and associated functions of a typical
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`computer system.
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`Fig. 20 illustrates one implementation of the protocol layer transmit circuit.
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`Fig. 21 illustrates one implementation of the protocol layer receive circuit.
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`Fig. 22 illustrates a pipe source circuit structure.
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`Fig. 22A illustrates a pipe source circuit structure that includes a pass through
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`Fig. 23 illustrates a non-concentrated pipe target circuit structure.
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`Fig. 23A illustrates a pipe target circuit structure that includes a pass through
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`5
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`queue.
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`queue.
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`
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`it};
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`
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`Fig. 24 illustrates a concentrated pipe target circuit structure.
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`Fig. 25 shows a block diagram of a target distributor and its connections to
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`common logic and to functions.
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`Fig. 26 illustrates additional logic used in the target concentrator to map
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`accesses to appropriate functions.
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`Fig. 27 illustrates the software structure for the capabilities pointer.
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`Fig. 28 illustrates the basic configuration structure and register addressing
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`strategy of a typical system according to one embodiment of the present invention.
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`Fig. 29 illustrates a type 1 (bridge) header.
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`Fig. 30 illustrates a type 0 (function) header.
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`Fig. 31 illustrates the upstream and downstream link registers used for link
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`bridges.
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`The use of the same reference symbols in different drawings indicates similar or
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`identical items.
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`Attorney Docket No.: 1001-0080-V-US
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`DESCRIPTION OF THE PREFERRED EMBODIMENT§SI
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`Fig. 2, illustrates a generic system according to one embodiment of the present
`
`invention. The system includes module 201 and module 203 coupled by high speed
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`link 205. High speed link 205 is in one embodiment a 10W pin count high speed point
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`to point bus (generally referred to herein as a "link" to distinguish the point to point
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`interconnect bus from a multi—drop bus) one example of which is described in
`
`application no. 09/098,874, entitled BUS OPTIMIZED FOR PERSONAL
`
`COMPUTER TRAFFIC, previously incorporated herein by reference. The term
`
`"interconnect bus“ is also used herein interchangeably with "link“ to avoid confiision
`
`when discussing the “link layer" of the communication link. Link 205 has a plurality
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`of pipes 207 — 211. Each pipe (or channel), couples a function in module 201 to a
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`function in module 203. Each pipe has a source end and a target end. For example,
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`source end 215 of pipe 207 couples function A on module 201 to the target end 221 of
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`pipe 0. The target end 221 of pipe of pipe 0 is in turn coupled to function D on
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`module 203, thereby providing a path between function A and function D.
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`A function is a circuit that provides a specific function in the computer system.
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`For example, a CPU and memory controller on a processor module are examples of
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`functions. A PCI bridge and 1394 host controller are further examples of functions on
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`an interface module. A function can have any combination of target and source pipes.
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`For example, in an exemplary system, the memory controller may only have targets,
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`the CPU may only have sources, and the PCI bridge may have both.
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`Each pipe source and pipe target communicate over bus 205 on a packet
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`multiplexed basis using packets uniquely associated with the respective pipe. Before
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`various aspects of the pipe architecture is examined in greater detail, certain details of
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`exemplary bus 205 will be discussed to provide the appropriate context for use of the
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`pipes.
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`One way to achieve high speed is to utilize a point—to-point bus in which only
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`two devices are present on the bus. A point-to-point bus can inherently run at higher
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`speeds than a multi-drop bus such as the PCI bus since a point—to—point link has
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`reduced electrical loading and reduced noise caused by reflections at tap points such
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`as connectors. It is possible to provide a point to point link that operates at, e. g., 25
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`Attorney Docket No: 1001 -0080-V-US
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`times the speed of the PCI bus. Given this, a 32-bit wide PCI bus can be replaced by
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`a 16—bit (or even an 8-bit link) while still adding significant bandwidth.
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`Referring to Fig. 3, a portion of a typical personal computer system is shown
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`which utilizes link 205 to communicate between two integrated circuits 301 and 303.
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`The computer system includes processor module 301 and interface module 303.
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`Processor module 301 includes an link interface 305 which is coupled to link interface
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`307 in interface module 303. Bus 205 provides guaranteed bandwidth and latency to
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`each isochronous stream such as RAMDAC data, audio data, and 1394 isochronous
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`streams while also attempting to minimize latency to asynchronous accesses such as
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`CPU-initiated accesses and POI—initiated accesses.
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`One feature of the architecture shown in Fig. 3 is that the PCI bus no longer
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`functions as the primary interface between the processor/memory controller and
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`input/output filnctions. Link 205 has replaced the PCI bus as the primary interface
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`and also carries both isochronous and asynchronous data.
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`The exemplary processor module 301 provides the major processing function
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`in the computer system and includes system memory controller 309, a central
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`processing unit (CPU) (such as the x86 processor AlVID K6“) and graphics interface
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`306. Interface module 303 provides an interface between various input/output devices
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`such as Video monitors, hard drives, scanners, printers, network connections, modems,
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`and the processor module. The exemplary interface module 307 includes interface
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`310 providing an interface to the industry standard architecture (ISA) bus, IEEE 1394
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`interface 312, peripheral component interface (PCI) 314, RAMDAC 316 and
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`Intelligent Drive Electronics (IDE) controller 318.
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`Exemplary link 205 connecting processor module (PM) 301 and the interface
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`module (1M) 303 includes data portion DB. Data bus DB includes two bi—directional
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`data portions. In one embodiment, each data portion contains one byte (8 bits) of
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`data. However, the number of bits on the data bus may be of size (211 —1 :0), where n is
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`an integer > 0. Thus, a minimum implementation has one data bit in each direction.
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`In the illustrated embodiment, n equals 4, with each data portion having one byte.
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`The exemplary system is divided into two sides with processor module 301
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`arbitrarily designated side A and interface module 303 designated as side B. Link 205
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`also includes a unidirectional clock line CLKB2A and a unidirectional control line
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`CTLBZA provided by link interface 307 to link interface 305. The “BZA”
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`designation indicates that the signal is an output of side B and an input to side A.
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`Link 205 also includes a second unidirectional clock line CLKA2B and a second
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`unidirectional control line CTLA2B, which are provided by processor module 301 to
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`interface module 303. The "AZB" designation indicates that the signal is an output of
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`side A and an input to side B. The protocol uses clock-forwarding technology to
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`reliably synchronize source data to a clock. CLKAZB and CLKBZA are preferably
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`derived from the same source such that they are the same frequency and they do not
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`drift.
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`Referring to Fig. 4, the data bus DB and the link interfaces are shown in
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`greater detail. Each side includes a transmit controller and a receive controller. Data
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`always flows from the transmit controller on one side to the receive controller on the
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`other side. Thus, side A link interface 305 includes transmit controller 415 and a
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`receive controller 413. Side B link interface includes transmit controller 411 and
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`receive controller 417. The two portions 407 and 409 of data bus portion DB are
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`shown with arrows indicating their direction of transfer. Data bus portion 407
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`transmits data from transmit controller 411 to receive controller 413 (from side B to
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`side A) synchronous with CLKB2A. Data portion 409 of the data bus transmits data
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`from transmit controller 415 to receive controller 417 (side A to side B),
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`synchronously with CLKAZB.
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`One main feature of bus 205 is that bus 205 provides a guaranteed minimum
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`bandwidth and a maximum latency to data transferred over the bus. That is
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`accomplished in one embodiment, as described in greater detail in application number
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`09/098,874 (BUS OPTIMIZED FOR PERSONAL COMPUTER TRAFFIC), by
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`transferring data over the high speed link in frames, with each frame guaranteeing a
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`portion of the frame for isochronous data and a portion of the frame for asynchronous
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`data. Guaranteeing maximum latency for various channels (or pipes) carried over the
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`communication link is becoming more important as isochronous data streams are
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`being conveyed between the south bridge and main memory. One source of such
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`isochronous data is the IEEE 1394 bus. In order to provide the necessary isochronous
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`bandwidth on the bus for isochronous streams, the isochronous streams are guaranteed
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`a specified amount of bandwidth during each frame on the link.
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`Maximum bandwidth requirements are specified for each isochronous stream
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`in terms of bytes per frame. The sum of the isochronous-stream maximum—bandwidth
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`requirements should be less than the theoretical total bandwidth. However, as a
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`matter of practicality, the higher the percentage bandwidth of isochronous streams,
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`the greater the probability that asynchronous traffic will incur latency. In the design
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`of a balanced system, one expects the sum of typical asynchronous bandwidth and
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`maximum isochronous bandwidth to be less than about 60 to 80 percent of the
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`theoretical maximum bandwidth. If that is done, then average latency for
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`asynchronous cycles will be minimized.
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`lsochronous requesters should not send more bytes across the link, during a
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`frame, than the programmed maximum bandwidth for that requester. Hardware may
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`be implemented in the link layer to ensure that isochronous requesters comply with
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`that requirement
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`The side A transmit controller delivers clock CLKA2B to the side B receive
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`controller, and the side B transmit controller delivers clock CLKBZA to the side A
`
`receive controller. Thus, the side A transmit controller and side B receive controller
`
`are included in the same time domain, called time domain A, and the side B transmit
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`controller and the side A receive controller are included in the same time domain,
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`called time domain B.
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`In the illustrated embodiment, it is assumed that both side A and side B
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`initialize to a mode of 16 bits wide and have an 800 megahertz data rate. The data
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`rate is based on a clock (CLK) (meaning CLKAZB and CLKB2A) rate of 400
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`megahertz with the data being provided on each edge of the clock. So, if clock is 400
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`megahertz, this represents 800 million edges per second. Address phases and data
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`phases of bus cycles transfer information at each edge of CLK. Thus, the edge rate of
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`CLK specifies the maximum theoretical bandwidth of the bus rather than the cycle
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`rate. In the illustrated embodiment, frames are several microseconds in length, e.g.
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`five microseconds.
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`Two kinds of traffic occur over bus 205: bus cycles and instant messages. The
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`greatest amount of bandwidth is used by bus cycles or transactions, which are
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`transfers of blocks of addressing information or addressing information and associated
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`data sent from one link layer to the link layer on the other side. The addressing
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`information determines where in the integrated circuit a particular access is targeted.
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`The second type of bus traffic is messages, which are used to send protocol
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`information across the link. In one embodiment, messages are aligned to the rising
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`edge of CLK and consume one CLK cycle and can occur at any time, including in the
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`middle of bus cycles.
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`Link 205 is very useful in situations where high—bandwidth asynchronous
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`traffic must be mixed with isochronous traffic. The bus protocol assumes (1) that
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`system performance is adversely affected by the latency of asynchronous traffic, (2)
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`asynchronous traffic can be delayed indefinitely without adversely affecting real-time
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`data streams, (3) isochronous traffic should be guaranteed a specified amount of
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`bandwidth and worst—case latency, and (4) as long as the bandwidth and latency
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`requirements for isochronous traffic are met, then the latency between their requests
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`and the transfer of the data has no adverse affect on system performance.
`
`The hardware on each side of the link includes a physical layer, a protocol
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`layer, and a link layer. The protocol layers for both sides of the bus include the same
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`hardware elements. In this way, the bus is symmetrical with no centralized resources
`
`(as opposed to, for example, the PCI bus arbiter which in prior art systems was
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`typically located in the north bridge of the PCI bus and arbitrates for all masters).
`
`Referring to Fig. 5, bus (or link) 205 includes link layer 501, protocol layer
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`503, and physical layer 505. The specific implementation of the physical layer
`
`depends on such factors as the frequency of the bus, the number of devices on the bus,
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`the length of the bus, as is known to those of skill in the art. The specification for the
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`physical layer and the protocol layer is generally device independent, except for
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`variations of the bus Width and frequency.
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`Attorney Docket No.: 1001 ~0080-V—US
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`In the illustrated embodiment, each channel or pipe is associated with one or
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`more functions coupled through bus 205. For example, referring again to Fig. 3,
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`processor module 301 may include separate pipes for the function CPU 311 and for
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`the function system memory controller 309. One or more pipes may be provided for
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`the various functions on the interface module 303 including 1394 host controller 312,
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`the PCI bridge 314, RAMDAC 316 and IDE controller 318. The link layer also
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`includes an arbiter 507 to determine the source of the next locally-generated bus cycle
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`since there are typically multiple asynchronous and isochronous sources. The arbiters
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`guarantee bandwidth to isochronous streams (within a maximum latency) while
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`minimizing latency to asynchronous accesses.
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`Bus traffic is grouped into frames. In an exemplary system, two counters
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`associated with frames are used in the local request arbitration logic (507 in Fig. 5).
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`They are the elapsed frame counter, which is used to specify how much bandwidth
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`remains in the frame, and the isochronous byte counter, which is used to specify how
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`much isochronous bandwidth remains to be transferred in the flame.
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`The elapsed flame counter starts, at the beginning of each flame, at a value
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`equal to the number of bytes that can be transferred across the flame (product of the
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`width of the bus in bytes and the number of clock edges in the frame). For example,
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`in a 16-bit, 800 megahertz implementation (data rate), with a two microsecond frame,
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`the value of the counter would start out at (1600 bytes per microsecond) X (2
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`microseconds per frame) = 3200. It counts down to zero over the course of the frame,
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`reloads, counts down again, and so forth. When the elapsed-frame counter reaches
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`zero, a new frame is defined to be started. This is true for both sides of the link.
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`When the elapsed frame counter reaches zero, in certain embodiments a new frame
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`(NewFrame) message to is sent across the link to side B, which causes B’s elapsed-
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`frame counter to reset.
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`The isochronous byte counter starts, at the beginning of each frame, at a value
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`equal to the number of isochronous bytes that should be guaranteed to be transferred
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`during the frame. It decrements with each isochronous byte transferred. It is
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`programmed to be slightly higher than the actual maximum isochronous bandwidth of
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`a frame. Shortly after the beginning of each flame, all the isochronous streams make
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`their requests to send data across the bus during the next frame. The requests may be
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`made in the illustrated embodiment Within a predetermined time period after the
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`frame starts.
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`Initially during a frame, asynchronous transfers are granted priority over
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`isochronous transfers (to minimize the latency of the asynchronous transfers),
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`(asynchronous priority mode). However, counter(s) track of how much isochronous
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`traffic passes during the frame and if the isochronous streams are in danger of running
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`out of the required bandwidth for the frame, arbitration priority switches to the
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`isochronous traffic, (isochronous—priority mode). In that way, a minimum amount of
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`isochronous bandwidth can be guaranteed while minimizing latencies for
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`asynchronous transfer requests. After all the isochronous bus cycles for the frame are
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`complete (which occurs before the end of the frame), the priority switches back to the
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`asynchronous traffic.
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`The local request arbiter operates as follows. At the beginning of each frame,
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`all isochronous streams that will require bandwidth during the frame request the link
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`fiom the local-request arbiter. They continue to request the link until they have
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`completed all of their bus cycles for the frame.
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`Typically, the total requested bandwidth for the vast majority of frames will be
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`well under 100%. Generally, asynchronous transfers will be granted highest priority
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`for the entire frame because of generally low rates of isochronous traffic relative to
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`the available bandwidth on the link. Thus, as described above, asynchronous CPU
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`accesses will most often be granted higher priority than isochronous transfers and
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`therefore incur reduced average latency. In situations Where large blocks of bulk
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`asynchronous data are being transferred across the link (for example, from the PCI
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`bus), then the isochronous transfers will tend to come at the end of the frame, after the
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`priority has switched to isochronous bus cycles. In this case, CPU latency will tend to
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`increase as the CPU loses priority to the isochronous bus cycles and contends with the
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`bulk asynchronous transfers.
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`For each frame, the link either stays in asynchronous priority mode for the
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`entire frame or (1) starts in asynchronous priority mode, (2) transitions to isochronous
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`priority mode during the frame, and (3) then transitions again to asynchronous priority
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`mode before the end of the frame.
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`In one implementation, the rules for the local—request arbiter are:
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`asynchronous requesters are higher priority than isochronous requesters during
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`asynchronous-priority mode and only isochronous requesters are granted bus cycles
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`during isochronous—priority mode. The arbitration method for the group of
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`asynchronous requesters is not limited other than it is required to be fair and to not
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`cause deadlock situations. The arbitration scheme for the group of isochronous
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`requesters may utilize a fixed priority scheme.
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`Detailed implementation of one embodiment of transmit and receive circuits in
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`the protocol layer is described further herein. However, first the utilization of the
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`high speed link will be examined in greater detail beginning with the transaction
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`protocol. As described with relation to Fig. 2, the link includes a plurality of pipes,
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`each pipe sharing the bus in a time division multiplexing scheme. The basic function
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`of pipes is to carry transactions. The transactions can be reads, writes, or both. In one
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`embodiment, reads and writes are carried across the link as memory-mapped
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`transactions to a 40-bit address space.
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`Each transaction includes a command and response packet. There are multiple
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`types of command and response packets. A packet type field within each packet
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`identifies the type of packet. It is advantageous if the first byte of the packet
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`identifies a destination queue. That provides a particular advantage when the link is
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`only 8—bits wide since the first byte contains necessary routing information.
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`Otherwise, in an 8—bit link implementation, the target would have to wait for the
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`second byte to determine the appropriate destination.
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`Thus, in one embodiment, the first 8—bits of the packet include a 5—bit Pipe
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`Identification (ID) field and the first 3-bits of a 6—bit Packet Type field. The Pipe ID
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`field, which identifies the pipe on which the transaction is being carried, is used to
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`route the packet to the correct pipe hardware and the first 2—bits of the Packet Type
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`field identify the correct queue Within the pipe hardware. The pipe hardware includes
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`are Command, Response, Write Data, and Read Data queues. The first bit (bit 0) of
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`Attorney Docket No.:
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`the packet type field specifies whether the packet is a Command (0) from the source
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`or Response (1) from the target. The second most significant bit (bit 1) specifies
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`whether the operation is a Read (0) or Write (1) operation. The packet types for the
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`command packets sent from the source to the target are shown in Table 1.
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`Ml
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`Packet Type Code Command
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`The response packets sent from a source to a target in response to a command
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`are shown in Table 2.
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`Packet TJ'e Code
`.1 .
`____________________ 100999” Readtssapsase.
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`.. 11000901 _ NQnrAdétssssdread resnmise
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`...1..QQQ_1.O Rsadrsispt,
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`.
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`Reserved
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`" ib'i'i’iil 100011’
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`.””110009.Writseckmwlcdgg ..
`N m0..r_lru;100911
`WfitanegaireAChflswledge, .
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`111111 - 111010 Reserved
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`Transactions across the bus may be pipelined. The pipeline structures may
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`support two different kinds ofpipelining, “in order” and “out of order” transactions.
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`In order pipelining means that multiple transactions can be outstanding, but they are
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`strictly ordered, i.e., they are responded to by the target in the exact order that they
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