United States Patent (19)
`Hart et al.
`
`US006041372A
`Patent Number:
`11
`(45) Date of Patent:
`
`6,041,372
`Mar. 21, 2000
`
`54 METHOD AND APPARATUS FOR
`PROVIDING A PROCESSORMODULE FOR
`A COMPUTER SYSTEM
`
`(75) Inventors: Frank P. Hart, Beaverton; Ravi
`
`Nagaraj, Hillsboro; James L. Noble
`s
`s
`s
`Portland, all of Oreg; Neil W. Songer,
`Santa Clara, Calif.
`73 Assignee: Intel Corporation, Santa Clara, Calif.
`
`21 Appl. No.: 08/774,515
`22 Filed:
`Dec. 30, 1996
`51
`Int. Cl." .............................. G06F 13/10; H03K 5/09
`52 U.S. Cl. ............................ 710,62, 710/101: 307/475.
`326/37
`58 Field of Search ............................ 395.500 348,243.
`307/475; 326/37; 710/62, 101, 1
`References Cited
`
`56)
`
`U.S. PATENT DOCUMENTS
`4,872,213 10/1989 Sebald et al. ........................... 364/180
`5,023,488 6/1991 Gunning ...
`... 307/475
`5,162,676 11/1992 Aoki et al. ...
`... 307/475
`5,210,858 5/1993 Jensen et al. .
`... 395/550
`5,297.272 3/1994 Lu et al. ...
`... 395/500
`5,321,827 6/1994 Lu et al. .......
`... 395/500
`5,404,559 4/1995 Bonella et al. ...
`... 395/800
`5,410,726 4/1995 Baqai et al. ......
`395/800
`5,440,244 8/1995 Richter et al. ............................ 326/37
`5.444.298 8/1995 Schutz ...........
`... 257/691
`5,455,927 10/1995 Huang ..................................... 395/500
`5,473,766 12/1995 Shaver .................................... 395/500
`
`5,490,279 2/1996 Golbert et al. .......................... 395/800
`5,493,655 2/1996 Shen et al. ...
`395/280
`5,513.329 4/1996 Pecone ............
`... 395/281
`5.530,620 6/1996 Sangveraphunsiri.................... 361/686
`
`5,551,012 8/1996 Chuang et al. - - - - - - - - - - - - - - - - - - - - - - - - - 395/500
`
`5,554,947 9/1996 Saitou et al. ............................ 327/184
`5,559,966 9/1996 Cho et al. ............................... 395/285
`5,586,270 12/1996 Rotier et al. .
`395/282
`5,600,267 2/1997 Wong et al. .
`... 326/73
`5,604.871 2/1997 Pecone .................................... 395/281
`5,611,046 3/1997 Russell et al.
`... 395/200.1
`5,617,546 4/1997 Shih et al. .............................. 395/307
`5,625,802 4/1997 Cho et al. ...
`395/500
`5,627,413 5/1997 Mughir et al...
`... 307/86
`5,640,536 6/1997 King et al. ...
`395/500
`5,644,760 7/1997 Polzin et al. ............................ 395/555
`Primary Examiner-Thomas C. Lee
`ASSistant Examiner-Rehana Perveen
`Attorney, Agent, or Firm—David J. Kaplan
`57
`ABSTRACT
`A method and apparatus for converting a signal from a first
`Voltage level to a Second Voltage level before providing the
`Signal to a processor. A circuit board includes an interface
`for coupling the circuit board to a peripheral Subsystem via
`a Socket. The circuit board also includes a processor that
`receives Signals of a first voltage level, a first signal line, and
`a Second Signal line. The first signal line is coupled to the
`interface and provides a reference signal to the peripheral
`Subsystem that indicates the first Voltage level. The Second
`ignal line is also coupled to the interface and provides a
`Signal line is a
`p
`p
`Subsystem Signal back from the peripheral Subsystem after
`the Signal has been converted to the first Voltage level.
`
`14 Claims, 4 Drawing Sheets
`
`2 2 O
`
`PROCESSOR
`
`200
`
`WOLTAGE
`REG.
`O
`
`
`
`
`
`BRIDGEA
`203
`
`
`
`- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`. V23
`
`
`
`
`
`MEMORY
`
`PCCLOCK
`SIGNAL
`
`222
`
`AGENT
`
`AGENT2
`
`l
`
`BRIDGEB
`
`205
`
`
`
`
`
`AGNT3
`
`AGENT 4
`
`210
`
`221
`
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`U.S. Patent
`
`Mar. 21, 2000
`
`Sheet 1 of 4
`
`6,041372
`
`E
`PROCESSOR
`100
`108
`
`
`
`
`
`VOLTAGE
`REGULATOR
`101
`
`
`
`
`
`
`
`
`
`
`
`PC CLOCK
`SIGNAL
`
`AGENT 1
`
`
`
`AGENT 3
`
`AGENT 4
`
`110
`
`FIG. 1
`(PRIOR ART)
`
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`U.S. Patent
`
`Mar. 21, 2000
`
`Sheet 2 of 4
`
`6,041372
`
`
`
`
`
`
`
`PROCESSOR
`
`VOLTAGE
`REG.
`201
`
`a still a
`
`a
`
`a - r - - - - - - -
`
`
`
`
`
`
`
`AGENT 1
`
`
`
`
`
`AGENT 3
`
`AGENT 4
`
`V23
`
`210
`
`PC CLOCK
`SIGNAL
`
`221
`
`FIG.2
`
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`U.S. Patent
`
`Mar. 21, 2000
`
`Sheet 3 of 4
`
`6,041372
`
`
`
`
`
`
`
`
`
`PROCESSOR
`
`
`
`300
`
`VOLTAGE
`REG.
`301
`
`BRIDGE
`303 O
`
`F - - - - a
`
`w re
`
`r u
`
`us
`
`a
`
`- - - - - - - - -
`
`as
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`V33
`
`
`
`
`
`MEMORY
`304
`
`PC CLOCK
`SIGNAL
`
`310
`
`
`
`
`
`
`
`
`
`AGENT 1
`
`AGENT2
`
`BRIDGE B
`
`305
`
`
`
`AGENT 3
`
`AGENT 4
`
`321
`
`FIG. 3
`
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`U.S. Patent
`
`Mar. 21, 2000
`
`Sheet 4 of 4
`
`6,041372
`
`
`
`INSERT THE PROCESSOR
`MODULE INTO THE SYSTEM
`SOCKET
`400
`
`PROVIDE THE SYSTEM
`WITH A REFERENCESIGNAL
`FROM THE PROCESSOR
`MODULE INDICATING THE
`INPUT VOLTAGE LEVEL
`THAT THE PROCESSORS
`CONFIGURED TO RECEIVE
`401
`
`CONVERT A SIGNAL FROM
`ONE VOLTAGE LEVEL TO
`THE DIFFERENT, INPUT
`VOLTAGE LEVEL THE
`CONVERSION TAKING
`PLACE IN THE SYSTEM
`402
`
`PROVIDE THE PROCESSOR
`ON THE PROCESSOR
`MODULE WITH THE
`CONVERTED SIGNAL
`403
`
`FIG. 4
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`1
`METHOD AND APPARATUS FOR
`PROVIDING A PROCESSOR MODULE FOR
`A COMPUTER SYSTEM
`
`FIELD OF THE INVENTION
`The present invention relates to computer Systems and
`more particularly to a method and apparatus for converting
`a signal from a first voltage level to a Second Voltage level
`before providing the Signal to a processor.
`
`BACKGROUND OF THE INVENTION
`At the current pace of technological innovation, an elec
`tronic device purchased today will likely become obsolete
`within the next couple of years. This presents a frustrating
`dilemma to consumers. Rapid obsolescence is perhaps
`nowhere more apparent than in the personal computer
`market Segment. With new generations of more powerful
`computers being released every six months to a year, a
`consumer is wary of paying a premium for a top-of-the-line
`computer System knowing that in less than a year's time, the
`Same computer will be considered old technology, available
`to consumers at less than half its retail price at introduction.
`One way a consumer can protect their investment in a
`computer System is to purchase a System having a processor
`that can be upgraded. For example, a consumer could
`purchase a 486-based computer System operating at 66
`MHZ, and later, if more power is desired, upgrade their
`processor to for example, a 100 MHz 486 processor. For
`desktop personal computer Systems, a consumer may also be
`able to upgrade their 486 processor-based System to a more
`powerful, compatible, next generation processor Such as a
`Pentium(R) processor, available from Intel Corporation of
`Santa Clara, Calif. In this manner, Some portion of a
`consumers initial investment in their desktop computer
`System is Salvaged because the consumer need only pur
`chase a more powerful processor to upgrade their computer
`System rather than purchasing an entirely new computer
`System.
`Unfortunately, mobile computer Systems are not as easily
`upgradable. Mobile computer Systems include, for example,
`notebook computers, laptop computers, and personal data
`assistants. In the interest of Saving Space, the processor,
`chipset, memory, and various other primary components of
`the mobile computer System are highly integrated. This high
`degree of integration makes upgrading any one component
`of the mobile computer System, Such as the processor,
`technically challenging and expensive, particularly for an
`upgrade from one processor generation to the next.
`For example, FIG. 1 is a prior art computer System in
`which processor 100 is coupled to and communicates with
`the primary bridge, bridge A103, via host bus 108. Bridge
`103 couples processor 100 to peripheral component inter
`connect (PCI) bus agents 1 and 2 by coupling host bus 108
`to PCI bus 106, to which the bus agents are coupled. The PCI
`protocol is described by the PCI Local Bus Specification,
`Revision 2.0 (1993), and Revision 2.1 (1995). In addition,
`bridge 103 couples processor 100 and PCI bus agents 1 and
`2 to memory 104 by coupling host bus 108 and PCI bus 106
`to memory bus 109, to which memory 104 is coupled. In this
`manner, bridge 103 enables three-way communication
`between memory 104, processor 100, and PCI agents 1 and
`2. Clock 102 is coupled to and provides clock Signals to
`processor 100, primary bridge 103, and PCI agents 1 and 2.
`A secondary bridge, bridge B 105, is coupled to PCI bus 106
`and to secondary bus 107, enabling communication between
`Secondary buS agents 3 and 4, coupled to Secondary bus 107,
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`and the rest of the computer System. Secondary bus bridge
`105 is also coupled to processor 100 by way of signal line
`110. Also, voltage regulator 101 is coupled to and provides
`a Voltage Supply to processor 100.
`Upgrading processor 100 to a faster processor in the same
`processor family is simply a matter of removing the old
`processor and inserting a new processor into the same
`Socket. Upgrading to a next generation processor family,
`however, is more involved. To effectively upgrade the com
`puter System of FIG. 1 to a next generation processor family,
`processor 100, primary bridge 103, and possibly clock 102
`and Voltage regulator 101 may need to be replaced. Sec
`ondary bridge 105 may also need to be replaced if its output
`Voltage levels along Signal line 110 are not compatible with
`the upgraded processor's input Voltage level Specifications.
`Replacement of all of these components in a mobile System
`may wind up costing more than the System itself is worth. In
`addition, the interconnect routings between these compo
`nents and their corresponding Sockets may not Support an
`upgrade.
`
`SUMMARY OF THE INVENTION
`A method and apparatus is described for converting a
`Signal from a first voltage level to a Second Voltage level
`before providing the Signal to a processor. A circuit board
`includes an interface for coupling the circuit board to a
`peripheral Subsystem via a Socket. The circuit board also
`includes a processor that receives signals of a first voltage
`level, a first Signal line, aid a Second Signal line. The first
`Signal line is coupled to the interface and provides a refer
`ence Signal to the peripheral Subsystem that indicates the
`first voltage level. The Second Signal line is also coupled to
`the interface and provides a peripheral Subsystem signal
`back from the peripheral Subsystem after the Signal has been
`converted to the first voltage level.
`Other features and advantages of the present invention
`will be apparent from the accompanying drawings and the
`detailed description that follows.
`BRIEF DESCRIPTION OF THE DRAWINGS
`The present invention is illustrated by way of example
`and not limitation in the figures of the accompanying
`drawings in which like references indicate Similar elements
`and in which:
`FIG. 1 is a prior art computer System;
`FIG. 2 is a computer System formed in accordance with
`one embodiment of the present invention;
`FIG. 3 is a computer system formed in accordance with
`another embodiment of the present invention; and
`FIG. 4 is a flow chart showing a method of the present
`invention.
`
`DETAILED DESCRIPTION
`A method and apparatus is described for converting a
`Signal from a first voltage level to a Second Voltage level
`before providing the Signal to a processor. A circuit board of
`a processor module includes an interface for coupling the
`circuit board to a peripheral Subsystem via a Socket. In one
`embodiment of prevent invention, the circuit board also
`includes a processor, a Voltage regulator, and a primary
`bridge. The processor of the circuit board is designed to
`receive signals of a specified input-output (I-O) voltage
`level, and the Voltage regulator is coupled to the processor
`to provide the processor with a Voltage Supply equal to the
`Specified I-O Voltage level. The processor module is coupled
`
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`3
`to a mobile System by plugging the circuit board into a
`Socket of the System, mating the interface to the Socket. The
`peripheral Subsystem includes a voltage conversion circuit
`that converts Signals from a first voltage to a Second Voltage,
`the Second Voltage being determined by a reference Signal
`applied to the Voltage conversion circuit.
`A Voltage reference Signal line couples the Voltage regul
`lator of the processor module circuit board, through the
`Socket interface, to the Voltage conversion circuit. This
`reference Signal line provides the reference Signal from the
`Voltage regulator that the conversion circuit uses to convert
`Signals to the I-O Voltage levels. A Subsystem Signal that
`originates from the peripheral Subsystem, Such as a signal
`from a Secondary bridge, is converted from the peripheral
`Subsystem Voltage level to the processor I-O Voltage level by
`the Voltage conversion circuit. A signal line that couples the
`conversion circuit to the processor through the Socket inter
`face then provides the converted Subsystem signal to the
`processor. In addition, other Subsystem signals Such as, for
`example, a clock Signal from a clock residing in the periph
`eral Subsystem, may similarly be converted to the processor
`I-O Voltage level before being provided along a clock signal
`line through the Socket interface to the processor of the
`processor module circuit board.
`By providing the Voltage reference signal line from the
`processor module to th(e Voltage conversion circuit of the
`peripheral Subsystem, Voltage conversion of Subsystem Sig
`nals from System Voltage levels to processor I-O Voltage
`levels takes place before the Subsystem signals reach the
`processor module. In this manner, Signal timings, which are
`related to the Signal Voltage levels, are maintained to tight
`skew tolerances. A more detailed description of the present
`invention, including various configurations and implemen
`tations in accordance with alternate embodiments, of the
`present invention, is provided below.
`FIG. 2 is a computer System formed in accordance with
`one embodiment of the present invention in which an
`electronic component referred to as a processor module 220
`includes a circuit board containing processor 200, Voltage
`regulator 201, primary bridge A203, clock 202, and asso
`ciated Signal lines and interfaces. Processor module 220
`includes an interface that is inserted into System Socket 223,
`thereby coupling the Signal lines of the circuit board of
`processor module 220 to corresponding Signal lines of a
`peripheral Subsystem comprising one or more Separate cir
`cuit boards that contain System memory 204, buS agents 1-4,
`secondary bridge B205, and voltage conversion circuit 221.
`Processor 200 is coupled to primary bridge 203 by way of
`host bus 208. Voltages regulator 201 is coupled to and
`provides a voltage supply to processor 200, and clock 202 is
`coupled to and provides a clock signal to processor 200 and
`to bridge 203. Primary bridge 203 is also coupled to two
`other buses, peripheral component interconnect (PCI) bus
`206 and memory bus 209. The signal lines that make up PCI
`bus 206 couple primary bridge 203, through system socket
`interface 223, to PCI bus agents 1 and 2 as well as to
`secondary bridge 205. Memory bus 209 couples bridge 203,
`through System Socket interface 223, to System main
`memory 204. Clock 202 includes a clock signal output that
`provides a PCI clock signal to PCI bus agents along the PCI
`clock signal line that extends from clock 202, across the
`System Socket interface 223, to the peripheral Subsystem
`Side comprising the circuit boards containing PCI bus agents
`1 and 2.
`Secondary bus bridge 205 is coupled to bus agents 3 and
`4 by way of secondary bus 207. Bridge 205 is also coupled
`
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`to processor 200, through interface 223, by Subsystem signal
`line 210. A voltage conversion circuit 221 is included on
`Subsystem signal line 210, between secondary bridge 205
`and processor 200, on the peripheral Subsystem side of the
`Subsystem Signal line. The peripheral Subsystem side of the
`computer system of FIG. 2 is the portion of the computer
`System external to the processor module (the portion of FIG.
`2 that is below socket interface 223). In addition, voltage
`regulator 201 is coupled to Voltage conversion circuit 221 by
`Voltage reference Signal line 222, bridging the processor
`module circuit board to the circuit board containing Voltage
`conversion circuit 221 by way of System Socket interface
`223.
`For one embodiment of the present invention, the System
`of FIG. 2 is implemented in a mobile computer system. For
`another embodiment, the System is implemented in another
`type of computer System Such as, e.g., a desktop computer
`System or a server.
`Processor 200, along with the other components included
`on processor module 220, communicates with the rest of the
`computer System, on the peripheral Subsystem Side, through
`a Socket 223 that couples an interface of exposed electrical
`contact regions located at an edge of the circuit board of
`processor module 220 to a Second circuit board. By placing
`processor 200 on a peripheral circuit board in this manner,
`rather than directly on the motherboard, the need for pin
`compatibility between processor generations is reduced.
`This is because Specified Signal lines of the peripheral
`Subsystem are coupled to corresponding Signal lines on the
`processor module Via the interface, and these signal lines are
`then routed in the desired manner on the processor module
`to the appropriate I-O pins of the processor. This way, not
`only can different processor speeds and generations having
`different I-O pin definitions be made compatible with a
`Single Socket interface but also different processor packag
`ing technologies can be explored on different processor
`modules, while Socket interface compatibility is maintained.
`Therefore, in accordance with an embodiment of the present
`invention, a user can upgrade or modify a computer System
`by Simply Swapping one processor module for another,
`without concern for matching the pinout or packaging
`technologies from one processor to another.
`The Voltage level of a signal is the magnitude of the
`nominal high voltage (the specified “on” state) minus the
`nominal low voltage (the specified “off” state). This is the
`difference in Voltages corresponding to a logical “1” and a
`logical “0”. For an embodiment in which the low voltage
`value is 0 V (ground), the Voltage level is equal to the
`defined nominal high Voltage.
`Voltage regulator 201 provides processor 200 with a
`Voltage Supply.
`For one embodiment of the present invention, the Voltage
`supply provided by voltage regulator 201 is at the I-O
`voltage level (the voltage level for which the processor's I-O
`pins are specified). In accordance with a mobile
`environment, this voltage is typically 3.3 V or 2.5 V, but this
`value continues to decrease with each new processor gen
`eration. For embodiments of the present invention in which
`the processor requires Voltage Supplies of two or more
`different Voltages, Such as, for example, when the proces
`Sor's core operates at a lower Voltage than its I-O Voltage
`level, the Voltage regulator on the processor module may
`provide these additional Voltage Supplies as well. By includ
`ing Voltage regulator 201 on processor module 220, one can
`ensure that the Voltage regulator output Voltage always
`properly matches the requirements of the processor and
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`S
`other components of the processor module, and is coupled to
`the proper pins. This allows a computer System to be
`upgraded or modified by Simply Swapping one processor
`module for another, without concern for processor I-O
`Voltage levels or attempting to match the Voltage levels and
`Signal lines of the computer System to the processors and
`components being upgraded.
`Primary bridge 203 translates signals between the signal
`lines that make up host bus 208, PCI bus 206, and memory
`bus 209. This allows three-way communication between
`processor 200, memory 204, and any components coupled to
`PCI bus 206, including agents 1 and 2 and secondary bridge
`205. For one embodiment of the present invention, the
`interface between bridge 203 and processor 200 along the
`hostbus (also known as a System bus, processorbus, or local
`bus) is unique to each processor/bridge pair. Conversely,
`PCI bus 206 and memory bus 209 operate on well specified
`protocols that are consistent acroSS processor and bridge
`generations. By including primary bridge 203 together with
`its matching processor 200 on processor module 220, one
`can ensure that the bridge always properly communicates
`with the processor across the host bus. This allows a
`computer System to be upgraded or modified by Simply
`Swapping one processor module for another, without con
`cern for attempting to match the processor to a correspond
`ing bridge, while keeping PCI and memory bus protocols
`consistent.
`Clock 202 provides processor 200 and primary bridge 203
`with a clock signal. In addition, clock 202 provides a PCI
`clock signal acroSS Socket interface 223 to PCI agents 1 and
`2, and to secondary bridge 205. For one embodiment of the
`present invention, the clock signal provided to processor 210
`and to bridge 203 is 60 or 66 MHz. The clock signal
`provided to components coupled to PCI bus 206, including
`bridges 203 and 205, and agents 1 and 2, is 30 or 33 MHz.
`For an embodiment of the present invention in which the
`clock Signal is provided to an input pin of processor 200, the
`Voltage level of the clock signal provided to the processor
`matches the voltage level that processor 200 is designed for.
`For one embodiment, the PCI clock signal voltage level is
`different from the voltage level of the signal provided to the
`processor, and is approximately 3.3 V in a mobile computer
`System. For an embodiment of the present invention imple
`mented in a more advanced computer System, the clock
`Signal is faster. By including clock 202 together with bridge
`203 and processor 200 on processor module 220, one can
`ensure that the included clock is properly designed to
`Support the associated processor and bridge. This allows a
`computer System to be upgraded or modified by a user by
`Simply Swapping one processor module for another, without
`concern for determining and accounting for the proper clock
`Speed and Voltage levels.
`Memory 204 comprises Several dynamic random acceSS
`memory (DRAM) semiconductor components which do not
`require a clock signal. An embodiment in which Synchro
`nous DRAM (SDRAM) memory components are
`implemented, requiring the application of a clock signal to
`achieve Synchronization, is described below in conjunction
`with FIG. 3.
`PCI bus agents 1 and 2 coupled to PCI bus 206 are
`peripheral devices compliant with the PCI bus protocol, and
`communicate with other components of the computer Sys
`tem including, for example, processor module 220. For one
`embodiment of the present invention, PCI bus agents 1 and
`2 include a graphics card, Video capture device, or other
`device that requires close proximity to the processor. For
`another embodiment of the present invention, PCI bus
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`agents are PCcard or CardbuS Sockets into which a user
`inserts compatible peripheral devices.
`Secondary bridge 205 translates Signals between the Sig
`nal lines that make up PCI bus 206 and secondary bus 207.
`This allows devices above secondary bridge 205, including
`PCI bus agents 1 and 2, memory 204, and processor 200, to
`communicate with devices coupled to secondary bus 207,
`including Secondary buS agents 3 and 4. For one embodi
`ment of the present invention, secondary bus 207 is another
`PCI bus. For are alternate embodiment of the present
`invention, the Secondary bus conforms to an alternate type
`of bus architecture including, for example, IDE, ISA, or
`universal serial bus (USB). In addition to bridging PCI bus
`206 to secondary bus 207, secondary bridge 205 sends
`Subsystem signals directly to processor 200, along Sub
`System signal line 210. Subsystem Signals are signals that
`are provided from the peripheral Subsystem to the processor
`module, other than those Signals provided along the PCI or
`memory buses. For one embodiment of the present
`invention, these Signals include, for example, clock signals,
`processor reset, co-processor error, initialization, processor
`interrupt, reset processor input, sleep, System management
`interrupt, and Stop clock. In accordance with an embodiment
`of the present invention, these Subsystem Signals are pro
`Vided to and are used by other System resources as well.
`Voltage conversion circuit 221 receives Subsystem signals
`provided by Secondary bridge 205 along Subsystem signal
`line 210, and converts the voltage level of these subsystem
`Signals to a Voltage level indicated by the Voltage reference
`Signal provided by reference Signal line 222. This is done to
`maintain the proper timing between the peripheral Sub
`System and the processor. Signal timing is a function of
`voltage levels. The Voltage levels of the Subsystem signals
`provided by bridge 205 are converted to processor I-O
`Voltage levels before the Subsystem signals reach processor
`module 220 along Signal line 210. By using Voltage con
`version circuit 221 to convert the Subsystem signals on the
`peripheral Subsystem Side, rather than waiting until those
`Signals reach the processor module, proper timing between
`the Subsystem Signals, components coupled to Signal line
`210 on the peripheral Subsystem side, and processor 200 is
`achieved. This is particularly important for embodiments in
`which tight skew tolerances between clocked Signals must
`be achieved.
`For the embodiment of the present invention shown in
`FIG. 2, the Voltage reference Signal is provided by Voltage
`regulator 201 along Signal line 222. For one embodiment,
`the Voltage reference Signal is a voltage level that is approxi
`mately equal to the I-O Voltage level provided by Voltage
`regulator 201. For this embodiment, a suitable voltage
`conversion circuit may be a buffer circuit, the Voltage Supply
`for which is provided by reference signal line 222 from
`Voltage regulator 201. For another embodiment, the Voltage
`reference Signal is a binary Signal that indicates the appro
`priate Voltage to circuitry within the Voltage conversion
`circuit, and the Voltage conversion circuit then converts the
`Subsystem signal to the proper Voltage level according to
`this signal. In accordance with an alternate embodiment of
`the present invention, the Voltage reference Signal is not
`provided by the voltage regulator but rather by a different
`component on the processor module Such as, for example,
`the processor or bridge.
`For an alternate embodiment of the present invention,
`Subsystem signals other than those provide by the Secondary
`bridge are similarly converted to the desired Voltage levels
`on the peripheral Subsystem side before reaching the pro
`ceSSor module. For another embodiment, these Subsystem
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`Signals are provided to components on the processor module
`other than the processor. By providing the Voltage reference
`Signal from the processor module indicating the proper
`target Voltage level to a Voltage conversion circuit, one can
`ensure that the Subsystem signals provided to the processor,
`or other components of the processor module, are properly
`Synchronized and at the proper Voltage levels. This allows a
`computer System to be upgraded or modified by a user by
`Simply Swapping one processor module for another, without
`concern for changes in processor I-O Voltage levels and
`Signal timings.
`FIG. 3 is a computer system formed in accordance with
`another embodiment of the present invention in which a
`processor module 320 includes a circuit board containing
`processor 300, voltage regulator 301, bridge A303, and the
`asSociated Signal lines and interfaces. Processor module 320
`includes an interface that is inserted into System Socket 323,
`thereby coupling the Signal lines of the circuit board of
`processor module 320 to corresponding Signal lines of a
`peripheral Subsystem comprising one or more Separate cir
`cuit boards that contain System memory 304, buS agents 1-4,
`bridge B305, clock 302, and voltage conversion circuit 321.
`Processor 300 is coupled to primary bridge 303 by way of
`host bus 308. Voltage regulator 301 is coupled to and
`provides a voltage supply to processor 300. Primary bridge
`303 is also coupled to two other buses, PCI bus 306 and
`memory bus 309. The signal lines that make up PCI bus 306
`couple primary bridge 303, through System Socket interface
`323, to PCI bus agents 1 and 2 as well as to secondary bridge
`305. Memory bus 309 couples bridge 303, through system
`socket interface 323, to system main memory 304. Clock
`302 includes a clock signal output that provides a PCI clock
`Signal to the PCI bus and another clock signal output that is
`coupled to and provides a clock signal to System main
`memory 304. Clock 302 also provides clock signals across
`a clock signal line that extends from clock 302, acroSS
`system socket interface 323, to processor 300 and bridge 303
`of processor module 320.
`Secondary bus bridge 305 is coupled to bus agents 3 and
`4 by way of secondary bus 307. Bridge 305 is also coupled
`to processor 300, through interface 323, by Subsystem signal
`line 310. A voltage conversion circuit 321 included on
`Subsystem signal line 310, between secondary bridge 305
`and processor 300, on the peripheral Subsystem side of the
`Subsystem Signal line. In addition, Voltage regulator 301 is
`coupled to voltage conversion circuit 321 and to clock 302
`by Voltage reference Signal line 322, bridging the processor
`module circuit board to the circuit board containing Voltage
`conversion circuit 321 and the circuit board containing clock
`302 by way of system socket interface 323.
`For cone embodiment of the present invention, the System
`of FIG. 3 is implemented in a mobile computer system. For
`another embodiment, the System is implemented in a desk
`top computer System or in a Server.
`The computer system of FIG.3 operates in much the same
`way that the computer System of FIG. 2 operates, the
`primary difference being that clock 302 provides clock
`signals to processor 300, bridge 303, and PCI components
`from the peripheral Subsystem side (i.e. is a Subsystem
`signal) rather than from processor module 320. In addition,
`for the embodiment shown in FIG. 3, memory 304 com
`prises SDRAM components, requiring that a clock signal be
`provided to memory 304 from clock 302, as shown. As
`Stated above, Signal timing is a function of Voltage levels.
`Therefore, to reduce the clock skew between processor 300
`and memory 304, the voltage level of the clock signal
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`provided to processor 300 is converted by voltage conver
`sion circuitry within clock 302 according to the reference
`Voltage provided along Signal line 322. This ensures that the
`tight skew tolerances required by SDRAM components are
`met.
`FIG. 4 is a flow chart showing one method of the present
`invention. At step 400 a processor module is inserted into a
`Socket coupled to another circuit board of a peripheral
`Subsystem. For one embodiment of the present invention
`this processor module includes a clock, processor, bridge,
`and Voltage regulator. For another embodiment of the
`present invention, th(e processor module has no clock. For
`an alternate embodiment of the present invention, the pro
`ceSSor module additionally includes a level-2 cache.
`At Step 401 a reference Signal is provided to the peripheral
`Subsystem from the processor module, the reference Signal
`indicating the input voltage level that the processor is
`configured to receive. This input voltage level is, for
`example, the I-O Voltage level of the processor. For one
`embodiment of the present invention, the Voltage of the
`reference Signal is equal to the input Voltage level. For
`another embodiment of the present invention, the Voltage of
`the reference Signal is a value that is related to the input
`Voltage level by a known function, So that given this
`reference Signal, the peripheral Subsystem can determine the
`proper input voltage level.
`At Step 402 a Subsystem signal is converted from a System
`Voltage level to the processor I-O Voltage level on the
`peripheral Subsystem side. A Subsystem signal is a signal
`that is generated on the p