Dec. 13, 1960
`
`Filed Nov. 15, 1956
`
`
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`FIG.
`
`H. S. YoURKE
`TRANSISTOR SWITCHING CIRCUITS
`
`2,964,652
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`4. Sheets-Sheet
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`r
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`INVENTOR.
`HANNON S. YOUR KE
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`BY
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`AGENT
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`SAMSUNG
`EX 1028, PAGE 1
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`

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`Dec. 13, 1960
`
`H. S. YOURKE
`TRANSISTOR SWITCHING CIRCUITS
`
`Filed Nov. 5, 1956
`FIG, 4.
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`2,964,652
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`4. Sheets-Sheet 2
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`SAMSUNG
`EX 1028, PAGE 2
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`Dec. 13, 1960
`
`H. S. YOURKE
`TRANSISTOR SWITCHING CIRCUITS
`
`Filed Nov. 15, 1956
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`
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`2,964,652
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`4. Sheets-Sheet 3
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`SAMSUNG
`EX 1028, PAGE 3
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`Dec. 13, 1960
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`Filed Nov. 5, 1956
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`H. s. YoURKE
`TRANSISTOR SWITCHING CIRCUITS
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`2,964,652
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`4. Sheets-Sheet 4
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`United States Patent
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`
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`2,964,652
`Patiented Dec. 3, 2960
`
`2,964,652
`TRANSSTOR SWITCHENG CIRCUITS
`Hannon S. Yourke, Poughkeepsie, N.Y., assignor to Inter
`national Business Machines Corporation, New York,
`N.Y., a corporation of New York
`Filed Nov. 15, 1956, Ser. No. 622,307
`18 Claims. (C. 307-88.5)
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`Still another object is to provide a transistor switching
`system wherein all elements are directly coupled.
`Still another object is to provide a transistor switching
`System wherein the individual stages of the switching sys
`ten are not interdependent with respect to loading.
`Still another object is to provide a transistor switching
`System wherein the load on the power supplies is essen
`tially constant.
`A related object is to provide a transistor switching
`circuit using a minimum number of supply voltages.
`Another related object is to provide a transistor switch
`ing System operating above cut off and below saturation.
`Other objects of the invention will be pointed out in
`the following description and claims and illustrated in
`the accompanying drawings, which disclose, by way of
`example, the principle of the invention and the best mode,
`which has been contemplated, of applying that principle.
`In the drawings:
`Figure 1 is a transistor switching circuit illustrating
`the principle of this circuit.
`Figure 2 is a PNP complemented transistor switching
`circuit.
`Figure 3 is an NPN complemented transistor switch
`ing circuit.
`Figure 4 is an N way complemented OR switching
`circuit using PNP transistors.
`Figure 5 is an N way complemented OR switching
`circuit using NPN and PNP type transistors.
`Figure 6 is a complemented switching circuit capable
`of realizing more than one logical function.
`Figure 7 is one type of complemented transistor bi
`stable circuit.
`Figure 8 is another type of complemented transistor
`bistable circuit.
`Figure 9 is a third type of complemented transistor
`bistable circuit.
`Figure 10 is an illustration of a coupling technique for
`transistor switching circuits of this invention.
`Referring now to Figure 1, a transistor circuit is shown
`illustrating the basic principle of the switching circuit of
`this invention. In Figure 1 a PNP junction transistor 1
`is shown having an emitter 2, a base 3 and a collector 4
`each separated by junctions 5 and 6, respectively. A
`common point 7 is provided in the circuit and a source
`of constant current illustrated as a battery 8 and resistor 9
`in series is connected to this point. The emitter 2 of
`transistor
`is connected to point 7 and an asymmetric
`impedance shown as a diode 10 is connected in the for
`Ward direction between the point 7 and a reference po
`tential. The collector 4 of transistor 1 is connected to a
`negative potential shown as battery 1 through a load
`impedance illustrated as a resistor 12. Input terminal 13
`is provided to permit impressing potential changes on
`the base 3 of transistor 1.
`Operation.-In the no signal condition, the base 3 of
`transistor i
`is maintained positive with respect to the
`emitter 2, by connecting the input terminal 3 to a
`Source of positive potential not shown and transistor is
`cut off. The constant current applied to point 7 through
`the constant current generator, comprising battery 8 and
`resistor 9 in the no signal condition, flows through diode
`16 to reference potential. When a negative input signal
`is impressed at terminal 3 of sufficient magnitude to
`remove the reverse bias from the emitter junction 5 the
`direction of constant current flow supplied to point 7 is
`changed so as to pass through the alternate path com
`prising transistor and the load resistor 2 to the nega
`tive potential of battery 1. Under these conditions, the
`potential of point 7 becomes negative with respect to
`reference potential and the current flow through the first
`path diode 0 is cut off. At this time, the constant cur
`rent Supplied to point 7 by the constant current generator
`
`This invention relates to transistor switching circuits
`and in particular to transistor switching circuits wherein
`a transistor is operated in an essentially common base
`type of operation.
`In the design and development of transistor switching
`circuitry, a number of limitations have been encountered
`which have an effect on the speed of operation of such
`circuits. These limitations arise from a number of
`Sources, the more serious of which are the result of the
`wide range of characteristics which transistors may ex
`hibit and the effect of both transistor and stray circuit
`capacitances. The phenomena of "Minority carrier stor
`age,” “Avalanche” and "Zener” breakdown of junctions,
`and the wide range of base to collector amplification fac
`tors, known in the art as ce' of transistors, that must be
`considered in transistor circuit design are examples of
`problems encountered.
`There are three principal types of operation known in
`the art for transistor circuitry, these are referred to as
`the common or grounded emitter type, the common or
`grounded base type and the common or grounded col
`lector type of transistor circuitry. Each of these types
`of operation has advantages for particular applications
`and it has been discovered that the common base type
`of operation is superior to all others with respect to
`minimizing the above mentioned problems and ultimately
`to provide Superior speed and reliability when used in
`switching circuits.
`A discussion of the performance of the common or
`grounded base type of operation appears in the follow
`ing references.
`Principles of Transistor Circuits, by
`R. F. Shea, published by J. Wiley & Sons, N.Y., 1953;
`Transistors and Other Crystal Valves, by T. R. Scott,
`published by MacDonald Evans Ltd., London, 1955;
`Fundamentals of Transistors, by L. M. Krugman, pub
`lished by John F. Rider, N.Y., 1954; Transistors
`Theory and Applications, by A. Coblenz and H. L.
`Owens, published by McGraw-Hill, N.Y., 1955.
`What has been discovered is a principle of operation
`of transistor circuitry for switching applications where
`the advantages of the grounded base type of operation
`are utilized to provide a maximum of switching speed.
`This is accomplished by providing a transistor switching
`circuit having a common point to which is attached a
`constant current source. Multiple current paths are pro
`vided between the common point and the reference poten
`tial, each of which has an asymmetric impedance and at
`least one of which is a transistor. With this configura
`tion a difference of potential may be applied between
`points in the paths to control the path through which the
`constant current flows.
`A primary object of this invention is to provide an
`improved principle for the design of transistor switching
`circuits.
`Another object is to provide an improved high speed
`transistor switching circuit.
`Another object is to provide a transistor switching
`circuit system which operates on relatively small signals.
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`made up of battery 8 and resistor 9, flows entirely
`through the transistor and load. When the potential at
`the input terminal 3 returns to the no signal condition,
`the base 3 of the transistor it becomes positive with re
`spect to the emitter 2 and junction 5 is again reverse
`biased, thereby cutting cff conduction through transistor i,
`changing the direction of the constant current flow at
`point 7 back through diode 10. It may be seen from the
`above discussion and Figure 1 that what is provided is a
`source of constant current delivered to a common point
`in a switching circuit and that multiple, shown here as
`two alternate paths, are provided connected to that com
`mon point, each of the alternate paths having asymmetric
`impedance and at least one of which is a transistor. Each
`path is then connected to a potential level such that a
`small variation between the potential level to which each
`path is connected would serve to change the direction
`but not the magnitude of the constant current supplied to
`the common point.
`-
`Through the use of this switching circuit principle a
`number of not immediately apparent advantages are
`achieved. The first of these advantages is that the tran
`sistor , which, for purposes of explanation will be re
`ferred to as the 'switching transistor," is operated in
`what is known in the art as the common or grounded
`base type of circuit operation. The advantages of the
`common base type of operation are well known in the
`art and the Turn Off and Turn On performance of the
`transistor operated in such a circuit configuration is
`governed by time constants which are orders of magni
`tude shorter than those of all other types of operation
`currently available in the art. Thus, for an applied volt
`age switching signal applied to terminal 13, the char
`actertistics in Turn. On and Turn Off of transistor
`are
`governed by the time constants involved in the grounded
`base operation of a transistor. The grounded base type
`of operation here may be seen from the fact that the
`constant current is switched into the emitter of a tran
`sistor which is connected to a low impedance or voltage
`source at the base. Furthermore, as the voltage change
`at the emitter required is very small for this circuit the
`effects of capacitance at the emitter are very small. The
`transient behavior and the direct current behavior of the
`grounded base type of operation permits the circuit to be
`relatively independent of the “base to collector” amplifi
`cation factor of the transistor. This factor is known in
`the art as ox'. Another advantage of the grounded base
`type of operation is that such a circuit has an inherent
`stability factor (known in the art as S that is close to
`"unity"). The stability factor is defined in the art as
`the effect of the back current through the collector
`junction on the circuit; and in circuit applications, this
`factor is expressed in terms of a ratio of the emitter re
`sistance to the base resistance and consequently it is a
`measure of the input impedance that can be realized for
`the circuit. Since the transistor 1 may be closely con
`trolled as to both the magnitude of reverse bias on the
`junction 5 at cut-off and the potential on the base 3 in
`conduction, neither "Turn On" delay due to an excessive
`reverse bias on junction 5 nor "Turn Off” delay due to
`minority carrier storage resulting from saturation is en
`countered. This is illustrated by the fact that the maxi
`mum negative voltage necessary to turn on the tran
`sistor is merely the forward voltage drop across the
`emitter Zone and emitter junction. Similarly, the mini
`mum positive voltage necessary to be applied to the
`base 3 of transistor
`in order to turn of the circuit is
`the maximum forward potential drop across the diode
`19. Since a constant current is supplied to point 7, both
`the maximum negative voltage and the minimum positive
`voltage necessary for operation may be very accurately
`established for the circuit. Further, the actual potential
`Swing between these two maxima and minima as is well
`known in the semiconductor art is very small and there
`fore the circuit parameters in constructing a circuit in
`
`4.
`volving the principle of this invention may be so selected
`that the transistor 1 operates at the optimum point on the
`characteristic curve for the type of switching operation
`desired. It will be also apparent to one skilled in the
`art that an additional advantage of the circuit of con
`figuration of Figure 1 is that the reactive component
`associated with the distributed capacitance associated with
`the diode 10, upon the switching of the current path of
`point 7 to the transistor i, discharges so as to aid in
`turning on transistor .
`The above-described basic principle of this invention
`overcomes several limitations in the speed of transistor
`switching circuitry. A first advantage is that through the
`operation of the transistor as is performed by the method
`of this invention, saturation is avoided and thereby the
`phenomena of minority carrier storage and consequently
`"Turn Off” delay is minimized. Another advantage is
`that a circuit frequency response limitation imposed by
`the capacitance associated with the transistor and other
`portions of the circuit is minimized in that as the voltage
`swings handled by the circuit are small, little time is lost
`in charging and discharging of associated capacitance.
`Further, since the impedance levels of circuitry con
`structed according to the principle of this invention are
`low, the time constants associated with circuit capaci
`tances are short. Another limitation that is minimized
`as a result of this type of operation is that the a' (base to
`collector amplification factor) of the transistor has little
`effect on the speed of operation of the circuit since in
`this type of operation the output is not dependent on
`the ox' of the transistor but rather on the oz (emitter to
`collector amplification factor) of the transistor. There
`fore a wider range of transistors is available with this
`type of circuitry. The limitation due to the storage time
`in associated diode circuitry is eliminated, due to direct
`coupling of all elements, as will be explained in detail
`later.
`The above-described basic principle and the advantages
`inherently flowing therefrom may be incorporated into
`a basic building block for logical circuitry wherein the
`diode 10 of Figure 1 may be replaced with a second
`grounded base transistor, resulting in a symmetric circuit
`wherein the complement of the logical function desired
`may be acquired as a by-product of the logic performed.
`An illustration of this type of basic building block is
`shown in Figure 2.
`Referring now to Figure 2 wherein like elements with
`those of Figure 1 are given the same reference numerals,
`a transistor 1 is provided having an emitter 2, a base 3
`and a collector 4, separated by junctions 5 and 6 re
`spectively. The emitter 2 is connected to a common point
`7 to which is supplied a constant current through battery
`8 and a resistor 9, in series. A second current path is
`provided comprising a transistor 15 having an emitter 16,
`base 7 and a collector 18, separated by junctions 9 and
`20, respectively. The base 17 of transistor 15 is con
`nected to reference potential. The emitter 6 is con
`nected to a common point 7. The collectors 18 and 4
`are connected through a symmetrical load system where
`by collector 4 is connected through resistor 12 to battery
`11 and through resistor 22 to battery 24, similarly col
`lector. 8 is connected through resistor 2 to battery 1i
`and through resistor 23 to battery 24. Output terminals
`25 and 26 are connected to collectors 4 and 8 respec
`tively for signal sensing purposes as is well known in the
`art.
`Operation.-In operation, current flows in the sym
`metrical load system from battery 11 in two parallel
`paths, the first of which being through resistor 21 and
`resistor 23, to battery 24 and the second of which being
`through resistors 12 and 22 to battery 24.
`Under this condition current flows through the load
`system by virtue of a large difference of potential be
`tween batteries 11 and 24 so that switching performed
`between the active elements. in the circuit namely trans
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`An equivalent embodiment of the building block of
`sistors 15 and 1 serves merely to alter the magnitude or
`Figure 2, wherein opposite polarity pulses are handled
`direction of this current. Assuming the potential at
`through the use of NPN type transistors is shown in Fig
`the base 3 of transistor to be in a no signal condition
`which is such that conduction through transistor
`is
`ure 3. In this embodiment as in the embodiment of
`Figure 2, complementary type logic is available and all
`cut off, the constant current delivered to point 7 from
`of the features found to be advantageous in the PNP type
`battery 8 to resistor 9 flows through transistor 15 and
`embodiment of Figure 2 are also present here.
`affects the current flowing through resistors 23 and 21
`Referring now to Figure 3, a constant current of proper
`of the load. Under these conditions a maximum posi
`direction for the type transistors being employed is de
`tive potential level is established at terminal 26 and
`similarly a maximum negative value of potential is estab
`livered to a point 7A by battery 8A and resistor 9A, in
`Series. A first current path is provided from point 7A
`lished at terminal 25. When a negative input signal
`through transistor 1A to the load impedance system com
`sufficient in magnitude to overcome the reverse bias on
`junction 5 is impressed on terminal 13 conduction in
`prising resistors 2A and 22A connected in series, be
`tween reference potential and battery 24A. Similarly, an
`transistor 1 is initiated and the direction of current flow
`supplied to point 7 changes from through transistor 15
`alternate current path is provided through transistor 5A
`from point 7A to the load impedance system comprising
`to flow through transistor 1. This decreases the poten
`tial at point 7 slightly and reverse biases junction 9
`resistors 25A and 23A connected in series between refer
`of transistor 15 thereby cutting off conduction in transis
`ence potential and battery 24A. It will be noted that the
`tor 15. The increment of current flow through transistor
`potential of the base 17A of transistor 15A in this NPN
`configuration is connected to an established negative po
`1 is added to the current flow through the load system
`20
`comprising resistors 12 and 22 thereby providing a po
`tential shown as battery 27 and that the load impedance
`tential shift at terminal 25 so as to raise the potential
`System is connected to reference potential rather than to
`at that terminal an amount equivalent to the magnitude
`a negative potential as was illustrated in Figure 2. This is
`of the input signal. Similarly, in the alternate current
`accomplished for a potential shifting purpose which will
`path involving transistor 15, the cutting off of transistor
`be explained later, which serves to permit building blocks
`5 removes an increment of current that has been flowing
`of the types of Figures 2 and 3 to be used in pairs such
`in the load system comprising resistors 21 and 23, there
`that the potential levels at the output terminals are of
`by reducing potential level at terminal 26.
`proper magnitude excursion to directly drive a subsequent
`logical block employing the opposite conductivity type
`It may now be seen that the circuit of Figure 2 is a
`very versatile building block. In it, direct current im
`transistors. With this arrangement and the fact that the
`30
`pedance levels may be low at all times in all parts of
`complement of a particular signal is always available
`the circuit, delays due to circuit and transistor capaci
`considerable logical versatility may be realized.
`tance are maintained at a minimum. By the symmetrical
`To aid in understanding and practicing the invention,
`aspects of such a building block as is described in Figure
`the specifications of the circuit of Figure 3 are here pro
`2 the logic performed as a result of the switching func
`vided for comparison purposes with the circuit of Figure
`tion of the building block, appears as the direct logical
`2 and the explanation of the operation will be undertaken
`operator at terminal 25 and the complement or denial
`from a slightly different viewpoint. As previously men
`of the logical operator appears at terminal 26. Thus,
`tioned, it should be understood that the following set of
`it should be noted that the structural features of the
`Specifications for the circuit of Figure 3, should not be
`switching circuitry of this invention not only provide
`construed as a limitation it being well established in the
`speed of operation but also in providing such speed
`art that a wide range of such specifications are available
`achieve a powerful switching advantage of complemen
`in the art for such circuitry.
`tary logic.
`Transistor 1A -------- NPN a cut of 5 mic. ac,95-with a
`The following specifications are provided as an illus
`maximum of 0.4 volt, emitter to
`base voltage drop with 4 milli
`tration of the magnitude and direction of the parameters
`anpees’ collector current and a
`of the circuit of Figure 2, merely for the purpose of aid
`minimum emitter to base break
`down voltage of 1.5 volts.
`ing in understanding and practicing the invention and
`Transistor 15A ------- NFNa cut of 5 Inc. a.c. 95-with a
`maximum of 0.4 volt, emitter to
`to provide a basis for comparison of material to be pre
`base voltage drop with 4 milli
`sented later. The following specifications should not
`amperes' collector current and a
`minimum emitter to base break
`be construed as a limitation on such circuitry as it is well
`down voltage of 1.5 volts.
`Battery 8A----------- 44 volts.
`established in the art that a wide range of such specifica
`Battery 24A ---------- 4 volts,
`tions are available.
`Battery 27------------ 3 wolts.
`Resistor 9A.----------- 0 ohms.
`Transistor ---------- PNPct cut of 5 mic, c.95-with a
`Resistor 23A.---------- 20K ohms.
`maximum of 0.4 wot, emitter to
`Resistor 22A.---------- 20K ohms.
`base voltage drop with 4 milliam
`Resistor 12A.---------- 300 ohms,
`peres' collector current and a
`Resistor 21A.---------- 300 ohms,
`Peaking coils--------- 5 microhenries-optional-one each
`minimum emitter to base break
`down Yoltage of 15 volts. .
`to be inserted between resistor
`Transistor 15--------- PNPac.95c, cut of 5 moc.-with a
`12A and terminal 25 and resistor
`maximum of 0.4 volt, emitter to
`2A and terminal 26.
`Input pulse :
`base voltage drop with 4 milliam
`peres' collector current and a
`No signal level --- -3.6 volts.
`Signal level ----- -2.4 volts,
`minimum emitter to base break
`Signal at terminal 26A:
`down voltage of 1.5 volts.
`Battery 8------------ 4 volts.
`No signal level-.... - 0.6 volt.
`Signal level ------ -- 0.6 volt.
`Resistor 9------------ 10K Ohms,
`Signal level at terminal 25A:
`Resistor 22-
`-- 20K ohms.
`Resistor 23
`- 20K ohms.
`No signal level.---- --9.6 volt.
`Battery 24-
`44 volts.
`Signal level ------ - 0.6 volt.
`Resistor 2.
`300 ohms.
`Operation.-Referring to Figure 3 and to the above
`Resistor 2.---
`-- 300 ohms.
`Peaking coils--------- 5 microhenries-optional-one each.
`recited specifications for the NPN circuit shown in Fig
`to be inserted between resistor
`ure 3, assume that the input signal in the no signal con
`2 and terminal 25 and between
`resistor 2 and terminal 26.
`dition is at -3.6 volts. The transistor 15A will be con
`Battery 11 ----------- 3 volts.
`ducting, and for a maximum potential difference across
`Input signal :
`No signal level
`- 0.6 volt.
`the conducting emitter 16A of 0.4 volt, the emitter 2A
`Signal level------ -0.6 volt.
`Output signal at terminal 26:
`of transistor A will be reverse biased by 0.2 volt. As
`No signal level.--- -2.4 volts.
`Surning, as above-described, a maximum potential differ.
`Signal level------ -3.6 volts.
`ence across the conducting emitter 16A of 0.4 volt and a
`Output signal level at terminal 25:
`No signal level
`-3.6 volts.
`minimum drop of 0.2 volt and further assume an o', for
`Signal level.------ -2.4 wolts.
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`transistors 15A and 1A, ranging from 20 to oo (infinity),
`4. This circuit is usable as an N way complement OR
`circuit. Referring now to Figure 4, like reference nu
`the collector current of the conducting transistor 15A will
`vary approximately between the limits of 3.86 and 4.08
`merals have been applied to like elements, and a common
`milliamperes, in addition to the back current (Ico) across
`point 7 is supplied by a constant current generator com
`the collector junction 20A. The collector current of tran
`prising a battery 8 and resistor 9 in series. A first current
`sistor 1A while cut off, is ico. When an input signal of
`path is made up of a transistor 15, connected to a load
`-- 1.2 volts is impressed on terminal 13A, raising thereby
`system comprising resistors 23 and 2i and batteries 24
`the potential of the base 3A to -2.4 volts, transistor A
`and 11, respectively, as previously described in connec
`will begin conduction, and considering a maximum poten
`tion with Figure 2. The alternate current path between
`tial difference across the conducting emitter 2A of 0.4
`point 7 and reference potential is made up of a number
`volt, the emitter 16A of transistor 15A would then be
`of branches shown in this illustration as transistors. A
`reverse biased by 0.2 volt. For the same tolerances as
`1 . . . 1 each connected in parallel between point 7
`recited above, the collector current for transistor A
`and a load system comprising resistors 22 and 12, and
`will vary between the limits of 3.92 to 4.12 milliamperes
`batteries 24 and 11.
`Operation-In operation, the circuit of Figure 4 per
`plus the back current through the collector junction ice.
`The collector current of transistor 15A under these coin
`forms in a manner similar to that described for the cir
`ditions will be I. The variations of output currents de
`cuits of Figures 2 and 3, wherein the constant current
`scribed above are approximate due to the fact that varia
`supplied to point 7 is switched alternately through one
`tions due to resistor and power supply tolerances are not
`of two paths to reference potential. The first path com
`included. It will be apparent then, in the circuit of Fig
`prising transistor 15 or the alternate path comprising
`ure 3, that the potential excursion of the collector 4A
`transistors A, B . . .
`.N. in parallel. The load System
`will be essentially equivalent to the potential excursion
`made up of impedances 21, 22, 23 and E2 and batteries
`at the input terminal. 3A and similarly, the potential
`11 and 24 function as previously described in the case
`excursion at the collector 18A will be the equivalent in
`of Figures 2 and 3. Under these conditions of operation,
`complementary form of the potential excursion produced
`assuming transistors 1A, B . . . 1N "cut off' by virtue
`by the input signal of terminal 3A. In view of the fact
`of having input terminals 13A, 13B . . . 13N connected
`that the common points of the load impedance system
`to a no signal level that is positive with respect to point 7,
`have been raised by a potential level of 3 volts, the poten
`constant current flows from point 7 through transistor 15
`tial level excursion of terminals 26A and 25A is now such
`and influences the potential at output terminal 26, causing
`as to be directly coupled to the input of a PNP type build
`30
`it to assume a maximum positive or no signal level value.
`ing block as illustrated in Figure 2. This fact may be
`Should a negative signal appear at any one or a combina
`seen by examination of the two sets of example specifica
`tion of inputs 13A, 13B . . . 13N, conduction will be
`tions set forth for Figures 2 and 3.
`initiated in at least one of transistors A, B . . .
`N, and
`The load system of this circuit and subsequent circuits
`the constant current supplied to point 7 will be switched
`to be described comprising resistors 2 and 22 and 21
`through one or more of transistors 1A,
`B . . . 1N
`and 23 and batteries 11 and 24 may be replaced by its
`thereby producing a positive potential excursion at output
`Thevenin equivalent of a resistor returned to a battery.
`terminal 25, as previously described in connection with
`The loading system described is used so as to reduce the
`Figures 2 and 3. It will then be apparent that the logical
`number of power supplies in a system wherein NPN and
`operator “OR” symbolized “V," may be realized at output
`PNP type circuits are used and to minimize the effects
`terminal 25 as a result of an input signal appearing at
`of noise on the power supplies. Further, an inductive
`any one of the input terminals 13A, 13B . . . 13N. Since
`element known in the art as a "peaking coil" may be in
`the circuit of Figure 4 is a complemented circuit, it will
`serted in the load system in series with the smaller of the
`then be apparent that at output terminal 26, the denial of
`two resistors in each branch for purposes of compensat
`the logical operator AND, symbolized “...” for the num
`ing for shunt capacitance at terminals 25 and 26 and to
`ber of input variables appearing at terminals 13A, 13
`45
`provide a transient source of reverse current at the out
`. . . 13N, will be realized. This may be seen from the
`put at the time that either the transistor 1 or 15, or A
`fact that the potential level at the terminal 25 is only
`or 15A is turned off. It should also be noted, looking
`changed when the denial of all input variables appearing
`at Figures 2 and 3, that by virtue of the complementary
`at terminals 13A, 13B . . . 13N are present. For ex
`nature of these building block circuits that one side or the
`ample, the constant current applied to point 7 flows
`other being connected to a common power supply is al
`through transistor 15 if and only if no input variable
`ways on and the load on all power supplies is therefore
`appears at any of terminals 13A, 13 . . . 13. When
`essentially constant, thus this greatly reduces the require
`an input variable appears at any one of these terminals
`ments on A.C. and D.C. voltage regulation for these sup
`the constant current supplied to point 7 is switched
`plies and noise is minimized throughout the system.
`through the particular transistor associated with the input
`Building blocks of the types illustrated in Figures 2
`variable that is present and the potential level at terminals
`and 3 may be provided with more than merely the two
`26 and 25 move in opposite directions. Since comple
`paths illustrated by introducing further switching tran
`ments are always available in circuits constructed along
`sistors in separate paths between the common point and
`the lines of this invention, the N way complemented OR
`the reference potential so that the constant current
`circuit of Figure 4 can perform all “AND” and “OR”
`through any particular one to the exclusion of the others
`operations on an N number of signals or their comple
`may be controlled by a particular magnitude of the
`ments. It will be apparent to one skilled in the art that
`switching signal to that path.
`the use of NPN type transistors constructed along the
`The previously described principle of this invention
`lines illustrated in Figure 3 will permit a positive “AND”
`exhibits considerable versatility and it may be seen that
`logical operator to be realized. In the circuit of Figure 4,
`a wide range of logical switching circuits constructed
`if the complement is not required, transistor 15 may be
`along the lines of the circuits described in Figures 2
`replaced by a diode as illustrated in Figure 1 and under
`and 3 may be fabricated wherein a constant current is
`this condition only the logical operator “V' at terminal 25
`supplied to a common point, which current may be
`switched through one of several alternate paths to change
`A further extension of the switching principle may be
`a potential in a load system having controlled current
`accomplished by coupling the circuits of Figures 2 and 3
`flowing therein. As an example of one type of modifica
`together thereby facilitating the handling of opposite
`tion of the switching principle of this invention a logical
`polarity Switching pulses. In Figure 5 of this invention
`circuit having a plurality of parallel-paths making up one
`there is illustrated an N way complemented “OR” circuit
`of the two alternate current directions is shown in Figure
`employing transistors of m