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`I H
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`First Edition
`Compiled by the Computer Applications Engineering Department
`
`Author
`William R. Blood JI.
`
`Contributors
`
`Jon M. DeLaune
`Jerry E. Prioste
`
`Editor
`Edmund C. Tynan JI.
`
`@ MOTOROLA Serniconduc~or Produc~s Inc.
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`Circuit diagrams external to Motorola products are included as a means of
`illustrating typical semiconductor applications; consequently, complete infor(cid:173)
`mation sufficient for construction purposes is not necessarily given. The
`information in this book has been carefully checked and is believed to be entirely
`reliable. However, no responsibility is assumed for inaccuracies. Furthermore,
`such information does not convey to the purchaser of the semiconductor devices
`described any license under the patent rights of Motorola Inc. or others.
`
`MECL, MECL II, MECL III, MECL 10,000, MTTL,
`MTTL III, and MDTL are trademarks of Motorola Inc.
`
`First Edition
`October, 1971
`
`@MOTOROLA INC., 1971
`
`ii
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`PREFACE
`
`In response to the demand for higher performance systems, engineers
`are looking at digital integrated circuit families which are faster than the
`popular TTL and DTL types. Motorola's Emitter Coupled Logic (MECL)
`circuits have the characteristics to meet the performance requirements
`for present and future systems. MECL 10,000 is ideal for computer and
`communications systems, while state-ofthe-art instrumentation equip(cid:173)
`ment uses MECL III.
`As circuit speeds increase, wiring rules and system design techniques
`must be adjusted accordingly. Designing with MECL is no more difficult
`than designing high performance equipment with slower forms of logic.
`High performance system design for any form of logic, however, does
`require an understanding of the factors which affect system performance.
`In fact, many of the MECL features such as transmission line drive capa(cid:173)
`bility, complementary outputs, Wired-OR, and versatile logic functions
`can add as much to system performance as the short propagation delays
`and high toggle rates.
`In the past, several articles and application notes have been written
`about MECL circuits and systems. However, there was a need for a book
`which would completely define MECL operation. This book has been
`written to give the designer the information to establish design rules for
`his own high performance systems.
`The information in this book is based on equations derived from
`electronic theory, laboratory tests, and inputs from MECL users. All of
`the rules and tables are for conservative system design with MECL
`circuits. It is important to realize that the circuits can operate properly
`under conditions much more adverse than suggested in this book.
`In addition to the technical contributors, Jon DeLaune and Jerry
`Prioste, the author would like to thank Lloyd Maul, Mike Lee, Reg
`Hamer, Jim Hively, Howard Gnauden, Don Murray, Tom Balph, and
`Colin Crook whose knowledge of MECL has added to the completeness
`and accuracy of this book. Finally, great appreciation is due to the
`many technicians, engineers, and managers who took their valuable time
`to read all or part of this book as it was depeloped.
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`Table of Contents
`
`Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. vi
`What Is MECL? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. VI
`History of MECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. vi
`Why Use MECL? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. vii
`The Advantages of MECL . . . . . . . . . . . . . . . . . . . . . . . . . . . .. viii
`MECL Areas of Application. . . . . . . . . . . . . . . . . . . . . . . . . .. ix
`Purpose of This Book. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . x
`CHAPTER 1 - MECL Families . ........................................... .
`The Basic MECL Gate ........................................................... .
`Noise Margin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5
`MECL Circuit Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6
`MECL Flip-Flops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`8
`Operation of Flip-Flop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
`8
`MECL Family Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10
`CHAPTER 2 - Using MECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15
`MECL II Design Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15
`A. Logic Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15
`B. System Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 19
`C. Circuit Board Layout Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20
`D. Backplane Wiring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 21
`E. System Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 22
`
`MECL 10,000 Design Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 23
`A. General Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 23
`B. Printed Circuit Card Layout Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 23
`C. Power Supply Bypassing on Circuit Cards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 24
`D. Backplane and Loading Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 24
`E. System Distribution and Grounding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25
`F. Loading Rules for MECL 10,000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25
`
`MECL III Design Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 29
`A. Circuit Card Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 29
`B. Transmission Line (Microstrip Line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30
`C. On-Card Clock Distribution via Transmission Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30
`D. Off-Card Clock Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 31
`E. Testing MECL III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 31
`CHAPTER 3 - Printed Circuit Board Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 35
`Transmission Line Geometries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 37
`Basic Transmission Line Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 42
`Unterminated Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 43
`Series Damped and Series Terminated Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 46
`Parallel Terminated Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 52
`Transmission Line Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 53
`Wire wrapped Cards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 55
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`Contents (continued)
`
`CHAPTER 4 - System Interconnections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 57
`Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`59
`Coaxial Cable ................................................................. , 59
`Differential Twisted Pair Lines and Receivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 64
`Ribbon Cable ................................................................. , 70
`Schottky Diode Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. 71
`Parallel Wire Cables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 76
`Twisted Pair Cable, Driven Single-Ended. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 83
`
`CHAPTER 5 - Power Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 87
`System Power Calculations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 88
`Power Supply Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`91
`System Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`92
`Backplane Power Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 95
`On-Card Power Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`96
`Vrr Termination Voltage Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 99
`
`CHAPTER 6 - Thermal Considerations ...................................... 101
`MECL Integrated Circuit Heat Transfer .............................................. 102
`MECL DC Thermal Characteristics ................................................ , 106
`Heat Dissipation Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 110
`Mounting Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 112
`
`CHAPTER 7 - Transmission Line Theory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 115
`Transmission Line Design Information, With Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 115
`Signal Propagation Delay for Microstrip and Strip Lines With
`Distributed or Lumped Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 123
`Microstrip Transmission Line Techniques, Evaluated Using TDR
`Measurements, With Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 126
`The Effect of Loading on a Parallel Terminated Transmission Line,
`With Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 139
`Analysis: Series Terminated Lines Compared to Parallel Terminated
`Lines, With Example ........................................................... 146
`Analysis of Series Damping Terminations ............................................ 153
`Bibliography ....................... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 166
`CHAPTER 8 - MECL Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 167
`Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. ............................ 167
`Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 182
`Adders ...................................................................... , 182
`Code Converters .............................................................. , 191
`Memories ..................................................................... 196
`Oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 199
`One-Shot Multivibrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 202
`Linear Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 205
`Translators. . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 206
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`Introduction
`
`What is MECL?
`
`The term MECL identifies Motorola's emitter coupled logic. Emitter coupled
`logic is a non-saturating form of digital logic which eliminates transistor storage time
`as a speed limiting characteristic, permitting very high speed operation. "Emitter
`Coupled" refers to the manner in which the emitters of a differential amplifier with(cid:173)
`in the integrated circuit are connected. The differential amplifier provides high
`impedance inputs and voltage gain within the circuit. Emitter follower outputs re(cid:173)
`store the logic levels and provide low output impedance for good line driving and
`high fanout capability.
`
`History of MECL
`
`Motorola offers MECL circuits in four logic families: MECL I, MECL II,
`MECL III, and MECL 10,000.
`The MECL I family was the first digital monolithic integrated circuit line
`produced by Motorola. Introduced in 1962, MECL I was considerably beyond the
`state-of-the-art at that time. Several years passed before any other form of logic
`could equal the 8 ns gate propagation delays and 30 MHz toggle rates of MECL I. As
`a result of its reliability and performance, MECL I was designed into many advanced
`systems.
`Nearly a decade later, MECL I is still being produced by Motorola. It finds wide
`usage in existing products. However, several features of the more advanced MECL II,
`III, and 10,000 favor their being used in new designs. For example, MECL I requires
`a separate bias driver package, MC304/MC354, to be connected to the logic
`functions. This means increased package coun t and extra circuit board wiring. Also
`the 10-pin packages used for MECL I limit the number of gates per package and the
`number of gate inputs. No provision was made for operation of MECL I with
`transmission lines, as they were unnecessary with the 8 ns rise and fall times.
`In 1966 Motorola introduced the more advanced MECL II. The basic gate
`featured 4 ns propagation delays and flip-flop circuits that would toggle at over
`70 MHz. MECL II immediately set a new standard for performance that has been
`equaled by non-ECL logic only with the introduction of Schottky TTL in 1970.
`Motorola continued with the development of MECL II and flip-flop speeds
`were increased first to 120 MHz for the MC I 027/MC 1227 JK circuit, and then to
`180 MHz for the MC 1 034 type D flip-flop. To drive these high speed flip-flops, high
`speed line drivers were introduced with 2 ns propagation delays and 2 ns rise and fall
`times. With 2 ns edges, transmission lines could be used to preserve the waveforms
`and limit overshoot and ringing on longer lines. Consequently, the MC 1 026 was
`designed to drive 50-ohm lines. Because of the significant speed increase of the line
`drivers and high speed flip-flops over the basic MECL II parts, these circuits are
`commonly called MECL 11-1/2, although they are part of the MECL II family.
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`MECL II is continuing to gain in popularity and is being designed into many
`high speed systems. MECL II circuits have a temperature compensated bias driver
`internal to the circuits (except for the MC 1 020/MC 1220 line receiver which requires
`no internal bias). The internal bias source simplifies circuit interconnections and
`tracks with both temperature and supply voltage to retain noise margin under varied
`operating conditions.
`Complex functions became available in MECL II when trends shifted toward
`more complicated circuits. The family now has adders, data selectors, multiplexers,
`decoders and a Nixie* tube decoder/driver. MECL II is a growing line, with new
`products currently being designed and introduced.
`Motorola's continuing development of ECL made possible an even faster logic
`family. As a result, MECL III was introduced in 1968. Its 1 ns gate propagation
`delays and greater than 300 MHz flip-flop toggle rates remain the industry leaders.
`The I ns rise and fall times require a transmission line environment for all but the
`smallest systems. For this reason, all circuit outputs are designed to drive
`transmission lines and all output logic levels are specified when driving 50-ohm
`loads. Because of MECL TIl's fast edge speeds, multi-layer boards are recommended
`above 200 MHz. For the first time with MECL, internal input pull down resistors are
`included with the circuits to eliminate the need to tie unused inputs to VEE. The
`Hi-Z 50 kn input resistors are used with transmission lines for most applications.
`Optional Low-Z 2 kn input resistors can be used in place of pulldown resistors
`when the chips are used in a hybrid circuit or when line lengths are very short.
`MECL III is gaining in popularity - especially in high speed test and communica(cid:173)
`tions equipment. As a result, Motorola is continuing to expand and develop this
`product line.
`Trends in large high speed systems have shown the need for an easy to use logic
`family with 2 ns propagation delays. To fill this requirement, Motorola introduced
`the MECL 10,000 series in 1971. In order to make the circuits comparatively easy to
`use, edge speed was slowed to 3.5 ns while the important propagation delay was held
`to 2.0 ns. The slow edge speed permits use of wire wrap and standard printed circuit
`lines. However, the circuits are specified to drive transmission lines for optimum
`performance.
`MECL 10,000 is provided with logic levels that are completely compatible with
`MECL III to facilitate using both families in the same system. A second important
`feature of MECL 10,000 is the significant power reduction. MECL 10,000 gates use
`less than one-half the power of MECL III or high speed MECL II gates. Finally, the
`low gate power and advanced circuit design techniques have permitted a new level of
`MECL complex circuits. For example, complexity of the MCIOl81 four-bit
`arithmetic unit compares favorably to that of any bipolar integrated circuit on the
`market. MECL 10,000 is the fastest growing ECL family in the industry and
`Motorola is designing and introducing many versatile complex functions to expand
`the line.
`
`Why Use MECL?
`
`Circuit speed is, of course, an obvious reason for designing with MECL.
`MECL III is significantly faster than any other digital logic family. MECL 10,000
`offers shorter propagation delays and higher toggle rates than any non-ECL type of
`
`*T.M. - Burroughs Corp.
`
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`logic. Equally important to the circuit speed are the characteristics of MECL circuits
`which permit entire systems to operate at high speeds.
`The ability of the faster MECL families to drive transmission lines becomes
`increasingly important in larger and faster systems. While a transmission line
`environment imposes some additional design rules and restrictions, the advantages of
`longer signal paths, better fanout, improved noise immunity, and faster operation,
`often more than compensate for the restrictions.
`When using MECL II or MECL 10,000 without transmission lines, their high
`input impedances permit the use of series-damping resistors to increase wiring
`lengths and to improve waveforms. Unlike non-ECL forms of logic, MECL circuits
`have constant power supply requirements, independent of operating frequency. This
`simplifies power supply design, since circuit speed need not be considered a variable.
`At fast circuit speeds MECL can offer a considerable power saving over the other
`types of logic.
`In addition to faster operation, the line driving features of MECL circuits can
`be exploited to improve system performance. For one, the parts specified to drive
`transmission lines will drive coaxial cables over distances limited only by the
`bandwidth of the cable. In addition, the shielding in coaxial cable gives good
`isolation from external noise.
`More economical than using coaxial cable, is the ability of the MECL circuits to
`differentially drive and receive signals on twisted pair lines. Using this technique,
`signals have been sent over twisted pair lines up to 1000 feet in length.
`The complementary outputs and Wired-OR capabilities of MECL circuits result
`in faster system operation with reduced package count and a power saving. The
`complementary outputs are inherent in the circuit design and both outputs have
`equal propagation delay. This eliminates the timing problems associated with using
`an inverter to get a complement signal. The logic OR function is obtained by wiring
`circuit-outputs together. The propagation delay of the Wired-OR connection is much
`less than a gate function and can save power, as only one pulldown resistor or
`termination is required per Wired-OR.
`Another advantage when designing with MECL is the low noise generated by
`the circuits. Unlike totem pole outputs, the emitter follower does not generate a
`large current spike when switching logic states, so the power lines stay comparatively
`noise free. The low current-switching in signal paths, relatively small voltage swing
`(typically 800 mY), and low output impedances, cut down crosstalk and noise.
`Generated noise is also reduced by MECL's relatively slow rise and fall times.
`For each MECL family the edge speed is equal to or greater than the propagation
`delay. The low noise associated with MECL is especially important when the logic
`circuits are
`to be used
`in a system which contains
`low
`level analog or
`communications signals.
`The flexibility of the MECL line receivers and Schmitt triggers to act as linear
`amplifiers leads to many functions that may be performed with standard MECL
`circuits. For example, in addition to amplifying low level signals to MECL levels,
`these MECL circuits can be used as crystal oscillators, zero crossing detectors, power
`buffers, Schmitt triggers, RF and video amplifiers, one-shot multivibrators, etc.
`
`The Advantages of MECL
`1. Highest speed IC logic available
`
`2. Low cost
`3. Low output impedance
`
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`4. High fanout capability
`5. Constant supply current as a function of frequency or logic state
`
`6. Very low noise generation
`7. Complementary logic outputs save on package count
`8. Low crosstalk between signal leads
`9. All outputs are buffered
`10. Outputs can be tied together giving the Implied-OR function
`11. Common mode rejection of noise and supply variations is I V or greater
`for differential line receiving
`12. Bias supplies are internal, allowing MECL use with a single power
`supply
`13. Minimal degradation of parameters occurs with temperature variations
`14. Large family of devices yields economical designs
`15. Power dissipation can be reduced through use of Implied-OR and the
`"Series Gating" technique
`16. Easy data transmission over long distances by using the balanced twisted
`pair technique with standard parts
`
`17. Constant noise immunity versus temperature
`18. Best speed-power product available
`19. All positive logic functions are available
`20. Adapts easily to MSI and LSI techniques
`
`MECL Areas of Application
`1. Instrumentation
`2. High speed counters
`3. Computers
`4. Medical electronics
`5. Military systems
`6. Large real-time computers
`7. Aerospace and communication satellite systems
`8. Ground support system
`9. High speed AID conversion
`10. Digital communication systems
`11. Data transmission (twisted pair)
`12. Frequency synthesizers
`13. Phase array radar
`14. High speed memories
`15. Data delay lines
`
`ix
`
`SAMSUNG
`EX. 1030, PAGE 10
`
`

`

`Purpose of This Book
`
`Rules and guidelines for using the various MECL families comprise the subject
`matter of this book. Because of edge speed and bit rate capabilities, each family has
`differing system requirements. The family name will therefore be referenced for the
`examples and figures in the text, whenever applicable. The information in this book
`is meant to apply to MECL II, MECL III, and MECL 10,000. The information about
`MECL II will generally apply to MECL I, although the data would be conservative
`because of the slower MECL I speed. This book aims at giving the reader an
`understanding of the MECL families, as well as the knowledge needed to confidently
`design with and use MECL.
`Chapter I discusses the operation of MECL circuits and the characteristics of
`the various families. It also shows methods for internally connecting the basic gates
`to provide efficient complex functions. Of more importance to the user is Chapter 2
`-
`a list of rules providing a condensed reference for using the various MECL
`families.
`Chapters 3, 4, 5, and 6 elaborate on those rules giving a technical background
`for good system design and presenting test results showing MECL circuits in various
`modes of operation. Chapter 3 describes circuit-to-circuit interconnections on a
`card. Both open wire and transmission line techniques are covered. Chapter 4
`expands the wiring techniques to show methods for card-to-card and panel-to-panel
`interconnections. Chapter 5 elaborates on power distribution, showing how voltage
`drops and power line noise affect noise immunity. Chapter 6 discusses thermal
`considerations. Attention is given to the problems of calculating chip temperature,
`removing heat from the system, and to the effect of thermal differences on noise
`immunity.
`Chapter 7 provides background necessary for understanding transmission lines
`as they apply to MECL. Derivations of equations are shown, along with test results
`correlating with the theoretical analysis. This chapter should be especially useful
`when selecting a transmission line impedance and when determining the effect of
`fanout or stray capacitance on the line.
`Chapter 8 contains application ideas for MECL circuits. Included are methods
`for interfacing various logic families with MECL, and numerous useful circuits
`designed with MECL for high performance.
`
`x
`
`SAMSUNG
`EX. 1030, PAGE 11
`
`

`

`

`

`Basic MEeL Gate
`
`and 25 0 C ambient temperature, VBB is -1.29 volts dc for either MECL 10,000 or
`MECL III, and - 1.175 volts dc for MECL II. The diodes in the voltage divider line,
`together with Q6, provide temperature compensation by maintaining a level
`consistent with the midpoint of the logic levels despite changing temperatures.
`One additional feature of the bias supply is its ability to track supply voltage
`changes. Consequently MECL II gates, for example, are specified to operate from a
`- 5.2 volt ±20% supply. In fact, they are capable of working over a much wider range
`(-3.0 to -8.0 volts) although ac performance would be degraded.
`
`The emitter followers are output drivers. They provide level shifting from the
`differential amplifier to MECL output levels, and provide a low output impedance
`for driving transmission lines. Both MECL 10,000 and MECL III circuits use open
`emitter outputs. The reason is that since these circuits are designed for use with
`transmission lines, and since the line termination provides an output load, internal
`pulldown resistors would be a waste of power.
`
`However MECL II, which is not specified to drive transmission lines, offers
`gates both with and without pulldown resistors. In general, the circuits without
`pulldown resistors are intended for use in Wired-OR circuit designs rather than for
`driving high fanout loads. MECL II circuits with internal output pulldown resistors
`use 1.5 kQ values for standard speed parts, and as low as 600 Q values for the high
`speed circuits.
`MECL 10,000 and MECL III circuit families, designed to drive transmission
`lines, have two V CC power voltage inputs. V CC 1 is used to supply current to the
`output drivers, while V CC2 supplies the remainder of the circuit. Separate V CC lines
`are used to eliminate crosstalk between circuits in a package. More important, the
`use of two lines speeds up circuit performance by eliminating a voltage spike which
`otherwise would occur on the bias voltage, VBB, caused by the relatively heavy
`currents associated with transmission lines. Each V CC pin should be connected to
`the system ground by as short a path as possible (all V CC pins are connected to the
`same system ground). Standard speed MECL II circuits are not designed to drive
`transmission lines and consequently require only a single V CC package pin.
`The input pulldown resistors shown in Figure 1-1 are characteristic of MECL
`10,000 and MECL III. MECL 10,000 and Hi-Z MECL III use 50 kQ "pinch"
`resistors which serve to drain off the input transistor leakage current. These resistors
`hold unused inputs at a fixed zero level, so unused inputs are left open. On the other
`hand, MECL II without input pulldown resistors, requires unused inputs be tied to
`VEE or VOL·
`The following calculations illustrate the current switching operation of a MECL
`10,000 gate. Similar calculations may be performed for the other MECL families by
`substituting appropriate resistor values and voltage levels.
`When all gate inputs are at a voltage, Yin, equal to a logic f/J level, IVIL
`minl~IVinl~IVIL maxi, the input transistors Ql through Q4 in Figure 1-1 will not
`be conducting current, because the common emitter point of these four transistors is
`i.e., VBB + VBEQ5 ~ -1.29 V + (-0.80 V). This is not
`at about -2.09 V:
`enough forward bias (base to emitter) on Ql through Q4 for conduction. Thus,
`current flows through RC2, Q5, and RE- This current, IE(/), is:
`
`IE(/) = VEE - (V:: + VBE) "'" -4.0 rnA.
`
`2
`
`SAMSUNG
`EX. 1030, PAGE 13
`
`

`

`MECL Current Switching
`
`The voltage drop at the collector resistor. RC2, may be calculated as:
`
`VRC2 = IE0RC2 + IBRC2 ~ (-4.0 rnA) • (245 D) = -0.98V.
`
`The output transistor base current, IB, is small compared to the switch current,
`so the second term above can be ignored.
`The OR output is then obtained through an emitter-follower, Q8, which cuts
`the output level by one base-emitter drop, giving a voltage level:
`
`VOL OR = VRC2 + VBE,
`
`where: VBE = base to emitter drop on Q8, with logic zero current level (i.e., 6 rnA
`thm Q8).
`
`So:
`
`VOL OR ~ -0.98 V + (-0.77 V) ~ -1.75 V,
`
`typical at T A = 25°C.
`The base of the NOR output emitter-follower, Q7, is at about -0.05 V, yielding
`an output of - 0.924 V typical, at an output device current level of 22.5 rnA and
`T A = 25°C. (These output voltage and current levels assume 50-ohm loads to a
`terminating voltage, VTT, of - 2.0 V).
`If one or more of the gate inputs is switched to a voltage level, Yin, equal to a
`nominal logic 1 level, IVJH minl>IVinl>IVIH maxi, a current lEI flows through
`RCI, QI-Q4, and RE. This current is:
`
`where: Yin = -0.924 V
`
`VBE = -0.79 V.
`
`The current flow through RC 1 produces a voltage at the collector nodes of Q I
`through Q4:
`
`Finally, the output is obtained through an emitter follower, Q7, which drops
`the collector voltage level one base-emitter drop, so that:
`
`VOL NOR = VRCI + VBE (output device at 6 rnA)
`
`~ -0.98 V + (-0.77 V) = -1.75 V,
`
`typical at T A = 25°C.
`The transfer curves in Figures 1-2(a) and (b) indicate the behavior of the MECL
`gate while switching. Note from the data in Figure 1-3 and from the NOR transfer
`characteristic: for Yin increasing from VIL min to VILA max, the output remains
`at a high level. When Yin increases from VILA max to VIHA min' the NOR output
`
`3
`
`SAMSUNG
`EX. 1030, PAGE 14
`
`

`

`

`

`Noise Margin
`
`will sw