(12) United States Patent
`Chu
`
`I IIIII IIIIIIII Ill lllll lllll lllll lllll lllll lllll lllll lllll 111111111111111111
`US006345330B2
`US 6,345,330 B2
`*Feb.5,2002
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) COMMUNICATION CHANNELAND
`INTERFACE DEVICES FOR BRIDGING
`COMPUTER INTERFACE BUSES
`
`(75)
`
`Inventor: William W. Y. Chu, Los Altos, CA
`(US)
`
`(73) Assignee: Aegis Technology, Inc., Mountain
`View, CA (US)
`
`JP
`
`06 289953 A
`
`10/1994
`
`(List continued on next page.)
`
`OTHER PUBLICATIONS
`
`Digital Semiconductor, 21152 PCI-to-PCI Bridge Product
`Brief (02/96).
`
`(List continued on next page.)
`
`( *) Notice:
`
`This patent issued on a continued pros(cid:173)
`ecution application filed under 37 CFR
`1.53( d), and is subject to the twenty year
`patent term provisions of 35 U.S.C.
`154(a)(2).
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by O days.
`
`(21) Appl. No.: 09/149,882
`Sep. 8, 1998
`
`(22) Filed:
`
`(51)
`
`Related U.S. Application Data
`(60) Provisional application No. 60/083,886, filed on May 1,
`1998, and provisional application No. 60/092,706, filed on
`Jul. 14, 1998.
`Int. Cl.7 ........................... G06F 3/00; G06F 13/12;
`G06F 13/28; G06F 13/00
`(52) U.S. Cl. ............................ 710/65; 710/29; 710/101
`(58) Field of Search ............................ 375/244; 710/29,
`710/62, 65, 70, 71, 101, 128, 129, 69, 106;
`708/100
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`4,700,362 A * 10/1987 Todd et al.
`................. 375/249
`4,890,282 A
`12/1989 Lambert et al.
`.............. 370/79
`
`(List continued on next page.)
`
`FOREIGN PATENT DOCUMENTS
`
`Primary Examiner-Thomas Lee
`Assistant Examiner----Chun Cao
`(74) Attorney,
`Agent,
`Townsend&Crew LLP
`ABSTRACT
`
`(57)
`
`or
`
`Firm-Townsend&
`
`The present invention encompasses an apparatus for bridg(cid:173)
`ing a first computer interface bus and a second computer
`interface bus, where each of the first and second computer
`interface buses have a number of parallel multiplexed
`address/data bus lines and operate at a clock speed in a
`predetermined clock speed range having a minimum clock
`speed and a maximum clock speed. The apparatus comprises
`an interface channel having a clock line and a plurality of bit
`lines for transmitting bits; a first interface controller coupled
`to the first computer interface bus and to the interface
`channel to encode first control signals from the first com(cid:173)
`puter interface bus into first control bits to be transmitted on
`the interface channel and to decode second control bits
`received from the interface channel into second control
`signals to be transmitted to the first computer interface bus;
`and a second interface controller coupled to the interface
`channel and the second computer interface bus to decode the
`first control bits from the interface channel into third control
`signals to be transmitted on the second computer interface
`bus and to encode fourth control signals from the second
`computer interface bus into the second control bits to be
`transmitted on the interface channel.
`
`In one embodiment, the first and second interface controllers
`comprise a host interface controller (HIC) and a peripheral
`interface controller (PI C), respectively, the first and second
`computer interface buses comprise a primary PCI and a
`secondary PCI bus, respectively, and the interface channel
`comprises an LVDS channel.
`
`EP
`
`0 722 138 A
`
`7/1996
`
`15 Claims, 57 Drawing Sheets
`
`530
`
`525
`
`Host
`Interface
`Controller
`
`505
`
`Peripheral
`Interface
`Controller
`
`555
`
`Asynchronous
`
`Asynchronous
`
`~
`
`Intel Corporation v. ACQIS LLC
`Intel Corp.'s Exhibit 1003
`Ex. 1003, Page 1
`
`

`

`US 6,345,330 B2
`Page 2
`
`......... 714/798
`
`U.S. PATENT DOCUMENTS
`4,939,735 A * 7/1990 Fredericks et al.
`5,278,509 A
`1/1994 Haynes et al.
`5,278,730 A
`1/1994 Kikinis
`5,293,497 A
`3/1994 Free
`5,331,509 A
`7/1994 Kikinis
`5,355,391 A
`10/1994 Horowitz et al.
`5,463,742 A
`10/1995 Kobayashi .................. 395/281
`5,539,616 A
`7/1996 Kikinis
`5,550,710 A
`8/1996 Rahamim et al. ........... 361/687
`5,578,940 A
`11/1996 Dillon et al.
`5,600,800 A
`2/1997 Kikinis et al.
`5,606,717 A
`2/1997 Farmwald et al.
`5,640,302 A
`6/1997 Kikinis
`5,659,773 A
`8/1997 Huynh et al.
`5,663,661 A
`9/1997 Dillon et al.
`5,680,126 A
`10/1997 Kikinis
`5,721,837 A
`2/1998 Kikinis et al. .............. 395/281
`5,819,050 A
`10/1998 Boehling et al.
`........... 395/284
`5,826,048 A * 10/1998 Dempsey et al. ........... 710/129
`5,848,249 A * 12/1998 Garbus et al.
`.............. 710/128
`5,859,669 A * 1/1999 Prentice ...................... 348/469
`5,907,566 A * 5/1999 Benson et al. .............. 714/798
`5,948,047 A
`9/1999 Jenkins et al. .............. 708/141
`5,960,213 A * 9/1999 Wilson .......................... 710/2
`5,968,144 A * 10/1999 Walker et al.
`.............. 709/100
`5,991,844 A * 11/1999 Khosrowpour .............. 710/129
`5,999,952 A
`12/1999 Jenkins et al. .............. 708/100
`
`6,029,183 A
`6,040,792 A *
`6,052,513 A *
`6,216,185 Bl
`
`2/2000 Jenkins et al. .............. 708/100
`3/2000 Watson et al. . . . . . . . . . . . . . . 341/100
`4/2000 MacLaren ................... 395/294
`4/2001 Chu ........................... 710/101
`
`FOREIGN PATENT DOCUMENTS
`
`WO
`WO
`WO
`
`92 18924 A
`94 00970 A
`95 13640 A
`
`10/1992
`1/1994
`5/1995
`
`OTHER PUBLICATIONS
`
`Intel Corporation, Intel 430TX PCISET: 82439TX System
`Controller (MTXC) Architectural Overview (02/97).
`Intel Corporation, Intel 82371AB PCI-to-ISA/IDE XCEL(cid:173)
`ERATOR (PIIX4) Architectural Overview (04/97).
`Intel Corporation, Intel 440LX AGPSET: 82443LX PCI
`A.G.P. Controller (PAC) Advance Information (08/97).
`National Semiconductor, DS90CR215/DS90CR216 General
`Description (07/97).
`National Semiconductor, DS90CR215 Product Folder.
`Video Electronics Standards Association (VESA), Plug and
`Display(P&D) Standard, P&D and Digital Transition Mini(cid:173)
`mized Differential Signaling (TMDS) Video Transmission
`Overview, Version 1, Revision 0, pp. 1 & 31-34 (1997).
`* cited by examiner
`
`Ex. 1003, Page 2
`
`

`

`Flat
`Panel
`Display
`
`A
`
`r...
`
`~
`
`.
`
`-y
`
`Graphics 1--
`Subsystem
`
`North
`Bridge
`
`Keyboard V
`
`A
`
`,
`
`. 1/0
`':
`" Device
`
`---
`
`South
`Bridge
`
`r-------- ---------
`
`I
`
`•
`
`'F
`
`Notebook PC
`
`CPU
`
`Host Bus
`
`Cj
`•
`00. •
`
`L..---100
`
`PC
`Card
`
`Primarv PCI Bus
`...
`
`/105
`
`I
`I
`I
`I L High Pm Count
`: Connectors
`---------
`160
`PCl-to-
`PCIBridge
`
`I
`
`I
`
`~50
`
`I
`
`101
`102
`
`Seconda PCI Bus
`
`PCI
`Device 1
`
`155
`
`PCI Add(cid:173)
`on Board2
`
`FIG. 1
`
`Ex. 1003, Page 3
`
`

`

`TM
`Attached Computer Module
`
`/221
`
`I
`
`215
`205
`\ XI~-~~
`.J. ,"
`Power 81
`-
`
`' , iL,,.
`
`~
`
`d •
`r:JJ.
`•
`
`r-200
`
`210
`\
`
`Peripheral Console
`
`Power
`Supply
`
`CPU, Cache,
`North Bridge
`
`-
`
`I
`
`Graphics
`Subsystem
`
`216
`
`Memory
`
`....
`
`....
`
`Control
`Signals
`
`Video Output
`,219
`
`HOD
`
`IDE
`Cntrlr
`
`PCI Bus
`
`-
`
`Host
`Interface
`Controller
`
`I
`BIOS
`
`I
`
`USS
`
`XBus
`
`ITR; OMA
`
`South
`Bridge
`
`-
`
`To Display
`
`-
`I
`
`,..._ PCI
`Device
`
`PCI
`Bus
`
`- PCI
`
`Device
`
`Peripheral
`Interface
`~
`Controller
`
`...
`
`220_)
`
`217)!
`Video Bus
`
`I
`I
`I
`
`218
`XPBus IM);
`
`I
`
`I
`I
`I
`I
`I
`I
`~
`:Peripheral Bu~
`I
`I
`
`.... -- ...
`
`,,.
`
`I
`
`'
`'
`
`1
`
`FIG. 2
`
`Ex. 1003, Page 4
`
`

`

`U.S. Patent
`
`Feb.5,2002
`
`Sheet 3 of 57
`
`US 6,345,330 B2
`
`Computing System
`
`__.......----305
`
`CPU
`
`CPU/NB
`signals
`
`North BridQe s Primary PC I Bus
`r ____ _J______
`PCI Bus Bridge
`l Host
`l ¥ with
`l
`,- Interface
`Interface Dev.
`l Controller
`Pair And PBus
`
`I
`I
`
`Host Bus
`
`31 o......._ North
`Bridge
`I
`
`Peripheral System
`
`South
`
`I
`I
`I
`I
`I
`I
`
`I
`
`I
`
`•
`
`•
`
`I
`I
`I
`I
`Peripheral
`1
`I
`:
`I-C_P_U_/N_B_l.......---1 Interface
`l
`Controller
`Bridge signals I
`L-----~-----
`
`Second arv PC I Bus
`
`I
`PCI
`Device 1
`
`I
`PCI Add(cid:173)
`on Board 2
`
`FIG. 3
`
`Ex. 1003, Page 5
`
`

`

`U.S. Patent
`
`Feb.5,2002
`
`Sheet 4 of 57
`
`US 6,345,330 B2
`
`Computing System
`
`CPU
`
`,-----------
`!
`1 Integrated
`Main 1-----.-t,
`Memory
`: Host
`:
`.... 1 _...........~405
`:
`Interface
`Graphics ---·- Cntlr. &
`;
`Subsystem
`: North Bridge
`:
`!
`I
`
`-•
`
`I
`
`I
`
`...... - - · I I
`I
`I
`I
`I
`
`I
`
`I
`I
`I
`Peripheral System :
`I
`I
`I
`I
`I
`I
`Integrated
`1
`Other Bus!
`:
`Peripheral
`1 __,,,- r-. 410
`Interface
`:
`1 Cntlr. &
`r
`:
`S. Bridge
`I
`PCIBus1-----~-----~
`
`I
`PCI
`Device
`
`PCI
`Device
`
`FIG. 4
`
`Ex. 1003, Page 6
`
`

`

`U.S. Patent
`
`Feb.5,2002
`
`Sheet 5 of 57
`
`US 6,345,330 B2
`
`Primary PCI Bus
`
`...
`
`PCI Clock
`
`530
`\
`
`J~
`
`1 r
`
`10 Control
`
`
`H ost
`
`In terface
`ontroller
`C
`
`525
`
`1 r
`PCI Bus
`Controller
`
`I
`
`Asynchronous
`
`1,
`
`510_...,-
`
`XPBus
`Controller
`
`.~ J ~ .~
`
`_,,
`1-....
`
`~
`
`_.
`515
`XPBus ___ _ --
`1 592
`- -
`590~
`' -
`I
`7
`PD[3::0], P
`CNI -
`I
`I
`
`I ----
`
`Asynchronous
`
`i--505
`
`p
`eripheral
`
`I nterface
`Controller
`
`V 555
`
`~ PLL
`Clock ~520
`v-
`r---- - ----- - ,-- -----,
`I
`I
`PCK
`I PDR[3::0], PCNR
`-591
`I
`RESET# -'-594
`PCKR
`..... 595 t
`593-
`·- ----- ,_
`I
`- ____ J
`, , 1 rD1
`
`XPBus
`Controller
`
`i.--565
`
`575
`
`570
`~
`\
`I
`PLL • PCI Bus I\
`10
`560 Control
`
`Clock
`
`Controller
`
`PCI Clock u
`
`. h
`
`1,
`
`I
`PCI
`Device
`
`j ..
`
`,,
`
`Secondary
`PCI Bus
`
`\
`
`580
`
`FIG. 5
`
`Ex. 1003, Page 7
`
`

`

`U.S. Patent
`
`Feb.5,2002
`
`Sheet 6 of 57
`
`US 6,345,330 B2
`
`Flash Memory , 601
`
`BIOS/
`Configuration
`
`(600
`
`A
`
`C
`
`66 0
`'-
`
`PCICLK
`
`~ Slave Data Path
`
`~
`
`FIFO
`
`PCIA[2_
`r
`
`_
`
`PLL
`
`PCK
`
`632
`
`r------------------
`
`L...c...631
`
`!~~ ...... , .. '--..
`rr?;-· ...I
`
`670
`H A/DMUX ~~tR
`620
`61Q
`_______ /"' ---- ,£.. _____________ \.. 650
`: 1 ~ 622
`---"-+----~.&.
`611 ---.;.+'.-ir612~.:..
`Dec .. -..... _,___,
`613
`: 627.. 6!\23
`Parallel lo
`AD[31::0] out
`t--+,!---'---'----,1-+-1:.i Serial
`Mstr Data Path :
`,~ ~-;;;;-~&~
`Converter
`
`XPBus
`
`• PCK
`
`on? ~
`r
`PD1 ~
`r
`
`onr,
`
`617
`._--1 ...... --.,.~ ~ : r:-,
`616 ~
`FIFO ~ I Dec 11o1,~1-+---1
`618
`r---r,614 !
`PCI CNTL ~ Slave
`- - - -~ - ; ... ~ RD/WR
`Control
`
`~
`
`, . . - - - I
`
`. .__ .
`
`'''628
`624
`....-...-......)
`
`I
`
`1
`
`-
`
`I ~633
`, __ c_N_T_L_o_u1--.. ~I Parallel to Serial ___ P_CN_-~
`r I Converter
`
`r
`
`1
`
`p~~l530-r~i~~6175;
`14-_R_E_SE_T_#4----11 Reset Cntl
`I
`~
`
`.. ----t-R_E_S_ET_#_
`,
`11
`
`-• PDR3
`
`1,
`
`in
`
`642_ V
`
`:
`:
`Control
`:
`Cnt i-:-,-
`Decoder &
`PCNR
`Separate
`1 "';---------------------
`_ I Serial to Parallel 114--;,i----tl
`1-+-----=8.::."'-..,' .... Data Path 1<11-1-1H---t-C.,..N_T_L...,.1-
`-
`r 615 : : ...... --,....~ ,
`4-i Converter
`I -
`ii 625 +
`643/1
`......-----,
`s~I,
`~ j r
`(
`...,_ __ __,
`
`-
`
`Master
`RD/WR
`Control
`
`: :
`\ Control
`Encoder & ~ -:-t,
`: :
`4+- ,- Merge
`: :
`Data Path
`,,
`________________ ,,_
`Bus Controller
`
`Ho st
`PC I
`Bu s
`
`RESET#s
`
`CPU
`
`North
`Bridge
`
`-
`Translator ~ AD[3 ::OJ in -
`... ~--t------r~ & GPIO
`~ CPU CNTL ~
`.i!:===:j------..1
`~...______.)
`690
`
`- - _J "- - - - - - - -... -.. _____ ..,.
`
`-
`
`Serial to
`Parallel
`Converter
`
`,
`
`-
`
`~
`
`1
`
`~
`
`PDR1
`
`PORO
`
`PCKR
`
`VPD
`
`:
`
`'
`
`VPCK
`
`....,_,...._
`[ill] 641
`644
`t . ...1
`-7------------- ~----
`640
`Receiver 681 >-..
`Serial to
`: . ' . ' . ' . ' . '
`Parallel
`Converter
`680../"'-----r--'
`: .. ...
`
`Latch/Driver
`
`Graphics
`Controller
`
`Video Port Data [0::15]
`
`Video Pon Control
`
`FIG. 6
`
`Ex. 1003, Page 8
`
`

`

`d •
`r:JJ.
`•
`
`Primary PCI Bus
`Transaction Active
`Initiator Ready
`HI C Generates
`HIC Accepts Command
`HIC requests to retry
`Parity for NC; D/BE
`Used locally for config. 0
`Data Parity Error
`Address/System Parity Error
`HIC requests to be master
`Host grants bus
`
`Comment
`
`Positive decode, medium
`Posted Read operation
`
`S. Bus device requests bus
`
`Independent signal
`
`FIG. 7
`
`Encode
`
`HIC as Target (Default)
`Control Signal HIC to XPBus XPBusto HIC
`FRAME#
`Encode (BSO)
`Encode (BS 1)
`IRDY#
`TROY#
`Local
`DEVSEL#
`Local
`STOP#
`Local
`Encode
`PAR
`IDSEL
`Local
`PERR#
`Encode
`SERR#
`REQ#
`GNT#
`RST
`
`Decode
`
`Decode
`Decode
`Decode
`
`Ex. 1003, Page 9
`
`

`

`d •
`r:JJ.
`•
`
`HIC as Master
`Control Signal
`FRAME#
`IRDY#
`TROY#
`DEVSEL#
`STOP#
`PAR
`IDSEL
`PERR#
`SERR#
`REQ#
`GNT#
`RST
`
`HIC to XPBus
`
`XPBus to HIC
`Decode
`Decode
`
`Local
`Local
`Local
`Encode
`Local
`Encode
`
`Encode
`
`Decode
`
`Decode
`Decode
`Decode
`
`Primary PCI Bus
`Transaction Active
`Initiator Ready
`Receive from Target
`Receive from Target
`retry handles locally
`Parity for NC; 0/BE
`Used locally for config. 0
`Data Parity Error
`Address/System Parity Error
`HIC continue to be Master
`Arbiter grant bus to HIC
`
`Comment
`
`PCI device can end REQ#
`Arbiter can deassert GNT#
`Independent signal
`
`FIG. 8
`
`Ex. 1003, Page 10
`
`

`

`U.S. Patent
`
`Feb.5,2002
`
`Sheet 9 of 57
`
`US 6,345,330 B2
`
`Primary PCI Bus
`
`PCICLK
`
`AD
`
`--©-
`C/BE# ~ ..
`.. ~ \._ __ __,!
`~ ...
`
`IRDY#
`
`TROY#
`
`\
`I
`.... =ill:::: ~ ~
`
`BE#
`
`...... \ ~
`........... ~
`
`DSEL#
`
`STOP#
`
`PD0·3
`
`PDR0-3
`
`1.5 elk
`4"-E( _
`
`A
`
`______::,.,> 1111
`
`1.5 elk
`
`-<-->1111
`
`D
`
`Delay ~i
`cab1.;ii Secondary PCI Bus
`
`PCICLK
`< 2
`
`I
`
`>I
`
`I
`I
`FRN I~
`I
`
`AD
`
`C/BE#
`
`IRDY#
`
`TROY#
`
`DSEL#
`
`.. - -© -~~ ..
`.. ~
`... ~.~
`.. ~ .. ~
`~
`
`FIG. 9
`
`Ex. 1003, Page 11
`
`

`

`U.S. Patent
`
`Feb.5,2002
`
`Sheet 10 of 57
`
`US 6,345,330 B2
`
`Primary PCI Bus
`
`~ .... ~
`
`BE#
`
`......... ~ ..... :-:\ ...... _______ c=:_
`. . . . . . \ ~
`~
`.......... \,_ __ M_ed_iu_m_~~
`
`FRM
`
`AD
`
`C/BE#
`
`IRDY#
`
`TROY#
`
`DSEL#
`
`:1~<--->1111
`Gabl\
`i
`
`1.5clk
`
`A
`
`Delay
`
`D1
`1111
`
`D2
`
`Ill
`
`Secondary PCI Bus
`
`< 2
`
`>I
`c=
`........,,~-------------
`F~~~:
`
`I
`
`I
`I
`
`AD~~ · · · ·~ · · · · ·
`
`BE#
`
`IRDY#
`
`TROY#
`
`DSEL#
`
`...... ~ ..... :-:\..____ ____ .._r------_ ...
`
`'------~·
`
`·~········..
`
`FIG. 10
`
`....... L
`I
`I
`I
`I
`I
`:
`
`PD0·3
`
`I
`
`:
`I
`I
`I
`
`Ex. 1003, Page 12
`
`

`

`U.S. Patent
`
`Feb.5,2002
`
`Sheet 11 of 57
`
`US 6,345,330 B2
`
`Flash Memory ~ 11 Q 1
`(Optional)
`
`A
`
`C
`
`PCKR
`
`1
`
`-
`
`: •
`
`;_
`
`1
`_
`
`___,
`
`-
`
`XPBus
`
`PCKR~ -
`
`pnc~
`
`PDR2 -
`
`~
`
`111 j
`1116 -:--
`
`:
`
`1
`
`y
`
`.~~~~-------~~~L~~~~-1-~0
`ai~31 •r
`116~ JNDMUX
`:I PLL i--,
`1122
`: ~ Slave Data Path
`PCI CLK
`1132 r(1r .... 1_
`:. I FIFO ~ -
`1112
`: _, FIFO ~ ... ::---i::, __ A_D_[3_1_::0_J_o_ut_...,...,~.:------. -
`1111':
`1113 -1,>,-
`""\
`':
`Parallel to
`Mstr Data Path:: 1127, 1123
`: _
`Serial
`•
`PDR1;.
`PCI AD~
`Converter _
`,_
`Pn<:>t"I..
`L _ _,.._J---Tt ...... """''11-~
`___ , =
`. . . . . ~ ~ ~ , . .
`I r1133
`, .J Parallel to Serial
`,_ FIFO ~ Dec 111~----i
`~
`~ -
`' .....___,.'-
`r------!1, -911
`Converter
`___ P_C_N_R-1,_.a
`lJ
`------- y----------
`.., Transmitter
`1114
`:
`'~ -1128
`1118
`1130
`~
`pc1cNTL ~ sLv
`r1135
`,, L,-1124 :
`j
`:
`.-
`~~:Co~
`~ I Reset Cntl
`Control
`:,
`-1
`I
`~
`1-+------'B;;.:u:.::s+-a'~""'~ ~:r:~~~h i.~•-----+---1 ... ,_..,r,..;..,~..,;"'IL Serial to Parallel 1o1-M1-,1;.1,oc".l.ll"''--I
`:
`Decoder &
`._ ... ..., .... -.._--
`.-
`1 on ....i Converter
`MASTER -
`r1115
`'
`I
`(
`1142 Yl I,....._____, ~ PD3
`+,1125
`:1143
`-+.-- Merge -~
`-+.
`Control
`--+-
`Encoder &
`--
`--
`....., ............ - ... ~
`- - ~1141
`( ; ~ _l
`1140: ·------- -- -----------
`'-1190
`-1---------------V-id_eo_Po_rt_D_a_t_a"-[0_::_15-']-------~-~ Parallel 1' 189
`Ii
`r 1182
`I
`I
`
`CNTL out
`
`PCKR
`.._,,_. _____ .....,.____
`
`:
`
`RESET#
`
`1-
`
`RESET/I._
`
`~
`
`Data Path
`
`_
`
`Cntl
`
`1
`
`I
`I
`I
`I
`I
`I
`I
`I
`
`I
`I
`
`RD/WR
`Control
`
`Serial to
`________________ : , ___ , .. -------.Jolll~l--+----++---1 Parallel
`Bus Controller
`Translator
`AD[31::0] in
`Converter
`
`~
`
`~
`
`CPU CNTL
`~
`;_ & GPIO
`Latch/Drover 1------------.. ;_.,
`
`PD1
`
`PDQ
`
`PCK
`
`Video Port Control
`
`.-----,,:.:_R,ecelver
`
`VPD ~
`~ lo Serial 1-----+.....;..;..;;. __ ..,
`- Converte
`
`Secondary
`PCI Bus
`
`South
`Bridge
`
`~
`
`RESET#
`
`Video
`Capture
`Circuit
`
`Video-1---------------------·.il Clock
`Clock
`- , Doubler
`
`FIG. 11
`
`1183
`
`2X Video Clock -
`
`1184
`_
`
`VPCK ~
`
`Ex. 1003, Page 13
`
`

`

`d •
`r:JJ.
`•
`
`PIC as Target
`Control Signal PIC to XPBus
`Encode (BSD)
`FRAME#
`IRDY#
`Encode (BS1)
`TROY#
`Local
`DEVSEL#
`Local
`STOP#
`Local
`PAR
`Encode
`IDSEL
`Local
`PERR#
`Encode
`SERR#
`Encode
`REQ#
`GNT#
`RST
`
`Encode
`
`XPBus to PIC
`
`Decode
`Decode
`
`Decode
`Decode
`Decode
`
`Secondary PCI Bus
`Transaction Active
`Initiator Ready
`PIC Generates
`PIC Accepts Command
`PIC requests to retry
`Parity for NC; D/BE
`Used locally for config. 0
`Data Parity Error
`Address/System Parity Error
`PIC requests to be master
`PIC qrants bus to itself
`
`Comment
`
`Positive decode, medium
`Host can stop trans.
`
`P. Bus device requests bus
`
`Independent signal
`
`FIG. 12
`
`Ex. 1003, Page 14
`
`

`

`PIC as Master (Default)
`Control Signal PIC to XPBus
`FRAME#
`IRDY#
`TROY#
`DEVSEL#
`STOP#
`PAR
`IDSEL
`PERR#
`SERR#
`REQ#
`GNT#
`RST
`
`Local
`Local
`Local/Encode
`Encode
`Local
`Encode
`Encode
`
`Encode
`
`d •
`r:JJ.
`•
`
`XPBus to PIC
`Decode
`Decode
`
`Decode
`
`Decode
`Decode
`Decode
`
`Secondary PCI Bus
`Transaction Active
`Initiator Ready
`Receive from Target
`Receive from Target
`Receive from Target
`Parity for NC; D/BE
`Used locally for confiq. 0
`Data Paritv Error
`Address/System Parity Error
`PIC reauest to be Master
`Arbiter arant bus to PIC
`
`Comment
`
`Target can stop trans.
`
`-
`
`Independent signal
`
`FIG. 13
`
`Ex. 1003, Page 15
`
`

`

`U.S. Patent
`
`Feb.5,2002
`
`Sheet 14 of 57
`
`US 6,345,330 B2
`
`1400
`
`1455
`
`1450
`
`1405
`1410
`
`HIC
`
`PIC
`
`FIG. 14
`
`Ex. 1003, Page 16
`
`

`

`U.S. Patent
`US. Patent
`
`Feb. 5, 2002
`Feb.5,2002
`
`Sheet 15 of 57
`Sheet 15 of 57
`
`US 6,345,330 B2
`US 6,345,330 B2
`
`0
`LO
`
`1550
`
`LO -
`
`(.) -a..
`PIC
`
`LO
`LO
`
`LO -
`1555
`1582
`
`- - - -
`-
`----------
`
`1581
`
`0
`-
`1580
`«>
`LO
`
`LO
`
`~
`•
`(!)
`
`FIG.15
`-LL
`
`LO -
`C1')
`1583
`«>
`~
`1505
`LO -
`
`LO
`0
`
`0
`0
`
`LO -
`1500
`
`(.) -I
`
`Ex. 1003, Page 17
`
`Ex. 1003, Page 17
`
`

`

`U.S. Patent
`
`Feb.5,2002
`
`Sheet 16 of 57
`
`US 6,345,330 B2
`
`..._ __ o D----
`
`..._._-uo D1----......
`
`P44
`
`P1
`
`V44
`
`V1
`
`1605
`
`1610
`
`FIG. 16
`
`Ex. 1003, Page 18
`
`

`

`~ •
`'Jj_
`•
`
`ACM s XIS BUS Connector Plug PIN Position (88 pin):
`
`V23
`V24
`V25
`V26
`V27
`V28
`V29
`V30
`V31
`V32
`V33
`V34
`V35
`
`V36
`V37
`V38
`V39
`V40
`V41
`V42
`V43
`V44
`
`GND GND
`P&D DO+ RED VIDEO
`P&D DO - GND
`GND GREEN VIDEO
`P&D CLK + GND
`P&D CLK -
`BLUE VIDEO
`GND GND
`P&D D1 + HSYNC
`P&D 01 -
`VSYNC
`GND GND
`P&D D2 + DDC2: SCL
`P&D 02- DDC2: SDA
`Confiq 3 Confiq 2
`
`GND TV CV/CNTLO
`VPCK+ SVY/CNTL 1
`VPCK-
`SV C/CNTL2
`GND V33
`VPD+ V33
`VPD-
`V33
`GND V33
`GND V33
`GND V33
`
`V1
`V2
`V3
`V4
`vs
`V6
`V7
`VB
`V9
`V10
`V11
`V12
`V13
`
`V14
`V15
`V16
`V17
`V18
`V19
`V20
`V21
`V22
`
`P23
`P24
`P25
`P26
`P27
`P28
`P29
`P30
`P31
`P32
`P33
`P34
`P35
`
`P36
`P37
`P38
`P39
`P40
`P41
`P42
`P43
`P44
`
`GND
`GND
`PORO+
`PDO +
`PORO -
`PDO -
`GND GND
`PD1+ PDR1+
`PD1 -
`PDR1 -
`GND GND
`PD2+ PDR2+
`PD2 -
`PDR2 -
`GND GND
`PCK+ PCKR+
`PCK -
`PCKR -
`Confiq 1 Confiq 0
`
`GND GND
`PD3+ PDR3+
`PDR3 -
`PD3 -
`GND GND
`PCN+ PCNR+
`PCN-
`PCNR-
`Reserved vs
`Reserved
`VS
`Reserved V5
`
`P1
`P2
`P3
`P4
`P5
`P6
`P7
`P8
`P9
`P10
`P11
`P12
`P13
`
`P14
`P15
`P16
`P17
`P18
`P19
`P20
`P21
`P22
`
`FIG. 17
`
`Ex. 1003, Page 19
`
`

`

`d •
`r:JJ.
`•
`
`Pin No.
`P2
`P3
`PS
`P6
`P8
`pg
`P11
`P12
`P15
`P16
`P18
`P19
`P24
`P25
`P27
`P28
`P3Q
`P31
`P33
`P34
`P37
`P38
`P40
`P41
`P13
`P35
`P1 P4 P7 P10
`P14 P17 P23 P26
`P29,P32,P36,P39
`
`Symbol
`PORO+
`PORO -
`PDR1+
`PDR1 -
`PDR2+
`PDR2 -
`PCKR+
`PCKR -
`PDR3+
`PDR3 -
`PCNR+
`PCNR -
`PDQ+
`PDQ -
`PD1+
`PD1 -
`PD2 +
`PD2 -
`PCK+
`PCK -
`PD3 +
`PD3 -
`PCN+
`PCN -
`Confia Q
`Confia 1
`
`Signal
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`Static
`Static
`
`Standard
`
`3.3v or GND
`3.3v or GND
`
`Description
`Peripheral data reverse O +
`Peripheral data reverse O -
`Peripheral data reverse 1 +
`Peripheral data reverse 1 -
`Peripheral data reverse 2 +
`Peripheral data reverse 2 -
`Peripheral clock reverse +
`Peripheral clock reverse -
`Peripheral data reverse 3 +
`Peripheral data reverse 3 -
`Peripheral control reverse +
`Peripheral control reverse -
`Peripheral data O +
`Peripheral data Q -
`Peripheral data 1 +
`Peripheral data 1 -
`Peripheral data 2 +
`Peripheral data 2 -
`Peripheral clock +
`Perioheral clock -
`Peripheral data 3 +
`Perioheral data 3 -
`Peripheral control+
`Perioheral Control -
`Confiauration bit 0
`Confiouration bit 1
`
`GND
`
`GND
`
`Ground
`
`FIG. 18
`
`Ex. 1003, Page 20
`
`

`

`d •
`r:JJ.
`•
`
`Symbol
`Red Video
`Green Video
`Blue Video
`HSYNC
`VSYNC
`DDC2 SCL
`DDC2 SDA
`TV-CV/CNTL 0
`SV Y/CNTL 1
`SVC/CNTL2
`DO+
`DO -
`CLK+
`CLK-
`01 +
`01 -
`02 +
`02 -
`VPCK+
`VPCK -
`VPD+
`VPD -
`Confia 2
`Confia 3
`GND
`
`Signal
`AnaloQ
`Analoq
`Analoq
`
`TMDS
`TMDS
`TMDS
`TMDS
`TMDS
`TMDS
`TMDS
`TMDS
`LVDS
`LVDS
`LVDS
`LVDS
`
`Standard
`
`VESA DOC std 2
`VESA DOC std 2
`
`Super Video
`Super Video
`VESAP & D
`VESAP& D
`VESAP & D
`VESAP& D
`VESAP& D
`VESAP & D
`VESAP&D
`VESAP & D
`
`3.3v or GND
`3.3v or GND
`GND
`
`Description
`Video
`Video
`Video
`Horizontal Svnc
`Vertical Sync
`DOC Clock
`DOC Data
`TV Composite Video
`SV Luminance or Control 1
`SV Chrominance or Control 2
`Data O +
`Data O -
`Clock+
`Clock -
`Data 1 +
`Data 1 -
`Data 2 +
`Data 2 -
`Video Port Pixel Clock +
`Video Port Pixel Clock -
`Video Port Pixel Data +
`Video Port Pixel Data -
`Confiauration bit 2
`Confiauration bit 3
`Ground
`
`Pin No.
`V2
`V4
`V6
`VB
`V9
`V11
`V12
`V14
`V15
`V16
`V24
`V25
`V27
`V28
`V30
`V31
`V33
`V34
`V37
`V38
`V40
`V41
`V13
`V35
`V1 ,V3,V5,V7,
`V10,V23,V26,
`V29,V32,V36,
`V39,V42,V43,
`V44
`
`FIG. 19
`
`Ex. 1003, Page 21
`
`

`

`U.S. Patent
`
`Feb.5,2002
`
`Sheet 20 of 57
`
`US 6,345,330 B2
`
`Symbol
`p II RTN
`PDQ+
`PDQ -
`on1 RTN
`PD1+
`PD1 -
`PD2 RTN
`PD2 +
`PD2 -
`PD3 RTN
`PD3 +
`PD3 -
`PCK RTN
`PCK+
`PCK -
`PCN RTN
`PCN +
`PCN -
`PORO RTN
`PORO+
`PORO -
`PDR1 RTN
`PDR1+
`PDR1 -
`PDR2 RTN
`PDR2 +
`PDR2 -
`PDR3 RTN
`PDR3 +
`PDR3 -
`PCKR RTN
`PCKR +
`PCKR -
`PCNR t<IN
`1-'CNK+
`PCNR -
`RESET#
`
`1
`12
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`134
`~~
`36
`37
`
`Signal
`
`Data Rate
`
`Svnch Tn Dr'll
`
`1 Q X ~l""k r<>to
`
`Svnch. To PCK
`
`10 x clock rate
`
`Svnch. To PCK
`
`10 x clock rate
`
`Svnch. To PCK
`
`10 x clock rate
`
`Clock
`
`Clock rate
`
`Synch. To PCK
`
`1 0 x clock rate
`
`Synch. To PCKR
`
`10 x clock rate
`
`Synch. To PCKR
`
`10 x clock rate
`
`Synch. To PCKR
`
`1 O x clock rate
`
`Synch. To PCKR
`
`10 x clock rate
`
`Keverse Dir. Clock
`
`Clock rate
`
`::;ynch. 10 l"'L,l\t'(
`
`1 U x CIOCK rate
`
`Asynchronous
`
`FIG. 20
`
`Description
`rsf\1D
`, : .... ..;,;;I I Vn~ n,,t,:, 0 +
`C'.nmn11tor tn ""'
`Comouter to Perioheral LVDS Data O -
`r.No
`Comouter to Perioheral LVDS Data 1 +
`Comouter to Perioheral LVDS Data 1 -
`GND
`Comouter to Perioheral LVDS Data 2 +
`Comouter to Perioheral LVDS Data 2 -
`GND
`Comouter to Perioheral LVDS Data 3 +
`Comouter to Perioheral LVDS Data 3 -
`GND
`Computer to Peripheral LVDS Clock+
`Comouter to Perioheral LVDS Clock -
`GND
`Computer to Peripheral LVDS Control +
`Comouter to Perioheral LVDS Control -
`GND
`Peripheral to Computer LVDS Data O +
`Peripheral to Computer LVDS Data O -
`GND
`Peripheral to Computer LVDS Data 1 +
`Peripheral to Computer LVDS Data 1 -
`GND
`Peripheral to Computer LVDS Data 2 +
`Peripheral to Computer LVDS Data 2 -
`GND
`Peripheral to Computer LVDS Data 3 +
`Peripheral to Computer LVD::; Data 3 -
`GND
`Peripheral to Computer LVDS Clock+
`Peripheral to Computer LVD::; c.;lock -
`1..:,NU
`1-'enPheral to computer LVDS control +
`Perioheral to Comouter LVDS Control -
`Reset
`
`Ex. 1003, Page 22
`
`

`

`PCK CK+ CK+ CK+ CK+ CK+ CK-
`PDO BSO CMO# AOO
`A01
`A02 A03
`P01 BS1 CM1# A08
`A11
`A09 A10
`PD2 BS2 CM2# A16 A17 A18 A19
`PD3 BS3 CM3# A24 A25
`A26 A27
`
`CK-
`CK+ CK+ CK+ CK+ CK+ CK-
`CK-
`CK-
`CK-
`D02 D03
`A06 A07
`A04 A05
`BSO BEO# DOO D01
`A12 A13 A14 A15 BS1
`011
`009
`010
`BE1# 008
`017 D18
`019
`A20 A21
`A22 A23
`BS2 BE2# 016
`BS3 BE3# 024
`A28 A29 A30 A31
`025 D26
`027
`
`CK-
`CK-
`004 D05
`012
`013
`020
`021
`028
`029
`
`CK-
`CK-
`007
`006
`015
`014
`022 D23
`031
`030
`
`e • rJ'j
`
`•
`
`~
`~
`?'
`~Vt
`N
`
`= =
`
`N
`
`FIG. 21
`
`rJ'l =-~
`~ .....
`N
`lo-"
`;i ,...,
`Vt
`-..J
`
`Ex. 1003, Page 23
`
`

`

`d •
`r:JJ.
`•
`
`PCK-
`
`PCK+
`
`PCK-
`
`BSO
`BS1
`BS2
`BS3
`1
`
`CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17
`
`PCK+
`
`PCK-
`
`PCK+
`
`PCK-
`
`BSO
`BS1
`BS2
`BS3
`0
`
`BEO# 000
`BE1# 008
`BE2# 016
`BE3# 024
`CNO
`CN1
`
`005
`004
`003
`002
`001
`013
`012
`011
`010
`009
`021
`018
`017
`020
`019
`027
`026
`025
`029
`028
`CN2 CN3 CN4 CNS CN6
`
`007
`006
`015
`014
`022
`023
`031
`030
`CN7 CN8
`
`BSO
`BS1
`BS2
`BS3
`1
`
`CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17
`
`FIG. 22
`
`Ex. 1003, Page 24
`
`

`

`U.S. Patent
`
`Feb.5,2002
`
`Sheet 23 of 57
`
`US 6,345,330 B2
`
`PCK
`
`PCK
`
`PDO ~ < I[7 PDQ
`
`PD1
`
`PD2
`
`PD3
`
`FIG. 23
`
`PD1
`
`PD2
`
`PD3
`
`PCN
`
`Ex. 1003, Page 25
`
`

`

`U.S. Patent
`
`Feb.5,2002
`
`Sheet 24 of 57
`
`US 6,345,330 B2
`
`...
`
`, '
`10 Control
`
`Primary PCI Bus
`a
`
`, '
`PCI Bus
`Controller
`
`I
`
`I
`
`Host
`Interface
`Controller
`
`PC I Cloe<
`,,
`
`Asynchronous
`
`~
`
`XPBus
`PLL
`~
`Controller
`Clock
`A .. ~ .. Al
`r-- -- - ----- - ..... _ -----
`
`Peripheral
`Interface
`Controller
`
`RSTEH# ~ ~ , ~ , ,
`~ Controller
`..
`
`Asynchronous
`
`XPBus
`
`PLL
`Clock
`
`PCIClock v
`
`I
`10
`Control
`a
`
`Secondary
`PCI Bus
`
`,,
`
`PCI Bus
`Controller
`...
`, '
`
`I
`PCI
`Device
`
`FIG. 24
`
`XPBus------
`
`__ 1
`I
`PD
`[3::0]:
`I
`I
`I
`
`PCK
`
`1-....
`I /
`
`PCKR
`
`~
`
`-
`
`I
`I
`I PDR[3::0]
`I
`RSTEP# :
`I
`I
`- ~- ----- - -- ____ J
`
`Ex. 1003, Page 26
`
`

`

`U.S. Patent
`
`Feb.5,2002
`
`Sheet 25 of 57
`
`US 6,345,330 B2
`
`2501
`
`Flash Memory
`BIOS/
`Configuration
`
`/2500
`
`ol A
`
`2560-,
`NNDMUX
`
`C
`
`PLL
`
`PCK
`
`-
`
`1 ,
`
`ec ...
`
`r------------------
`:__e_g_531 l
`2570
`RD/WR
`251
`6X r.
`~--{-~~~-~-----\ .. 2550
`~nu ______ {
`-2522 :
`PLL 1--, .
`Slave Data Path ! '
`:
`PCI CLK
`FIFO i ~--~
`~ =-i_
`' ~ I
`' r
`2512
`i AD[31:~J::
`...
`2
`2511 ~~- •
`t..r,...I.__ __
`-.. Parallel to
`11
`u
`, ,_ FIFO
`2513 ...
`I---+•' ------i.....--111,.1
`i ~ Mstr Data Path ; : 2527, '1t 23
`. Converter
`. Serial
`CNTL out
`
`& Buffer
`I
`
`'
`
`' - - - - - -1 ••
`
`I'
`
`RESET#
`
`Reset&
`XPBus
`Parity Error
`Control
`
`I
`I
`I
`
`r
`
`'.
`
`...
`
`in
`
`Host
`PCI
`Bus
`
`RESET#
`
`4
`
`CPU CNTL
`
`CP~ ...
`• &GPIO
`.. :;--+------1:._, Latch/Driver
`North
`Bridge
`
`.. I+--____ ..___..__\ ___ __.
`2525
`2540--...;
`~-------------------...... ---
`----
`2590_)
`.. ~1--1----------------V-id_e_o_P_o_rt_D_a_ta-'[0_:1_5]:__ _______ -l Serial to
`Parallel
`...... 1--1----------------V-id_e_o_P_o_rt_C_on_t_ro_l ----------I Converter
`Graphics
`Controller
`
`I
`
`2580_7
`
`Receiver
`
`.
`
`--.,
`
`FIG. 25
`
`PCI A~
`....
`2517t:::::::l:i'~~':::t•.j~~F~IF~O~
`Enc ~
`!!
`2536,
`2516~L-l-- ~ . · r.._;4-----1
`:
`_I
`---.,
`. ...
`'
`2518..:.....L+-"-- ~:~
`l '-2528
`2530-1--,
`2514----~: ~---
`: :
`'
`------------------~
`I~
`,,
`-- 2524
`..
`• • ,,
`PCI CNTL r?", Slave
`Transmitter
`PCK
`U,,-'
`RD/WR >-- 11
`r-- --------------------
`:
`'
`Control ~
`Reset &
`Control
`1 •
`1
`~ Decoder&
`XPBus
`:
`RSTEt:ti
`Parity Error
`:
`Cntl
`: '
`Separate
`..
`1,.-;.• __ _ __ B::;:u::.:s .... •._.:..w Data Path
`··-----'
`Detect ~ i
`"
`,r
`--........2546
`..
`~C~o~nt~rol:...._--11
`2515-r-. :
`::
`·· ..
`..
`'\..._
`I
`SYNC
`-ft- Master
`2 542-' _.__..-,---
`+~ Encoder & _ f-!-+
`I
`~+
`.. .. I
`
`-
`
`RD/WR
`Control
`
`I
`I
`I
`I
`
`Control
`
`Merge
`Data Path
`
`I
`I
`
`~----------------''-
`Bus Controller
`
`I
`II
`
`-- a---- ---
`Trans ator _ AD[J ::OJ in
`
`-+-
`
`·' ...
`
`PDR3
`
`PDR2
`
`-
`
`Serial to
`Parallel
`Converter
`
`'-.
`...
`.
`.... ...
`. ...
`
`XPBus
`
`PCK
`
`PD3 ..
`PD2 --.,
`. .
`PD1
`c,nn --..
`
`RSTEP#
`
`PDR1
`
`PORO
`
`PCKR
`
`VPD
`
`t
`
`' I
`VPCK:
`
`Ex. 1003, Page 27
`
`

`

`U.S. Patent
`
`Feb.5,2002
`
`Sheet 26 of 57
`
`US 6,345,330 B2
`
`2601
`Flash Memory/
`(Optional)
`
`/2600
`
`1NDMUX Cntl
`
`I..
`
`•
`
`• 1
`
`-
`
`PCKR
`;__.c_g_631
`
`~
`
`I
`
`CNTL out
`
`RESET#
`~
`
`Parity Error ..
`
`:
`
`2670
`2660-._ '--1 DI A I RD:R
`2620
`(2610
`:-,~-Sia~;-DaiaP;ii,-: :-£ ~2ff22-
`11 ~~LR'
`PCICLK
`1---'----'-----, ....... - 1
`_ / . I
`I : ,-...J.
`FIFO H Enc 1-f--+
`2632 ~ I......_ __
`,
`-.-
`2612
`: : =
`2611 --:--l-t'-
`u
`""'
`1 '--
`FIFO ~ Deci..,_;H--::=~--A_D_[3_1_::o_J_ou_t_f--T--I-..
`2613
`"" Parallel to
`; ._ Mstr Data Path : 12627,
`~€ 23
`~~~~~rter
`PCI A~
`;
`2617
`~ ~ ~~ _&_B_u_n ... er_26361
`~~~:ts& L!
`: RSTEH~
`2616-~ - ~ l< l~ t -1 - - - -1
`2618- :
`'
`,. ,
`,
`2628
`2614-- :
`t---..---+-o-:-+---1--'-PC::;.:K-"R"--1 •----~o-n~r~~----------:
`PCI CNTL ~ SLV
`Transmitter
`~-- 2624
`"
`r-------------------
`M~----~.......+-.;.r; RD,WR 1 - (cid:173)
`..
`~
`Control
`Control
`Reset&
`1-i+- Decoder &
`XPBus
`RSTEP#
`Cntl
`:
`Separate
`Parity Error
`1
`Bus
`.. Data Path
`.__D_e_te_ct _ __ ,~ 2646
`
`lnml
`
`CNTL
`
`2Ei42-
`
`I __... __ _
`
`XPBus
`
`PCKR_ ..
`
`PDR3-
`
`PDR2-
`
`PDR1-
`
`--..
`
`PD3
`
`PD2
`
`PD1
`
`PDQ
`
`PCK
`
`Secondary
`
`PCI Bus 2615----~~-(cid:173)
`~
`MASTER
`-4-,
`RD/WR
`Control
`
`I
`I
`I
`
`..
`
`I ~ - - -... ,.......J
`
`-WJ__
`, ' ':
`
`Control
`Encoder&-~
`Merge
`Data Path
`
`14---1-....... ---1 Serial to
`
`..
`
`Parallel
`Converter
`
`AD[31::0] in
`
`South
`Brid9e
`
`..
`
`RESET#
`
`2690_)
`
`.~641
`
`I
`
`. .
`
`·--------------------
`- - - - Receiver
`
`.· ...
`
`~
`
`-.
`..
`-
`-
`
`Video Port Data [0::15]
`
`• Parallel
`Video
`::
`to Serial
`Capture
`Circuit -+--------------V-id-eo_P_o_rt_C_o-nt_ro_l---------1.,.~~-co_n_ve~rt-e_.i\
`2683--...t
`2682~
`2689
`I Clock
`I 2X Video Clock~ •
`2684 y~·-1----1 .. ~
`l
`-i-,1~-~-k+--------------------a.l~I Doubler
`
`VPD --..
`
`VPCK
`
`FIG. 26
`
`Ex. 1003, Page 28
`
`

`

`U.S. Patent
`
`Feb.5,2002
`
`Sheet 27 of 57
`
`US 6,345,330 B2
`
`.______,o D--__,
`
`.....___o D1----....J
`
`V18
`
`E1
`
`P44
`
`P1
`
`2710
`
`2705
`
`FIG. 27
`
`Ex. 1003, Page 29
`
`

`

`~ •
`00
`•
`
`ACM s CMI BUS Connector Plug PIN Position (88 pin):
`GND GND
`E1
`P23
`P&D DO+ TPA+NPD+
`P24
`E2
`P&D DO - TPA-NPD-
`E3
`P25
`GND
`GND
`E4
`P26
`P&D CLK + TPB+ NPCK+
`ES
`P27
`P&D CLK - TPB-NPCK-
`E6
`P28
`GND
`1394 Detect
`E7
`P29
`P&D D1 + Reserved
`P30
`E8
`P&D D1 - Reserved
`E9
`P31
`GND Reserved
`E10
`P32
`P&D D2 + Reserved
`E11
`P33
`P&D D2- Reserved
`E12
`P34
`DFP Detect Confio 2
`E13
`P35
`
`GND GND
`PDO+ PORO+
`PDO -
`PORO -
`GND GND
`PD1 + PDR1+
`PD1 - PDR1 -
`GND GND
`PD2+ PDR2+
`PD2 - PDR2 -
`GND GND
`PCK+ PCKR+
`PCK - PCKR -
`Config 1 Config 0
`
`GND V33
`GND V33
`GND V33
`V33 V33
`V33 V33
`V33 V33
`vs V12
`vs V12
`vs V12
`
`V1
`V2
`V3
`V4
`V5
`V6
`V7
`VB
`V9
`
`GND GND
`P36
`PD3+ PDR3+
`P37
`P38
`PD3 - PDR3 -
`RSTEH# RSTEP#
`P39
`P40 GREEN VIDEO RED VIDEO
`P41
`GND GND
`P42
`HSYNC BLUE VIDEO
`P43
`VSYNC GND
`P44
`DDC2: SCL DDC2: SDA
`
`E14
`E15
`E16
`E17
`E18
`E19
`E20
`E21
`E22
`E23
`E24
`E25
`E26
`
`V10
`V11
`V12
`V13
`V14
`V15
`V16
`V17
`V18
`
`P1
`P2
`P3
`P4
`PS
`P6
`P7
`P8
`P9
`P10
`P11
`P12
`P13
`
`P14
`P15
`P16
`P17
`P18
`P19
`P20
`P21
`P22
`
`FIG. 28
`
`Ex. 1003, Page 30
`
`

`

`Symbol
`PORO+
`PDRO -
`PDR1+
`PDR1 -
`PDR2 +
`PDR2 -
`PCKR+
`PCKR -
`PDR3+
`PDR3 -
`PDO+
`PDO -
`PD1 +
`PD1 -
`PD2 +
`PD2 -
`PCK+
`PCK -
`PD3+
`PD3 -
`Config 0
`Config 1
`RESTEP#
`RESTEH#
`Red Video
`Green Video
`Blue Video
`HSYNC
`VSYNC
`DDC2 SCL
`D0C2 SOA
`GNO
`
`Pin No.
`P2
`P3
`P5
`PG
`P8
`pg
`P11
`P12
`P15
`P16
`P24
`P25
`P27
`P28
`P30
`P31
`P33
`P34
`P37
`P38
`P13
`P35
`P17
`P39
`P18
`P40
`P20
`P42
`P43
`P44
`P22
`P1,P4,P7,P10,
`P14,P19,P21,
`P23,P26,P29,
`P32 P36 P41
`
`Standard
`
`Signal
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`LVDS
`Static
`Static
`TIL
`TIL
`Analog
`Analog
`Analog
`TIL
`TIL
`TIL VESA DDC std 2
`TTL VESA DOC std 2
`GND
`
`3.3vorGND
`3.3vorGND
`3.3v
`3.3v
`
`d •
`r:JJ.
`•
`
`Description
`Peripheral data reverse O +
`Peripheral data reverse O -
`Peripheral data reverse 1 +
`Peripheral data reverse 1 -
`Peripheral data reverse 2 +
`Peripheral data reverse 2 -
`Peripheral clock reverse +
`Peripheral clock reverse -
`Peripheral data reverse 3 +
`Peripheral data reverse 3 -
`Peripheral data O +
`Peripheral data O -
`Peripheral data 1 +
`Peripheral data 1 -
`Peripheral data 2 +
`Peripheral data 2 -
`Peripheral clock +
`Peripheral clock -
`Peripheral data 3 +
`Peripheral data 3 -
`Configuration bit 0
`Configuration bit 1
`Reset and Parity Error from console to ACM
`Reset and Parity Error from ACM to console
`Video
`Video
`Video
`Horizontal Sync
`Vertical Sync
`DOC Clock
`DOC Data
`Ground
`
`FIG. 29
`
`Ex. 1003, Page 31
`
`

`

`Pin No.
`E2
`E3
`E5
`E6
`E15
`E16
`E18
`E19
`E21
`E22
`E24
`E25
`E13
`E26
`E1, E4, E14,
`E17,E20,E23
`
`Symbol Siqnal
`VPD+/TPA+
`VPD-/TPA-
`VPCK+/TPA+
`VPCK-/TPA-
`DO+ TMDS
`DO -
`TMDS
`CLK+ TMDS
`CLK-
`TMDS
`D1+ TMDS
`TMDS
`D1 -
`D2 + TMDS
`D2 -
`TMDS
`Confiq 2
`Config 3
`GND
`
`Standard
`LVDS or 1394
`LVDS or 1394
`LVDS or 1394
`LVDS or 1394
`VESAP & D
`VESAP & D
`VESAP & D
`VESAP& D
`VESAP& D
`VESAP & D
`VESAP & D
`VESAP& D
`
`GND
`
`E7
`E8
`E9
`E10
`E11
`E12
`
`Reserved
`Reserved
`Reserved
`TV-CV/reserved
`SV Y /reserved
`SV C/reserved
`
`NTSC
`