UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`AddIESS. COMMISSIONER FOR PATENTS
`PO Box 1450
`Alexandria, Vitgmia 22313-1450
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`
`
`
`
`F ING OR 371 (C) DATE
`
`
`
`[IF
`
`APPLICATION NUMBER
`
`FIRST NAMED APPLICANT
`
`ATTY. DOCKET No./TITLE
`
`13/087,912
`
`04/15/2011
`
`William W.Y. Chu
`
`ACQI-010/19US
`310578-2066
`CONFIRMATION NO. 7269
`
`58249
`COOLEY LLP
`ATTN: Patent Group
`Suite 1 100
`777 - 6th Street, NW
`WASHINGTON, DC 20001
`
`POA ACCEPTANCE LETTER
`
`HIIlIlIlIllIIIIIIIIIIIIIIIIIllllllllllllllIIIIIIIIIIHIIUIIIIIIIIIIIIIIIII
`000000047370250
`
`Date Mailed: 04/28/2011
`
`NOTICE OF ACCEPTANCE OF POWER OF ATTORNEY
`
`This is in response to the Power of Attorney filed 04/15/2011.
`
`The Power of Attorney in this application is accepted. Correspondence in this application will be mailed to the
`above address as provided by 37 CFR 1.33.
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`/dpham/
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`
`Office of Data Management, Application Assistance Unit (571) 272-4000, or (571) 272-4200, or 1-888-786-0101
`
`page 1 of 1
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`Ex. 1009, Page 190
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`Ex. 1009, Page 190
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`Attorney Docket No. ACQI—010/19US 310578—2066
`
`PATENT
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Application of: William W.Y. Chu
`
`Confirmation NO:
`
`7269
`
`Application No.:
`
`13/087,912
`
`Group Art Unit:
`
`21 1 1
`
`Filed:
`
`*
`
`April 15, 2011
`
`Examiner:
`
`Title: MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL
`
`CHANNEL COMPRISING UNIDIRECTIONAL SERIAL BIT CHANNELS
`
`
`
`Mail Stop: Missing Parts
`Commissioner for Patents
`
`PO. BOX 1450
`
`Alexandria, VA 22313-1450
`
`In response to the Notice to File Corrected Application Papers mailed April 28, 2011,
`enclosed are:
`
`[X]
`[X]
`
`Substitute Specification—Markup
`Substitute Specification-Clean
`
`The substitute Specification includes all of the changes made in the preliminary
`amendment, with the exception that new Paragraph NOS.
`[0041.1] and [0041.2]
`from the
`Preliminary Amendment have been renumbered as Paragraph NOS. [0042] and [0043] in both the
`Clean and Markup versions, and the paragraphs following have been renumbered accordingly.
`No new matter has been added.
`
`The Commissioner is hereby authorized to charge any appropriate fees that may be
`required by this paper to Deposit Account NO. 50~1283.
`
`Respectfully submitted,
`Cooley LLP
`
`Date: Mayii, 2011
`
`Customer No. 58249
`Cooley LLP
`777 6 Street NW, Suite 1100
`-
`Washington, DC 20001
`Tel: (650) 843-5852
`Fax: (202) 842-7899
`
`v
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`Cliff Z. Llu
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`
`938764 v1/HN
`
`Ex. 1009, Page 191
`
`Ex. 1009, Page 191
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`

`

`AGQI—Gl—G/l—GUS—31—05—78—2—052
`
`ACS 21-010/19US 310578-2066
`
`PATENT
`
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING
`DIFFERENTIAL SIGNAL CI-LANNEL COMPRISING UNDI—REGT—ION—A—L
`UNIDIRECTIONAL SERIAL BIT CI-LANNELS
`
`CROSS REFERENCE TO RELATED APPLICATIONS
`
`[0001] This application is a continuation of US. Application No. 12/504,534 filed July
`
`16 2009 which is a continuation of US. Application No. 12/077,503 filed March 18,
`
`2008 (Now US. Patent No. 7,676,624), which is a continuation of US. nonprovisional
`
`Application No. 1 1/ 166,656, filed June 24, 2005 (Now US. Patent No. 7,376,779), which
`
`is a continuation of US. nonprovisional Application No. 11/097,694, filed March 31,
`
`2005 (Now US Patent No. 7,363,415), which is a continuation of US. nonprovisional
`
`Application No. 10/772,214, filed February 3, 2004 (Now US. Patent No. 7,099,981),
`
`which is a continuation of US. nonprovisional Application No. 09/569,758, filed May 12,
`
`2000 (Now US patent no. 6,718,415), and which claimed priority to US. Provisional
`
`Application No. 60/134,122 filed May 14, 1999. These applications are hereby
`
`incorporated by reference in their entirety.
`
`BACKGROUND OF THE INVENTION
`
`[0002] The present invention relates to computing devices. More particularly, the present
`
`invention provides a system including a plurality of computer modules that can
`
`independently operate to provide backup capability, dual processing, and the like. Merely
`
`by way of example, the present invention is applied to a modular computing environment
`
`for desk top computers, but it will be recognized that the invention has a much wider
`
`range of applicability. It can be applied to a server as well as other portable or modular
`
`computing applications.
`
`[0003] Many desktop or personal computers, which are commonly termed PCs, have been
`
`around and used for over ten years. The PCs often come with state—of—art microprocessors
`
`such as the Intel PentiumTM microprocessor chips. They also include a hard or fixed disk
`
`drive such as memory in the giga—bit range. Additionally, the PCs often include a random
`
`access memory integrated circuit device such as a dynamic random access memory
`
`938747 vl/HN
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`Ex. 1009, Page 192
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`Ex. 1009, Page 192
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`

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`device, which is commonly termed DRAM. The DRAM devices now provide up to
`
`millions of memory cells (i.e., mega—bit) on a single slice of silicon. PCs also include a
`
`high resolution display such as cathode ray tubes or CRTs. In most cases, the CRTs are at
`
`least 15 inches or 17 inches or 20 inches in diameter. High resolution flat panel displays
`
`are also used with PCs.
`
`[0004] Many external or peripheral devices can be used with the PCs. Among others,
`
`these peripheral devices include mass storage devices such as a ZipTM Drive product sold
`
`by Iomega Corporation of Utah. Other storage devices include external hard drives, tape
`
`drives, and others. Additional devices include communication devices such as a modem,
`
`which can be used to link the PC to a wide area network of computers such as the Internet.
`
`Furthermore, the PC can include output devices such as a printer and other output means.
`
`Moreover, the PC can include special audio output devices such as speakers the like.
`
`[0005] PCs also have easy to use keyboards, mouse input devices, and the like. The
`
`keyboard is generally configured similar to a typewriter format. The keyboard also has
`
`the length and width for easily inputting information by way of keys to the computer. The
`
`mouse also has a sufficient size and shape to easily move a curser on the display from one
`
`location to another location.
`
`[0006] Other types of computing devices include portable computing devices such as
`
`“laptop” computers and the like. Although somewhat successful, laptop computers have
`
`many limitations. These computing devices have poor display technology. In fact, these
`
`devices often have a smaller flat panel display that has poor viewing characteristics.
`
`Additionally, these devices also have poor input devices such as smaller keyboards and
`
`the like. Furthermore.
`
`these devices have limited common platforms to transfer
`
`information to and from these devices and other devices such as PCs.
`
`[0007] Up to now, there has been little common ground between these platforms
`
`including the PCs and laptops in terms of upgrading, ease—of—use, cost, performance, and
`
`the like. Many differences between these platforms, probably somewhat intentional, has
`
`benefited computer manufacturers at the cost of consumers. A drawback to having two
`
`separate computers is that the user must often purchase both the desktop and laptop to
`
`have “total” computing power, where the desktop serves as a “regular” computer and the
`
`laptop serves as a “portable” computer. Purchasing both computers is often costly and
`
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`Ex. 1009, Page 193
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`Ex. 1009, Page 193
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`runs “thousands” of dollars. The user also wastes a significant amount of time
`
`transferring software and data between the two types of computers. For example, the user
`
`must often couple the portable computer to a local area network (i.e., LAN), to a serial
`
`port with a modem and then manually transfer over files and data between the desktop and
`
`the portable computer. Alternatively, the user often must use floppy disks to “zip” up
`
`files and programs that exceed the storage capacity of conventional floppy disks, and
`
`transfer the floppy disk data manually.
`
`[0008] Another drawback with the current model of separate portable and desktop
`
`computer is that the user has to spend money to buy components and peripherals the are
`
`duplicated in at least one of these computers. For example, both the desktop and portable
`
`computers typically include hard disk drives, floppy drives, CD—ROMs, computer
`
`memory, host processors, graphics accelerators, and the like. Because program software
`
`and supporting programs generally must be installed upon both hard drives in order for
`
`the user to operate programs on the road and in the office, hard disk space is often wasted.
`
`[0009] One approach to reduce some of these drawbacks has been the use of a docking
`
`station with a portable computer. Here, the user has the portable computer for “on the
`
`road” use and a docking station that houses the portable computer for office use.
`
`[0010] Similar to separate desktop and portable computers, there is no commonality
`
`between two desktop computers. To date, most personal computers are constructed with a
`
`single motherboard that provides connection for CPU and other components in the
`
`computer. Dual CPU systems have been available through Intel’s slot 1 architecture. For
`
`example, two Pentium II cartridges can be plugged into two “slot 1” card slots on a
`
`motherboard to form a Dual—processor system. The two CPU’s share a common host bus
`
`that connects to the rest of the system, e.g. main memory, hard disk drive, graphics
`
`subsystem, and others. Dual CPU systems have the advantage of increased CPU
`
`performance for the whole system. Adding a CPU cartridge requires no change in
`
`operating systems and application software. However, dual CPU systems may suffer
`
`limited performance improvement if memory or disk drive bandwidth becomes the
`
`limiting factor. Also, dual CPU systems have to time-share the processing unit in running
`
`multiple applications. CPU performance improvement efficiency also depends on
`
`software coding structure. Dual CPU systems provide no hardware redundancy to help
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`Ex. 1009, Page 194
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`fault tolerance. In running multiple applications, memory and disk drive data throughput
`
`will become the limiting factor in improving performance with multi-processor systems.
`
`[0011] The present invention generally relates to computer interfaces. More specifically,
`
`the present invention relates to an interface channel that interfaces two computer interface
`
`buses that operate under protocols that are different from that used by the interface
`
`channel.
`
`[0012] Interfaces coupling two independent computer buses are well known in the art. A
`
`block diagram of a computer system utilizing such a prior art interface is shown in Fig. 5.
`
`In Fig. 5, a primary peripheral component interconnect (PCI) bus 505 of a notebook PC
`
`500 is coupled to a secondary PCI bus 555 in a docking system 550 (also referred to as
`
`docking station 550) through high pin count connectors 501 and 502, which are normally
`
`mating connectors. The high pin count connectors 501 and 502 contain a sufficiently
`
`large number of pins so as to carry PCI bus signals between the two PCI buses without
`
`any translation. The main purpose for interfacing the two independent PCI buses is to
`
`allow transactions to occur between a master on one PCI bus and a target on the other PCI
`
`bus. The interface between these two independent PCI buses additionally includes an
`
`optional PCI to PCI bridge 560, located in the docking station 550, to expand the add on
`
`capability in docking station 550. The bridge 560 creates a new bus number for devices
`
`behind the bridge 560 so that they are not on the same bus number as other devices in the
`
`system thus increasing the add on capability in the docking station 550.
`
`[0013] An interface such as that shown in Fig. 5 provides an adequate interface between
`
`the primary and secondary PCI buses. However, the interface is limited in a number of
`
`ways. The interface transfers signals between the primary and secondary PCI buses using
`
`the protocols of a PCI bus. Consequently, the interface is subject to the limitations under
`
`which PCI buses operate. One such limitation is the fact that PCI buses are not cable
`
`friendly. The cable friendliness of the interface was not a major concern in the prior art.
`
`However, in the context of the computer system of the present invention, which is
`
`described in the present inventor’s (William W.Y. Chu’s) application for “Personal
`
`Computer Peripheral Console With Attached Computer Module” filed concurrently with
`
`the present application on Sep. 8, 1998 and incorporated herein by reference, a cable
`
`friendly interface is desired for interfacing an attached computer module (ACM) and a
`
`peripheral console of the present invention. Furthermore, as a result of operating by PCI
`
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`Ex. 1009, Page 195
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`Ex. 1009, Page 195
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`

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`protocols, the prior art interface includes a very large number of signal channels with a
`
`corresponding large number of conductive lines (and a similarly large number of pins in
`
`the connectors of the interface) that are commensurate in number with the number of
`
`signal lines in the PCI buses which it interfaces. One disadvantage of an interface having
`
`a relatively large number of conductive lines and pins is that it costs more than one that
`
`uses a fewer number of conductive lines and pins. Additionally, an interface having a
`
`large number of conductive lines is bulkier and more cumbersome to handle. Finally, a
`
`relatively large number of signal channels in the interface renders the option of using
`
`differential voltage signals less viable because a differential voltage signal method would
`
`require duplicating a large number of signal lines. It is desirable to use a low voltage
`
`differential signal (LVDS) channel in the computer system of the present invention
`
`because an LVDS channel is more cable friendly, faster, consumes less power, and
`
`generates less noise, including electromagnetic interferences (EMI), than a PCI channel.
`
`The term LVDS is herein used to generically refer to low voltage differential signals and
`
`is not intended to be limited to any particular type of LVDS technology.
`
`[0014] Thus, what is needed are computer systems that can have multiple computer
`
`modules. Each computer module has dedicated memory and disk drive, and can operate
`
`independently.
`
`BRIEF SUMMARY OF THE INVENTION
`
`[0015] According to the present invention, a technique including a method and device for
`
`multi-module computing is provided. In an exemplary embodiment, the present invention
`
`provides a system including a plurality of computer modules that can independently
`
`operate to provide backup capability, dual processing, and the like.
`
`[0016] In a specific embodiment, the present invention provides a computer system for
`
`multi—processing purposes. The computer system has a console comprising a first
`
`coupling site and a second coupling site, e. g., computer module bay. Each coupling site
`
`comprises a connector. The console is an enclosure that is capable of housing each
`
`coupling site. The system also has a plurality of computer modules, where each of the
`
`computer modules is coupled to one of the connectors. Each of the computer modules has
`
`a processing unit, a main memory coupled to the processing unit, a graphics controller
`
`coupled to the processing unit, and a mass storage device coupled to the processing unit.
`
`938747 vl/HN
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`Ex. 1009, Page 196
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`Each of the computer modules is substantially similar in design to each other to provide
`
`independent processing of each of the computer modules in the computer system.
`
`[0017] In an alternative specific embodiment, the present invention provides a multi-
`
`processing computer system. The system has a console comprising a first coupling site
`
`and a second coupling site. Each coupling site comprises a connector. The console is an
`
`enclosure that is capable of housing each coupling site. The system also has a plurality of
`
`computer modules, where each of the computer modules is coupled to one of the
`
`connectors. Each of the computer modules has a processing unit, a main memory coupled
`
`to the processing unit, a graphics controller coupled to the processing unit, a mass storage
`
`device coupled to the processing unit, and a video output coupled to the processing unit.
`
`Each of the computer modules is substantially similar in design to each other to provide
`
`independent processing of each of the computer modules in the computer system. A
`
`video switch circuit is coupled to each of the computer modules through the video output.
`
`The video switch is configured to switch a video signal from any one of the computer
`
`modules to a display.
`
`[0018] Numerous benefits are achieved using the present invention over previously
`
`existing techniques. In one embodiment, the invention provides improved processing and
`
`maintenance features. The invention can also provide increased CPU performance for the
`
`whole system. The invention also can be implemented without changes in operating
`
`system and application software. The present invention is also implemented using
`
`conventional technologies that can be provided in the present computer system in an easy
`
`and efficient manner.
`
`[0019] In another embodiment, the invention provides at least two users to share the same
`
`modular desktop system. Each user operates on a different computer module. The other
`
`peripheral devices, i.e. CDROM, printer, DSL connection, etc. can be shared. This
`
`provides lower system cost, less desktop space and more efficiency. Depending upon the
`
`embodiment, one or more of these benefits can be available. These and other advantages
`
`or benefits are described throughout the present specification and are described more
`
`particularly below.
`
`[0020] In still further embodiments, the present invention provides methods of using
`
`multiple computer modules.
`
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`Ex. 1009, Page 197
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`[0021] The present invention encompasses an apparatus for bridging a first computer
`
`interface bus and a second computer interface bus. where each of the first and second
`
`computer interface buses have a number of parallel multiplexed address/data bus lines and
`
`operate at a clock speed in a predetermined clock speed range having a minimum clock
`
`speed and a maximum clock speed. The apparatus comprises an interface channel having
`
`a clock line and a plurality of bit lines for transmitting bits; a first interface controller
`
`coupled to the first computer interface bus and to the interface channel to encode first
`
`control signals from the first computer interface bus into first control bits to be transmitted
`
`on the interface channel and to decode second control bits received from the interface
`
`channel into second control signals to be transmitted to the first computer interface bus;
`
`and a second interface controller coupled to the interface channel and the second
`
`computer interface bus to decode the first control bits from the interface channel into third
`
`control signals to be transmitted on the second computer interface bus and to encode
`
`fourth control signals from the second computer interface bus into the second control bits
`
`to be transmitted on the interface channel.
`
`[0022] In one embodiment, the first and second interface controllers comprise a host
`
`interface controller (HIC) and a peripheral interface controller (PIC), respectively, the first
`
`and second computer interface buses comprise a primary PCI and a secondary PCI bus,
`
`respectively, and the interface channel comprises an LVDS channel.
`
`[0023] The present invention overcomes the aforementioned disadvantages of the prior art
`
`by interfacing two PCI or PCI-like buses using a non-PCI or non-PCI-like channel. In the
`
`present invention, PCI control signals are encoded into control bits and the control bits,
`
`rather than the control signals that they represent, are transmitted on the interface channel.
`
`At the receiving end, the control bits representing control signals are decoded back into
`
`PCI control signals prior to being transmitted to the intended PCI bus.
`
`[0024] The fact that control bits rather than control signals are transmitted on the interface
`
`channel allows using a smaller number of signal channels and a correspondingly small
`
`number of conductive lines in the interface channel than would otherwise be possible.
`
`This is because the control bits can be more easily multiplexed at one end of the interface
`
`channel and recovered at the other end than control signals. This relatively small number
`
`of signal channels used in the interface channel allows using LVDS channels for the
`
`interface. As mentioned above, an LVDS channel is more cable friendly, faster,
`
`938747 vl/HN
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`Ex. 1009, Page 198
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`Ex. 1009, Page 198
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`

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`consumes less power, and generates less noise than a PCI bus channel, which is used in
`
`the prior art to interface two PCI buses. Therefore, the present invention advantageously
`
`uses an LVDS channel for the hereto unused purpose of interfacing PCI or PCI—like buses.
`
`The relatively smaller number of signal channels in the interface also allows using
`
`connectors having smaller pins counts. As mentioned above an interface having a smaller
`
`number of signal channels and, therefore, a smaller number of conductive lines is less
`
`bulky and less expensive than one having a larger number of signal channels. Similarly,
`
`connectors having a smaller number of pins are also less expensive and less bulky than
`
`connectors having a larger number of pins.
`
`[0025] In one embodiment, the present invention encompasses an apparatus for bridging a
`
`first computer interface bus and a second computer interface bus, in a microprocessor
`
`based computer system where each of the first and second computer interface buses have
`
`a number of parallel multiplexed address/data bus lines and operate at a clock speed in a
`
`predetermined clock speed range having a minimum clock speed and a maximum clock
`
`speed. The apparatus comprises an interface channel having a clock channel and a
`
`plurality of bit channels for transmitting bits; a first interface controller coupled to the first
`
`computer interface bus and to the interface channel to encode first control signals from the
`
`first computer interface bus into first control bits to be transmitted on the interface
`
`channel and to decode second control bits received from the interface channel into second
`
`control signals to be transmitted to the first computer interface bus; and a second interface
`
`controller coupled to the interface channel and the second computer interface bus to
`
`decode the first control bits from the interface channel into third control signals to be
`
`transmitted on the second computer interface bus and to encode fourth control signals
`
`from the second computer interface bus into the second control bits to be transmitted on
`
`the interface channel.
`
`[0026] In one embodiment, the first and second interface controllers comprise a host
`
`interface controller (HIC) and a peripheral interface controller (PIC), respectively, the first
`
`and second computer interface buses comprise a primary PCI and a secondary PCI bus,
`
`respectively, and the interface channel comprises an LVDS channel.
`
`[0027] In a preferred embodiment, the interface channel has a plurality of serial bit
`
`channels numbering fewer than the number of parallel bus lines in each of the PCI buses
`
`and operates at a clock speed higher than the clock speed at which any of the bus lines
`
`938747 vl/HN
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`Ex. 1009, Page 199
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`Ex. 1009, Page 199
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`

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`operates. More specifically, the interface channel includes two sets of unidirectional
`
`serial bit channels which transmit data in opposite directions such that one set of bit
`
`channels transmits serial bits from the HIC to the PIC while the other set transmits serial
`
`bits from the PIC to the HIC. For each cycle of the PCI clock, each bit channel of the
`
`interface channel transmits a packet of serial bits.
`
`[0028] The HIC and PIC each include a bus controller to interface with the first and
`
`second computer interface buses, respectively, and to manage transactions that occur
`
`therewith. The HIC and PIC also include a translator coupled to the bus controller to
`
`encode control signals from the first and second computer interface buses, respectively,
`
`into control bits and to decode control bits from the interface channel into control signals.
`
`Additionally, the HIC and PIC each include a transmitter and a receiver coupled to the
`
`translator. The transmitter converts parallel bits into serial bits and transmits the serial
`
`bits to the interface channel. The receiver receives serial bits from the interface channel
`
`and converts them into parallel bits.
`
`[0029] According to the present invention, a technique including a method and device for
`
`securing a computer module using a password in a computer system is provided. In an
`
`exemplary embodiment, the present invention provides a security system for an attached
`
`computer module (“ACM”). In an embodiment, the ACM inserts into a Computer
`
`Module Bay (CMB) within a peripheral console to form a functional computer.
`
`[0030] In a specific embodiment, the present invention provides a computer module. The
`
`computer module has an enclosure that is insertable into a console. The module also has a
`
`central processing unit (i.e., integrated circuit chip) in the enclosure. The module has a
`
`hard disk drive in the enclosure, where the hard disk drive is coupled to the central
`
`processing unit. The module further has a programmable memory device in the enclosure,
`
`where the programmable memory device can be configurable to store a password for
`
`preventing a possibility of unauthorized use of the hard disk drive and/or other module
`
`elements. The stored password can be any suitable key strokes that a user can change
`
`from time to time. In a further embodiment, the present invention provides a permanent
`
`password or user identification code stored in flash memory, which also can be in the
`
`processing unit, or other integrated circuit element. The permanent password or user
`
`identification code is designed to provide a permanent “finger print” on the attached
`
`computer module.
`
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`Ex. 1009, Page 200
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`

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`[0031] In a specific embodiment, the present invention provides a variety of methods. In
`
`one embodiment, the present invention provides a method for operating a computer
`
`system such as a modular computer system and others. The method includes inserting an
`
`attached computer module (“ACM”) into a bay of a modular computer system. The ACM
`
`has a microprocessor unit (e.g.. microcontroller, microprocessor) coupled to a mass
`
`memory storage device (e. g., hard disk). The method also includes applying power to the
`
`computer system and the ACM to execute a security program, which is stored in the mass
`
`memory storage device. The method also includes prompting for a user password from a
`
`user on a display (e.g., fiat panel, CRT). In a further embodiment, the present method
`
`includes a step of reading a permanent password or user identification code stored in flash
`
`memory, or other integrated circuit element. The permanent password or user
`
`identification code provides a permanent finger print on the attached computer module.
`
`The present invention includes a variety of these methods that can be implemented in
`
`computer codes, for example, as well as hardware.
`
`[0032] Numerous benefits are achieved using the present invention over previously
`
`existing techniques. The present invention provides mechanical and electrical security
`
`systems to prevent theft or unauthorized use of the computer system in a specific
`
`embodiment. Additionally, the present invention substantially prevents accidental
`
`removal of the ACM from the console. In some embodiments, the present invention
`
`prevents illegal or unauthorized use during transit. The present invention is also
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`implemented using conventional technologies that can be provided in the present
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`computer system in an easy and efficient manner. Depending upon the embodiment, one
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`or more of these benefits can be available. These and other advantages or benefits are
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`described throughout the present specification and are described more particularly below.
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`[0033] These and other embodiments of the present invention, as well as its advantages
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`and features, are described in more detail in conjunction with the text below and attached
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`Figs.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`[0034] Fig. l is a simplified diagram of a computer system according to an embodiment
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`of the present invention;
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`[0035] Fig. 2 is a simplified block diagram of a computer system according to an
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`alternative embodiment of the present invention;
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`[0036] Fig. 3 is a simplified block diagram of a compeer system according to a further
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`alternative embodiment of the present invention, and
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`[0037] Fig. 4 is a simplified flow diagram of a method according to an embodiment of the
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`present invention.
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`[0038] Fig. 5 is a block diagram of a computer system using a prior art interface between
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`a primary and a secondary PCI bus.
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`[0039] Fig. 6 is a block diagram of one embodiment of a computer system using the
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`interface of the present invention.
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`[0040] Fig. 7 is a partial block diagram of a computer system using the interface of the
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`present invention as a bridge between the north and south bridges of the computer system.
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`[0041] Fig. 8 is a partial block diagram of a computer system in which the north and
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`south bridges are integrated with the host and peripheral interface controllers,
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`respectively.
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`[0042] Fig. 8A shows an attached computer module with Integrated CPU/NB Graphics
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`and Integrated HIC/SB.
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`[0043] Fig. 8B shows an attached computer module with single chip fully integrated:
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`CPU, Cache, Core Logic, Graphics controller and Interface controller.
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`[0044] Fig. 9 is a block diagram of one embodiment of the host interface controller and
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`the peripheral interface controller of the present invention.
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`[0045] Fig. 10 is a detailed block diagram of one embodiment of the host interface
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`controller of the present invention.
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`[0046] Fig. 11 is a detailed block diagram of one embodiment of the PIC of the present
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`invention.
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`[0047] Fig. 12 is a table showing the symbols, signals, data rate and description of signals
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`in a first embodiment of the XPBus.
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`[0048] Fig. 13 is a table showing the information transmitted on the XPBus during two
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`clock cycles of the XPBus in one embodiment of the present invention where 10 data bits
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`transmitted in each clock cycle of the XPBus.
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`[0049] Fig. 14 is a table showing information transmitted on the XPBus during four clock
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`cycles of the XPBus in another embodiment of the present invention where 10 data bits
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`are transmitted in each clock cycle of the XPBus.
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`[0050] Fig. 15 is a schematic diagram of the signal lines PCK, PDO to PD3, and PCN.
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`[0051] Fig. 16 is a table showing the names, types, number of pins dedicated to, and the
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`description of the primary bus PCI signals.
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`[0052] FIG. 17 is a block diagram of one embodiment of a computer system employing
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`the present invention.
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`[0053] FIG. 18 is a block diagram of an attached computing module (ACM).
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`[0054] FIG. 19 illustrates an external view of one embodiment of an ACM.
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`[0055] FIG. 19b illustrates one possible embodiment of a computer bay.
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`[0056] FIG. 20 illustrates the internal component layout for one embodiment of an ACM.
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`[0057] FIG. 21 is a block diagram of a peripheral console (PCON).
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`[0058] FIG. 22 is a simplified layout diagram of a security system for a computer system
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`according to an embodiment of the present invention; and
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`[0059] FIG. 23 is a simplified block diagram of a security system for a computer module
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`according to an embodiment of the present invention.
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`DETAILED DESCRIPTION OF THE INVENTION
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`[0060] According to the present invention, a technique including a method and device for
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`multi-module computing is provided. In an exemplary embodiment, the present invention
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`provides a system including a plurality of computer modules that can independently
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`operate to provide backup capability, dual processing, and the like.
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`[0061] Fig. 1 is a simplified diagram of a computer system 100 according to an
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`embodiment of the present invention. This diagram is merely an illustration and should
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`not limit the scope of the claims herein. One of ordinary skill in the art would recognize
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`other variations, modifications, and alternatives. The computer