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`Intel Corporation v. ACQIS LLC
`Intel Corp.'s Exhibit 1017
`Ex. 1017, Page 1
`
`

`

`
`
`US 7,676,624 B2
`
`
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`
`
`
`
`
`4,623,964 A
`
`4,700,362 A
`
`4,769,764 A
`
`4,872,091 A
`
`4.890282 A
`
`4918572 A
`
`4939.735 A
`
`5056.141 A
`
`5,086,499 A
`
`5,251,097 A
`
`5,278,509 A
`
`5278.730 A
`
`5193497 A
`
`
`
`
`
`11/1986 Getz et a1.
`
`
`
`10/1987 Todd et al~
`
`
`
`9/1988 Levanon
`
`
`10/1989 Maniwa 6t al~
`
`
`12/1989 Lambert et a1~
`
`
`
`4/ 1990 Tawer 6t al~
`
`
`
`7/ 1990 Fredericks et al~
`
`
`10/ 1991 Dyke
`
`
`2/1992 Mutone
`
`
`
`10/1993 Simmons et al.
`
`
`
`1/ 1994 Haynes et al~
`
`
`1/ 1994 Kikinis
`
`
`“994 Free
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`5,317,477 A
`5/1994 Glue“
`
`
`
`
`5’319’771 A
`6/1994 Takéd?
`5,331,509 A
`7/1994 K1k1n1s.
`
`
`
`
`5,355,391 A
`10/1994 Horow1tz et a1.
`
`
`
`
`
`
`
`
`5,428,806 A
`6/1995 Pocrass
`
`
`
`
`5,436,857 A
`7/1995 Nelson et al.
`
`
`
`
`5,463,742 A
`10/1995 Kobayashi
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`
`
`
`5,539,616 A
`7/1996 Kikinis
`
`
`
`
`5,550,710 A
`8/1996 Rahamim et al.
`
`
`
`
`
`5,550,861 A
`8/1996 Chan et al.
`
`
`
`
`5,578,940 A
`11/1996 Dillon
`5,600,800 A
`2/1997 Kikinis et al.
`
`
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`
`
`
`5,603,044 A
`2/1997 Annapareddy et al.
`5,606,717 A
`2/1997 Farmwald et al.
`
`
`
`
`
`
`
`
`
`5,608,608 A
`3/1997 Flint et 31
`
`
`
`
`5,630,057 A
`5/1997 Hait
`
`
`
`
`
`5,638,521 A
`6/1997 Buchala et al.
`
`
`
`
`5,640,302 A
`6/1997 Kikinis ....................... 361/687
`
`
`
`
`
`5,659,773 A
`8/1997 Huynh et a1.
`
`
`
`
`5563561 A
`9/1997 D1110.“ 3531'
`
`
`
`
`5’67“” A
`9/1997 H3911?“
`5,680,126 A
`10/1997 K1k1n1s
`
`
`
`
`
`
`
`5,689,654 A
`11/1997 Kikinis
`
`
`
`
`5,721,837 A
`2/1998 Kikinis
`
`
`
`5,721,842 A
`2/1998 Beasley et al.
`
`
`
`5,745,733 A
`4/1998 Robinson
`
`
`
`5,752,080 A
`5/1998 Ryan
`
`
`
`5,764,924 A
`6/1998 Hong
`5,774,704 A
`6/ 1998 Williams
`
`
`
`
`5,795,228 A
`8/1998 Trumbull
`
`
`
`
`
`
`
`
`5,809,538 A
`9/ 1998 Pollmann
`
`
`
`
`5,815,681 A
`9/1998 Kikinis
`
`
`
`
`5,819,050 A
`10/1998 Boehling et 31,
`
`
`
`
`5,826,048 A
`10/1998 Dempsey et al.
`
`
`
`5,848,249 A
`12/1998 Garbus
`
`
`
`5,859,669 A
`1/1999 Prentice
`5,907,566 A
`5/1999 Benson et al.
`
`
`
`
`5,941,965 A
`8/ 1999 Moroz et al.
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`
`
`
`
`
`
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`
`5,948,047 A
`9/1999 Jenkins et a1.
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`5,960,213 A
`9/1999 Wilson
`5,968,144 A
`10/1999 Walker et al.
`
`
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`
`
`5,971,804 A
`10/1999 Gallagher et a1.
`
`
`
`
`5,977,989 A
`11/1999 Lee et a1.
`
`
`
`
`
`5,978,919 A
`11/1999 Doi et al.
`
`
`
`
`5,982,363 A
`11/1999 Naiff
`
`
`
`5,991,163 A
`11/1999 Marconi et al.
`
`
`
`5,991,844 A
`11/1999 KhOSIOWPOUI
`
`
`
`
`5,999,952 A
`12/1999 Jenkins et a1.
`
`
`
`
`6,002,442 A
`12/1999 Li et 31~
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`
`
`2883:2555; :
`12/1333 :ica-rd et al.
`av1purapu
`,
`,
`
`
`
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`
`6,011,546 A
`“2000 Bertram
`
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`
`6,016,252 A
`“2000 Pignolet et 31~
`
`
`
`
`6,028,643 A
`2/2000 Jordan et al.
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`
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`
`
`6,029,183 A
`2/2000 Jenkins 6t 31.
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`3/2000 Gale et al.
`6,040,792 A
`3/2000 Watson et a1.
`
`
`
`
`
`
`
`
`
`
`
`
`...................... 726/36
`
`
`
`
`
`
`
`
`
`
`6,052,513 A
`
`6,069,615 A
`
`
`6,070,214 A
`
`6,088,224 A
`
`6,088,752 A
`
`6,157,534 A
`
`6,163,464 A
`
`
`6,175,490 B1
`
`
`6,202,169 B1
`
`6,208,522 B1
`
`
`6,216,185 B1
`
`
`6,260,155 B1
`
`
`6,289,376 B1
`
`
`6,304,895 B1
`
`
`6,311,268 B1
`
`
`
`6,317,329 B1
`
`
`6,321,335 B1
`6,332,180 B1
`
`
`
`
`6’345’330 B2
`
`
`6366951 Bl
`
`
`6,378,009 B1
`
`
`6,381,602 B1
`
`
`6,393,561 B1
`
`
`6,401,124 B1
`
`
`6,425,033 B1
`6,452,789 B1
`
`
`
`
`6,452,790 B1
`6,453,344 B1
`
`
`
`
`6,496,361 B2
`
`
`6,549,966 B1
`
`
`6,564,274 B1
`
`
`6,643,777 B1
`
`
`6,718,415 B1
`
`
`6,725,317 B1
`
`
`7,099,981 B2
`
`
`7’146’446 B2
`
`7328397 B2 *
`
`
`7,363,415 B2
`
`
`7363416 32
`
`
`7,376,779 B2
`
`
`
`
`
`
`
`4/2000 MacLaren
`
`
`5/2000 Abraham et al.
`
`
`
`
`
`
`5/2000 Ahern
`
`
`7/2000 Gallagher et a1.
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`
`12/2000 Gallagher et a1.
`
`
`
`12/2000 Ishibashi et al.
`
`
`
`1/2001 Papa et al.
`
`
`3/2001 Razzaghe-Ashrafi et al.
`
`
`
`3/2001 Manweiler et al.
`
`
`4/2001 Chu
`
`
`7/2001 Dellacona
`
`
`
`9/2001 Taylor et al.
`
`
`10/2001 Schneider et al.
`
`
`10/2001 Chu
`
`
`
`
`
`
`
`
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`
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`
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`
`
`
`11/2001 Dowdy et al.
`
`
`
`11/2001 Chu
`12/2001 Kauffman et al.
`
`
`
`
`
`2/2002 Chu .
`
`
`“002 S?hmldt
`
`
`
`4/2002 PlIlkStOIl, H et 31.
`
`
`4/2002 ShOI‘Offet 3.1.
`
`
`5/2002 Hagiwara et a1.
`
`
`6/2002 Yang et al.
`
`
`7/2002 Conway et a1.
`9/2002 Pallotti et al.
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`
`
`
`
`
`
`
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`9/2002 Ellsworth
`
`
`
`
`
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`
`
`4/2003 Dickens et a1.
`
`
`
`5/2003 Heath et al.
`
`
`1 “2003 Chu
`
`
`4/2004 Chu
`
`
`4/2004 Bouchier et al.
`
`
`8/2006 Chu
`
`
`12/2006 Chu
`
`
`”008 Chu
`
`
`
`4/2008 Chu ........................... 710/313
`
`
`“008 Chu
`
`
`
`5/2008 Chu
`
`
`
`OTHER PUBLICATIONS
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`
`
`
`
`
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`
`
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`
`
`Ex. 1017, Page 2
`
`Ex. 1017, Page 2
`
`

`

`
`
`US 7,676,624 B2
`Page 3
`
`
`
`
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`
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`
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`
`
`
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`and Repair,
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`htm>>, downloaded from web on Jun. 22, 2004, 3 pgs.
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`Cubix, “Powering On/Off or Resetting Plug-in Computers in an
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`
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`
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`sity Systems”, (@2000) <<http://64.173.211.7/support/techinfo/sys-
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`IT Group Network Engines”,
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`
`<<http://egi.ebay.com/we/eBayISAPIdll?ViewItem
`&item:5706388046
`
`
`
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`Internet Telephone Roundup, “Industrial Computers”, http://www.
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`
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`Press Release: Hiawatha, Iowa, (Mar.
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`Group Products Offer Industrial PCs with Built-in Flexibility”,
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`Press Release: Kanata, Ontario, Canada,
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`“Enhanced COTS SBC from DY 4 Systems features 166MHz
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`
`
`
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`internet @ http://www.mplch/DOCS/
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`nw-con-0818rev.html.
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`
`
`
`
`
`Eversys Corporation, “Eversys System 8000 Consolidated Network
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`
`Server Market and Product Overview,” Slide presentation, down-
`
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`
`
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`pages.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
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`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`* cited by examiner
`
`
`
`Ex. 1017, Page 3
`
`Ex. 1017, Page 3
`
`

`

`U.S. Patent
`
`uM
`
`4
`
`676,
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`2B4
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`"MW.”fl‘u:325.91-620FOP.\23:00
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`
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`
`cmaozabmofiox8w
`
`Ex. 1017, Page 4
`
`Ex. 1017, Page 4
`
`
`

`

`
`US. Patent
`
`
`
`
`Mar. 9, 2010
`
`
`
`
`Sheet 2 of 24
`
`
`
`US 7,676,624 B2
`
`
`
`
`
`
`1” ACM Subsystem (Primary)
`
`
`
`
`
`Shared Peripheral System
`
`
`
`201
`
`
`
`
`
`
`FIGURE 2
`
`Ex. 1017, Page 5
`
`Ex. 1017, Page 5
`
`

`

`
`US. Patent
`
`
`
`
`Mar. 9, 2010
`
`
`
`
`Sheet 3 of 24
`
`
`
`US 7,676,624 B2
`
`
`
`
`18‘ ACM Subsystem (Pflmary)
`
`
`
`
`
`Shared Padpheml System
`
`
`
`
`/ 300
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`
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`215
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`
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`
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`
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`
`m
`
`
`
`
`
`
`Ex. 1017, Page 6
`
`Ex. 1017, Page 6
`
`

`

`
`US. Patent
`
`
`
`
`Mar. 9, 2010
`
`
`
`
`Sheet 4 of 24
`
`
`
`US 7,676,624 B2
`
`Us
`I
`3.5
`
`
`er se ac
`
`
`
`
`
`certain file for auto
`
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`
`
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`
`
`
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`
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`
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`
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`
`
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`
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`
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`
`
`
`
`433
`
`
`
`427
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`
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`
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`
`
`403
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`
`
`405
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`
`
`407
`
`
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`409
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`
`
`
`421
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`Yes
`
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`
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`
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`
`
`
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`
`
`
`
`417
`
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`
`FIGURE 4
`
`419
`
`
`
`Ex. 1017, Page 7
`
`Ex. 1017, Page 7
`
`

`

`
`US. Patent
`
`
`
`
`Mar. 9, 2010
`
`
`
`
`Sheet 5 of 24
`
`
`
`US 7,676,624 B2
`
`
`Notebook PC
`
`
`
`Flat
`
`
`
` Graphics
`Panel
`
`
`
`
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`Display
`
`
`
`
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`
`
`
`
`
`
`
`
`
`500
`
`
`
`
`
`
`
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`0.nnectors
`
`
`
`
`
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`
`
`
`
`
`
`
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`
`
`
`
`PCI Bus
`
`
`
`
`PCI Add-
`
`
`
`
`on Board2
`
`PRIOR ART
`
`
`
`
`FIGURE 5
`
`550
`
`
`
`Ex. 1017, Page 8
`
`Ex. 1017, Page 8
`
`

`

`
`U.S. Patent
`
`
`
`r.aM
`
`
`29,
`
`
`
`S
`
`
`42
`
`
`76,7SU
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`
`
`
`
`
`2020035:3th
`
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`
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`
`
`
`
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`
`33:2th.3:
`
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`m9
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`
`Ex. 1017, Page 9
`
`Ex. 1017, Page 9
`
`

`

`
`US. Patent
`
`
`
`
`Mar. 9, 2010
`
`
`
`
`Sheet 7 of 24
`
`
`
`US 7,676,624 B2
`
`
`Computing System
`
`
`
`
`
`
`CPU/NB
`
`signals
`
`
`
`
`PC! Bus Bridge
`
`
`K with
`
`
`Interface Dev.
`
`
`
`Pair And PBus
`
`
`
`
`
`
`
`North Bride 3 Primer
`
`I
`
`
`Host
`
`Interface
`Controller
`
`
`
`
`Peripheral System
`
`
`
`
`
`Sth CPU/NB
`
`
`signals :
`Bridge
`
`Peripheral
`
`Interface
`Controller
`
`
`
`
`
`
`Secondar PCI Bus
`
`
`PCI
`
`Device1
`
`
`
`PCI Add-
`
`
`on Board 2
`
`
`FIGURE 7
`
`Ex. 1017, Page 10
`
`Ex. 1017, Page 10
`
`

`

`
`US. Patent
`
`
`
`
`Mar. 9, 2010
`
`
`
`
`Sheet 8 of 24
`
`
`
`US 7,676,624 B2
`
`
`Computing System
`
`
`
`
`
`
`
`Integrated
`
`Host
`Interface
`
`
`
`
`
`'
`
`.
`
`
`SUbSYStem
`
`
`
`
`North Bridge
`
`
`
`PCIBus' —————
`
`
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`
`
`
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`
`
`
`
`
`
`
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`
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`
`Interface
`
`Cntir. &
`
`8. Bridge
`
`
`
`
`805
`
`
`
`810
`
`
`
`
`FIGURE 8
`
`Ex. 1017, Page 11
`
`Ex. 1017, Page 11
`
`

`

`
`US. Patent
`
`
`
`
`Mar. 9, 2010
`
`
`
`
`Sheet 9 of 24
`
`
`
`US 7,676,624 B2
`
`930
`
`
`Primary PCI Bus
`
`
`
`
`
`PCl Clock
`
`Host
`
`
`lnterface
`
`
`
`
`
`
`As nchronous
`y
`
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`
`
`
`
`
`
`
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`
`505
`
`
`
`
`
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`
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`
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`
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`
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`
`~~~~~
`
`
`
`PD[3::0], PCN l
`
`
`
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`
`
`
`
`
`Asynchronous
`
`
`
`Secondary
`
`
`
`980
`
`
`
`
`FIGURE 9
`
`
`Peripheral
`
`interface
`Controller
`
`955
`
`
`
`
`
`Ex. 1017, Page 12
`
`Ex. 1017, Page 12
`
`

`

`
`US. Patent
`
`
`
`
`Mar. 9, 2010
`
`
`
`
`Sheet 10 of 24
`
`
`
`US 7,676,624 B2
`
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`
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`
`1090
`
`
`
`
`
`
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`\"meo Pon Control
`
`
`
`
`
`
`
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`mm”
`
`
`
`Gtaphics
`
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`
`
`
`
`________________________
`
`1081
`
`
`
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`....'
`
`
`
`
`
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`
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`
`
`
`
`
`
`FIGURE 10
`
`Ex. 1017, Page 13
`
`Ex. 1017, Page 13
`
`

`

`
`US. Patent
`
`
`
`
`Mar. 9, 2010
`
`
`
`
`Sheet 11 of 24
`
`
`
`US 7,676,624 B2
`
`Hash Memory
`
`(Oplional)
`
`
`
`
`1160
`
`
`
`-I
`
`
`
`
`
`PCI CLK
`
`
`
`
`
`
`
`
`
`Parallel to Serial
`Convener
`
`
`
`
`
`
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`
`PCtcnn “ 51v
`
`
`
`
`
`Reset Cntl
`
`
`
`
`
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`Serial to Paraiéel
`
`
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`
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`MASTER
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`
`. ‘
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`
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`
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`
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`
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`
`
`CPU CNTL
`
`5 GPIO
`
`
`Leach/Drive:
`
`
`RESET”
`
`
`
`Video
`Video Fun Daze [02:15}
`Parallel
`
`
`
`
`
`to Sella!
`
`Captule
`
`
`
`Circuit
`
`
`Video Pod Control
`
`
`
`
`Video
`
`Clock
`
`
`
`
`
`
`
`
`
`
`
`FIGURE 11
`
`Ex. 1017, Page 14
`
`Ex. 1017, Page 14
`
`

`

`
`US. Patent
`
`
`
`
`Mar. 9, 2010
`
`
`
`
`Sheet 12 of 24
`
`
`
`US 7,676,624 B2
`
`
`
`
`
`
`
`
`
`
`
`
`
`
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`Description
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`Ex. 1017, Page 15
`
`Ex. 1017, Page 15
`
`

`

`
`U.S. Patent
`
`
`
`
`Diar.9,2010
`
`
`
`
`Sheet130f24
`
`
`
`US 7,676,624 B2
`
`
`
`2mmsgi
`
`Ex.1017,Page16
`
`Ex. 1017, Page 16
`
`

`

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`U.S. Patent
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`Ex. 1017, Page 17
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`Ex. 1017, Page 17
`
`

`

`
`US. Patent
`
`
`
`
`Mar. 9, 2010
`
`
`
`
`Sheet 15 of 24
`
`
`
`US 7,676,624 B2
`
`PCK
`
`
`
`
`
`PDO
`
`
`
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`
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`
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`[303
`
`
`FIGURE 15
`
`Ex. 1017, Page 18
`
`Ex. 1017, Page 18
`
`

`

`
`US. Patent
`
`
`
`
`Mar. 9, 2010
`
`
`
`
`Sheet 16 of 24
`
`
`
`US 7,676,624 B2
`
`Name
`
`
`
`
`T8
`“31313301
`C/BEBI-‘OW T8
`
`F RAME#
`
`
`
`
`mow;
`
`TRDY#
`
`
`
`
`DEVSEL#
`
`
`STOP#
`
`PAR
`
`
`
`LOCK#
`
`
`
`
`1133ng
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`
`SERR#
`
`
`
`
`REQ#
`
`
`GNT#
`
`CLKRUN#
`
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`PCICK
`
`
`
`
`315 1
`
`
`515 1
`
`
`315 1
`
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`STS 1
`
`
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`
`T5
`
`
`
`
`
`1
`
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`1
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`
`
`1
`
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`
`OD
`
`
`1
`
`
`1
`
`T3
`
`
`Input 1
`
`l/OD 1
`
`
`
`Input 1
`
`
`
`
`Type Pins Description
`
`
`
`
`
`
`
`
`
`32 Multiplexed Address/Data. AD is driven to a valid state when GNT# is asserted.
`
`
`
`
`
`
`
`. Multiplexed Commandr‘Byte Enables. For a two-address transaction, ist
`4
`
`
`
`
`
`
`
`
`
`
`
`
`address phase carries the command, and the 2nd address phase carries the
`
`
`
`
`
`
`
`
`
`transaction type. C/BE is driven to a valid state when GNTtt is asserted.
`
`
`
`
`
`
`
`
`indicates beginning and duration of a PCI transaction. When the bus is idle,
`
`
`
`
`
`
`
`
`
`
`FRAME? is driven to High for 1 cycle. A pull-up resistor sustains STS signal.
`
`
`
`
`
`
`
`
`
`
`initiator Ready. |RDY# is driven High for 1 cycle it bus is idle, and the state is
`
`
`
`sustained by a pull-up resistor.
`
`
`
`
`
`
`
`
`
`Target Ready. When bus is idle, TRDY# is driven High for 1 cycle it bus is idle.
`
`
`
`
`
`
`
`An external pull—up resistor sustains STS signal.
`
`
`
`
`
`
`
`
`Device Select. DEVSEL# is asserted by target to indicate it is ready to accept
`the transaction. HlC decodes address of a transaction to decide the need to
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`assert DEVSEL#. As an initiator, HlC waits for 5 cycles to detect assertion of
`
`
`
`
`
`
`
`
`DEVSEUt by the target; otherwise HlC terminates with a master abort.
`
`
`
`
`
`
`
`
`
`
`DEVSELtt is driven High for 1 cycle when bus is idle, and the state is sustained
`
`
`
`by a pullsup resistor.
`
`
`
`
`
`
`
`Target request to stop transaction. There are 3 cases:
`
`
`
`
`
`
`
`STOP#, TRDY# & DEVSEL# asserted: disconnect with data transfer
`
`
`
`
`
`
`
`
`Only STOP# 8. DEVSEL# asserted: request initiator to retry tater
`
`
`
`
`
`Only STOP# asserted: target abort
`
`
`
`
`
`
`
`
`
`
`
`STOP# is driven High for 1 cycle when bus is idle. and the state is sustained by
`
`
`
`a pull-up resistor.
`
`
`
`
`
`
`
`
`
`
`
`Even parity for 36 bits of AD 8. C/BE#. PAR is sent one cycle after address or
`
`
`
`
`
`
`
`
`
`
`
`
`
`data is valid.
`In write transaction, initiator sends PAR one cycle after write data
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`is valid.
`in read transaction. target sends PAR one cycle after read data is valid.
`
`
`
`
`
`
`
`
`
`initiator request lock on target downstream. LOCK# is asserted t clock cycle
`
`
`
`
`
`
`
`
`
`after address phase by an initiator wanting to pertorm an atomic operation that
`
`
`
`
`
`
`
`
`
`
`
`
`take more than one transaction i0 cornpieie. HlC passes the LCCK# request to
`
`
`
`
`
`
`
`
`
`
`
`the secondary PCl'bus. HlC does not drive LOCKitt or propagate LOCK#
`
`upstream.
`
`
`
`
`
`
`
`
`
`Chip Select for Type 0 configuration access. During a Type 0 configuration
`
`
`
`
`
`
`
`
`
`
`transaction, the initiator asserts lDSEL# during the address phase to select HlC.
`
`
`
`
`HlC responds by asserting DEVSELfi.
`
`
`
`
`
`
`
`
`
`Data Parity Error on all transactions except Special Cycle. PERR# is driven one
`
`
`
`
`
`
`
`
`
`
`clock cycle after PAR. PE RR# is asserted by target during write transactions,
`
`
`
`
`
`and by initiator during read transactions.
`
`
`
`
`
`
`
`
`
`System Error. HlC asserts SERR# under the following conditions:
`Address parity error, Secondary bus SERRtt asserted.
`
`
`
`
`
`
`
`Posted write transaction: data parity error on target bus. Posted write transaction discarded.
`
`
`
`
`
`
`
`
`
`
`
`Master abort. Target abort
`
`
`
`
`Delayed read or write transaction discarded. and
`
`
`
`
`
`Delayed transaction master timeout.
`
`
`
`
`
`
`
`
`
`
`
`Request for bus.
`If a target retry or disconnect is received in response to
`
`
`
`
`
`
`
`
`initiating a transaction. HlC deasserts REQ# for at least 2 cycles before
`
`
`asserting tt again.
`
`
`
`
`
`
`
`
`
`
`Bus is granted to HlC. HlC can initiate transaction it GNT# is asserted and the
`
`
`
`
`
`
`
`
`
`
`
`
`bus is idle. When HlC is not requesting bus and GNT# is asserted, HlC must
`
`
`
`
`
`
`
`
`drive AD. CIBE. and PAR to valid logic levels.
`
`
`
`
`
`
`
`
`
`
`
`Input indicating clock status. HlC can request the central clock resource to start.
`
`
`
`
`
`
`
`
`speed up or maintain the PCl clock. There are 3 clocking states:
`
`
`
`
`
`
`
`
`
`Clock running, Clock about to stop/slow down, and Clock stopped/slowed.
`
`
`
`
`
`
`
`
`
`
`PCI Clock. All inputs are sampled on the rising edge of PClCK. Frequency
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIGURE 16-
`
`Ex. 1017, Page 19
`
`Ex. 1017, Page 19
`
`

`

`U.S. Patent
`
`Diar.9,2010
`
`Sheet17of24
`
`US 7,676,624 B2
`
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`Ex.1017,Page20
`
`Ex. 1017, Page 20
`
`

`

`
`U.S. Patent
`
`
`
`
`Diar.9,2010
`
`
`
`
`Sheet180f24
`
`
`
`US 7,676,624 B2
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`Ex. 1017, Page 21
`
`Ex. 1017, Page 21
`
`
`

`

`
`US. Patent
`
`
`
`
`Mar. 9, 2010
`
`
`
`
`Sheet 19 of 24
`
`
`
`US 7,676,624 B2
`
`
`
`1930b
`
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`FIGURE 19
`
`Ex.1017,Page22
`
`Ex. 1017, Page 22
`
`

`

`
`US. Patent
`
`
`
`
`Mar. 9, 2010
`
`
`
`
`Sheet 20 of 24
`
`
`
`US 7,676,624 B2
`
`
`
`
`
`
`FIGURE 198
`
`
`
`Ex. 1017, Page 23
`
`Ex. 1017, Page 23
`
`

`

`
`U.S. Patent
`
`
`
`
`67697S
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`Ex. 1017, Page 24
`
`Ex. 1017, Page 24
`
`

`

`
`U.S. Patent
`
`
`
`
`Mar. 9, 2010
`
`
`
`
`Sheet 22 0f 24
`
`
`
`US 7,676,624 B2
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`
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`Ex. 1017, Page 25
`
`
`

`

`
`US. Patent
`
`
`
`
`Mar. 9, 2010
`
`
`
`
`Sheet 23 of 24
`
`
`
`US 7,676,624 B2
`
`
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`cpu MODULE
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`DEPTH:
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`234mm
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`(9213')
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`POWER
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`FIGURE 22
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`Ex. 1017, Page 26
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`Ex. 1017, Page 26
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`

`

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`U.S. Patent
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`7,
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`Ex. 1017, Page 27
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`Ex. 1017, Page 27
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`

`

`
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`US 7,676,624 B2
`
`
`1
`MULTIPLE MODULE COMPUTER SYSTEM
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`AND METHOD INCLUDING DIFFERENTIAL
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`SIGNAL CHANNEL COMPRISING
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`UNDIRECTIONAL SERIAL BIT CHANNELS
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`CROSS REFERENCE TO RELATED
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`APPLICATIONS
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`The present application claims priority as a continuation of
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