Intel Corporation v. ACQIS LLC
`Intel Corp.'s Exhibit 1020
`Ex. 1020, Page 1
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` Hillllllllllllillllllll
`88991.
`9017890'
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`gFEE TRANSMITTAL
`
`For FY 2005
`-
`.
`.
`X Applicant claims small entity status. See 37 CFR 1.27
`4
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`Effective on 12/08/2004.
`5:
`ayes pursuant to the Consolidated Appropriations Act, 2005 (HR. 4818).
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`PTO/SB/17 (12-04)
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`Com . late if Known
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`First Named Inventor Chu, William W. Y.
`Examiner Name
`To Be Assigned
`
`Art Unit
`
`
`Attorney Docket No.
`
`To Be Assigned
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`o19152-oo1114us
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`(5) 4050
`METHOD OF PAYMENT check all that a |
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`’
`E] Check El Credit Card [3 Money Order I: None D Other (please identify):
`E DEPOSit Account Deposit Account Number: 20-1430
`Deposit Account Name: Townsend and Townsend and Crew LLP
`For the above-identified deposit account. the Director is hereby authorized to: (check all that apply)
`X Charge fee(s) indicated below
`D Charge fee(s) indicated below. except for the filing fee
`Charge any additional fee(s) or underpayments of fee(s) v
`.
`under 37 CFR 1.16 and 1.17
`Credit any overpayments
`WARNING: Information on this form may become public. Credit card information should not be Included on this form. Provide credit card
`Information and authorization on PTO-203i!
`
`FEE CALCULATION
`
`1. BASIC FILING, SEARCH, AND EXAMINATION FEES
`FILING FEES
`SEARCH FEES
`Small Entig
`Small Entity
`Fee (fl Fee 1;)
`Fee (fl Fee (fl
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`Application Type
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`EXAMINATION FEES
`Small Entig
`Fee (fl Fee (fl
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`Utility
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`Design
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`Plant _
`Reissue
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`300
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`200
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`200
`300
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`ISO
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`100
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`100
`150
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`500
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`100
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`300
`500
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`250
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`50
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`150
`250
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`200
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`130
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`160
`600
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`100
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`65
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`80.
`300
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`Fees‘Paid (fl
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`500
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`200
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`100
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`0.
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`0
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`‘
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`0
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`0 __
`'
`Provisional
`Small Entity
`2. EXCESS CLAIM FEES
`Fee (fl Fee [fl
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`Fee Description '
`50
`25
`Each claim over 20 or, for Reissues, each claim over 20 and more than in the original patent
`Each independent claim over 3 or, for Reissues, each independent claim more than in the original patent 200
`100
`Multiple dependent claims
`360
`180
`Fee (fl
`Total Claims
`Extra Claims
`$25
`x
`.20 or HP =
`94
`74
`HP = highest number of total claims paid for, if greater than 20
`M M £91m M5.)
`20
`-3 or HP =
`17
`x
`$100
`=
`$1,700
`HP = highest number of independent claims paid for, if greater than 3
`3. APPLICATION SIZE FEE
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`Fee Paid (fl
`$1,850
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`=
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`Multiple Dependent Claims
`M my
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`-
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`If the specification and drawings exceed 100 sheets of paper, the application size fee due is $250 ($125 for small entity)
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`for each additional 50 sheets or fraction thereof. See 35 U.S.C. 41(a)(1)(G) and 37 CFR 1.16(s).
`Total Sheets
`Extra Sheets
`Number of each additional 50 or fraction thereof
`Fee (fi)
`Fee Paid (fl
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`
`
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`= - 100 = ‘ / 50 = (round up to a whole number) x
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`4. OTHER FEE(S)
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`Fees Paid l§l
` Non-English Specification,
`$130 fee (no small entity discount)
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` Other:
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`DateName (Printfl'ype) KentJ. Tobin June 24, 2005
`60522487 v1
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`r
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`Registration No.
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`
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`Ex. 1020, Page 2
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`Ex. 1020, Page 2
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`062405
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`m“.‘x
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`“A“...
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`‘;_,._
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`8899I
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`29017890
`
`UTILITY
`
`PATENT APPLICATION
`
`Attorney Docket No.
`
`First Inventor
`
`TRANSMITTAL
`
`.
`
`Title
`
`PTO/SB/05 (05-05)
`
`019152-001114US
`
`Chu. William W. Y.
`MULTIPLE MODULE COMPUTER
`SYSTEM AND METHOD
`
`(Only for new nonpmvisional applications under 37 CFR 1.53(b))
`
`Express Mail Label No.
`
`EV 656 873 915 US
`
`APPLICATION ELEMENTS
`See MPEP chapter 600 concerning utility patent application contents.
`
`ADDRESS TO:
`
`Commissioner for Patents
`PO. Box 1450
`Alexandria, VA 22313-1450
`
`‘
`
`(0
`0.
`.LO
`(OK.
`(D
`(O,—
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`ACCOMPANYING APPLICATION PARTS
`
`June 24, 2005
`
`1. IXI Fee Transmittal Form (e.g., PTO/SB/17)
`(Submit an original and a duplicate for fee processing)
`2. X Applicant claims small entity status.
`See 37 CFR 1.27.
`
`1
`49
`[Total Pages
`3% Specification
`Both the claims and abstract must start on a new page
`(For information on the preferred arrangement, see MPEP 608,01(a))
`4.8 Drawing(s) (35 U.S.C.113)
`[Total Sheets
`22
`5. Oath or Declaration
`[Total Sheets
`a. E] Newly executed (original or copy)
`b. E A copy from a prior application (37 CFR 1.63 (d))
`(for a continuation/divisional with Box 18 completed)
`i. C] DELETION OF |NVENTOR(S)
`Signed statement attached deleting inventor(s)
`named in the prior application. see 37 CFR
`1.63(d)(2) and 1.33(b).
`
`2
`
`]
`
`6. [2 Application Data Sheet. See 37 CFR 1.76
`
`7. E] CD-ROM or CD-R in duplicate, large table or
`Computer Program (Appendix)
`Landscape Table on CD
`
`8. Nucleotide and/or Amino Acid Sequence Submission
`(if applicable, items a. - c. are required)
`a. Computer Readable Form (CRF)
`i. C] Computer Readable Form (CRF)
`ii. [:1 Transfer Request (37 CFR 1.821(e))
`b. Specification Sequence Listing on:
`i. E] CD-ROM or CD-R (2 copies); or
`ii. E] Paper
`
`0. I: Statements verifying identity of above copies
`
`9. E] Assignment Papers (cover sheet & document(s))
`
`cu '—
`w ‘-
`
`Name of Assignee
`
`]
`
`10. E] 37 CFR 3.730;) Statement
`(when there is an assignee)
`
`[I Power of
`Attorney
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`11. CI English Translation Document (if applicable)
`
`12. X Information Disclosure Statement (PTO/SB/08 or PTO-1449)
`g Copies of foreign patent documents,
`publications. & other information
`
`13. IX Preliminary Amendment
`
`14. E Return Receipt Postcard (MPEP 503)
`(Should be specifically itemized)
`
`15. [3 Certified Copy of Priority Document(s)
`(if foreign priority is claimed)
`
`16. [I Nonpublication Request under 35 U.S.C. 122 (b)(2)(B)(i).
`Applicant must attach form PTO/SB/35 or its equivalent.
`
`17_ X Other: Title Page, Marked-Up Version of Specification;
`.
`Appendix to Preliminary Amendment containing -
`New Sheets Figs. 5-21
`
`18. If a CONTINUING APPLICATION, check appropriate box, and supply the requisite information below and in the first sentence of the
`specification following the title, or in an Application Data Sheet under 37 CFR 1. 76:
`E Continuation
`I: Divisional
`
`[I Continuation-impart (CIP)
`Examiner To Be Assigned
`
`of prior application No: 11I097 694
`Art Unit: To Be Assi ned
`
`Prior application information:
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`[Z The address associated with Customer Number:
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`OR E] Correspondence address below
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`19. CORRESPONDENCE ADDRESS
`
`'
`
`m:
`
`m
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`-“
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`Name
`Print/T e
`60522492 v1
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`.
`Kennenn
`
`Registration No.
`
`39496
`
`Ex. 1020, Page 3
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`Ex. 1020, Page 3
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`

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` Hillllllllllllillllllll
`88991.
`9017890'
`
`gFEE TRANSMITTAL
`
`For FY 2005
`-
`.
`.
`X Applicant claims small entity status. See 37 CFR 1.27
`4
`
`Effective on 12/08/2004.
`5:
`ayes pursuant to the Consolidated Appropriations Act, 2005 (HR. 4818).
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`PTO/SB/17 (12-04)
`
`Com . late if Known
`
`First Named Inventor Chu, William W. Y.
`Examiner Name
`To Be Assigned
`
`Art Unit
`
`
`Attorney Docket No.
`
`To Be Assigned
`
`o19152-oo1114us
`
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`
`(5) 4050
`METHOD OF PAYMENT check all that a |
`
`
`
`
`
`’
`E] Check El Credit Card [3 Money Order I: None D Other (please identify):
`E DEPOSit Account Deposit Account Number: 20-1430
`Deposit Account Name: Townsend and Townsend and Crew LLP
`For the above-identified deposit account. the Director is hereby authorized to: (check all that apply)
`X Charge fee(s) indicated below
`D Charge fee(s) indicated below. except for the filing fee
`Charge any additional fee(s) or underpayments of fee(s) v
`.
`under 37 CFR 1.16 and 1.17
`Credit any overpayments
`WARNING: Information on this form may become public. Credit card information should not be Included on this form. Provide credit card
`Information and authorization on PTO-203i!
`
`FEE CALCULATION
`
`1. BASIC FILING, SEARCH, AND EXAMINATION FEES
`FILING FEES
`SEARCH FEES
`Small Entig
`Small Entity
`Fee (fl Fee 1;)
`Fee (fl Fee (fl
`
`Application Type
`
`EXAMINATION FEES
`Small Entig
`Fee (fl Fee (fl
`
`Utility
`
`Design
`
`Plant _
`Reissue
`
`300
`
`200
`
`200
`300
`
`ISO
`
`100
`
`100
`150
`
`500
`
`100
`
`300
`500
`
`‘
`
`250
`
`50
`
`150
`250
`
`200
`
`130
`
`160
`600
`
`100
`
`65
`
`80.
`300
`
`Fees‘Paid (fl
`
`500
`
`200
`
`100
`
`0.
`
`0
`
`‘
`
`0
`
`0 __
`'
`Provisional
`Small Entity
`2. EXCESS CLAIM FEES
`Fee (fl Fee [fl
`_
`Fee Description '
`50
`25
`Each claim over 20 or, for Reissues, each claim over 20 and more than in the original patent
`Each independent claim over 3 or, for Reissues, each independent claim more than in the original patent 200
`100
`Multiple dependent claims
`360
`180
`Fee (fl
`Total Claims
`Extra Claims
`$25
`x
`.20 or HP =
`94
`74
`HP = highest number of total claims paid for, if greater than 20
`M M £91m M5.)
`20
`-3 or HP =
`17
`x
`$100
`=
`$1,700
`HP = highest number of independent claims paid for, if greater than 3
`3. APPLICATION SIZE FEE
`
`Fee Paid (fl
`$1,850
`
`=
`
`Multiple Dependent Claims
`M my
`
`-
`
`If the specification and drawings exceed 100 sheets of paper, the application size fee due is $250 ($125 for small entity)
`
`
`for each additional 50 sheets or fraction thereof. See 35 U.S.C. 41(a)(1)(G) and 37 CFR 1.16(s).
`Total Sheets
`Extra Sheets
`Number of each additional 50 or fraction thereof
`Fee (fi)
`Fee Paid (fl
`
`
`
`
`= - 100 = ‘ / 50 = (round up to a whole number) x
`
`
`
`4. OTHER FEE(S)
`.
`Fees Paid l§l
` Non-English Specification,
`$130 fee (no small entity discount)
`
` Other:
`
`
`
`
`
`
`
`DateName (Printfl'ype) KentJ. Tobin June 24, 2005
`60522487 v1
`
`r
`
`Registration No.
`
`
`
`Ex. 1020, Page 4
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`Ex. 1020, Page 4
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`

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`Attorney Docket No.: 019152-001114US
`
`CLEAN VERSION OF SUBSTITUTE SPECIFICATION
`
`UNDER 37 CFR 1.125
`
`PATENT APPLICATION
`
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD
`
`Inventor:
`
`‘ William W. Y. Chu, a citizen of The United States, residing at
`1320 Miravalle Avenue
`
`Los Altos, CA 94024
`
`Assignee:
`
`ACQIS Technology, Inc.
`1621 W. El Camino Real
`
`Mountain View, CA 94040
`
`Entity:
`
`Small
`
`TOWNSEND and TOWNSEND and CREW LLP
`
`Two Embarcadero Center, Eighth Floor
`San Francisco, California 94111-3834
`Tel: 650—326-2400
`
`Ex. 1020, Page 5
`
`Ex. 1020, Page 5
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`

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`Attorney Docket No.: 019152-001114US
`
`PATENT
`
`CLEAN VERSION OF SUBSTITUTE SPECIFICATION UNDER 37 CFR 1.125
`
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD
`
`CROSS REFERENCE TO RELATED APPLICATIONS
`
`[0001] The present application claims priority as a continuation of US. nonprovisional
`
`patent application no. 11/097,694, filed March 31, 2005, which is a continuation of US.
`
`nonprovisional patent application no. 10/772,214, filed February 3, 2004, which is a
`
`continuation of US. nonprovisional patent application no. 09/569,758, filed May 12, 2000
`
`(Now US. patent no. 6,718,415), which claimed priority to US. Provisional Application No.
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`60/134,122 filed May 14, 1999, commonly assigned, and hereby incorporated by reference.
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`10
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`3O
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`BACKGROUND OF THE INVENTION
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`[0002] The present invention relates to computing devices. More particularly, the present
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`invention provides a system including a plurality of computer modules that can independently
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`operate to provide backup capability, dual processing, and the like. Merely by way of
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`example, the present invention is applied to a modular computing environment for desk top
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`computers, but it will be recognized that the invention has a much wider range of
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`applicability. It can be applied to a server as well as other portable or modular computing
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`applications.
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`[0003] Many desktop or personal computers, which are commonly termed PCs, have been
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`around and used for over ten years. The PCs oflen come with state—of—art microprocessors
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`such as the Intel PentiumTM microprocessor chips. They also include a hard or fixed disk
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`drive such as memory in the giga-bit range. Additionally, the PCs often include a random
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`access memory integrated circuit device such as a dynamic random access memory device,
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`which is commonly termed DRAM. The DRAM devices now provide up to millions of
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`memory cells (i.e., mega-bit) on a single slice of silicon. PCs also include a high resolution
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`display such as cathode ray tubes or CRTs. In most cases, the CRTs are at least 15 inches or
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`17 inches or 20 inches in diameter. High resolution flat panel displays are also used with
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`PCs.
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`[0004] Many external or peripheral devices can be used with the PCs. Among others, these
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`peripheral devices include mass storage devices such as a ZipTM Drive product sold by
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`Iomega Corporation of Utah. Other storage devices include external hard drives, tape drives,
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`Ex. 1020, Page 6
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`Ex. 1020, Page 6
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`and others. Additional devices include communication devices such as a modem, which can
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`be used to link the PC to a wide area network of computers such as the Internet.
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`Furthermore, the PC can include output devices such as a printer and other output means.
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`Moreover, the PC can include special audio output devices such as speakers the like.
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`[0005]
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`PCs also have easy to use keyboards, mouse input devices, and the like. The
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`keyboard is generally configured similar to a typewriter format. The keyboard also has the
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`length and width for easily inputting information by way of keys to the computer. The mouse
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`also has a sufficient size and shape to easily move a curser on the display from one location
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`to another location.
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`[0006] Other types of computing devices include portable computing devices such as
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`"laptop" computers and the like. Although somewhat successful, laptop computers have
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`many limitations. These computing devices have poor display technology. In fact, these
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`devices often have a smaller flat panel display that has poor viewing characteristics.
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`Additionally, these devices also have poor input devices such as smaller keyboards and the
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`like. Furthermore, these devices have limited common platforms to transfer information to
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`and from these devices and other devices such as PCs.
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`[0007] Up to now, there has been little common ground between these platforms including
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`the PCs and laptops in terms of upgrading, ease-of-use, cost, performance, and the like.
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`Many differences between these platforms, probably somewhat intentional, has benefited
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`computer manufacturers at the cost of consumers. A drawback to having two separate
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`computers is that the user must often purchase both the desktop and laptop to have "total"
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`computing power, where the desktop serves as a "regular" computer and the laptop serves as
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`a "portable" computer. Purchasing both computers is often costly and runs "thousands" of
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`dollars. The user also wastes a significant amount of time transferring sofiware and data
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`between the two types of computers. For example, the user must often couple the portable
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`computer to a local area network (i.e., LAN), to a serial port with a modem and then
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`manually transfer over files and data between the desktop and the portable computer.
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`Alternatively, the user often must use floppy disks to "zip" up files and programs that exceed
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`the storage capacity of conventional floppy disks, and transfer the floppy disk data manually.
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`[0008] Another drawback with the current model of separate portable and desktop
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`computer is that the user has to spend money to buy components and peripherals the are
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`duplicated in at least one of these computers. For example, both the desktop and portable
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`Ex. 1020, Page 7
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`Ex. 1020, Page 7
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`computers typically include hard disk drives, floppy drives, CD-ROMS, computer memory,
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`host processors, graphics accelerators, and the like. Because program software and
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`supporting programs generally must be installed upon both hard drives in order for the user to
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`operate programs on the road and in the office, hard disk space is often wasted.
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`[0009] One approach to reduce some of these drawbacks has been the use of a docking
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`station with a portable computer. Here, the user has the portable computer for "on the road"
`
`use and a docking station that houses the portable computer for office use.
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`[0010]
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`Similar to separate desktop and portable computers, there is no commonality
`
`between two desktop computers. To date, most personal computers are constructed with a
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`single motherboard that provides connection for CPU and other components in the computer.
`
`Dual CPU systems have been available through Intel’s slot 1 architecture. For example, two
`
`Pentium II cartridges can be plugged into two “slot 1” card slots on a motherboard to form a
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`Dual-processor system. The two CPU’s share a common host bus that connects to the rest of
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`the system, e. g. main memory, hard disk drive, graphics subsystem, and others. Dual CPU
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`systems have the advantage of increased CPU performance for the whole system. Adding a
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`CPU cartridge requires no change in operating systems and application software. However,
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`dual CPU systems may suffer limited performance improvement if memory or disk drive
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`bandwidth becomes the limiting factor. Also, dual CPU systems have to time-share the
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`processing unit in running multiple applications. CPU performance improvement efficiency
`
`also depends on software coding structure. Dual CPU systems provide no hardware
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`redundancy to help fault tolerance. In running multiple applications, memory and disk drive
`
`data throughput will become the limiting factor in improving performance with multi-
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`processor systems.
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`[0011]
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`The present invention generally relates to computer interfaces. More specifically,
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`the present invention relates to an interface channel that interfaces two computer interface
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`buses that operate under protocols that are different from that used by the interface channel.
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`[0012]
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`Interfaces coupling two independent computer buses are well known in the art. A
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`block diagram of a computer system utilizing such a prior art interface is shown in Fig. 5. In
`
`Fig. 5, a primary peripheral component interconnect (PCI) bus 505 of a notebook PC 500 is
`
`coupled to a secondary PCI bus 555 in a docking system 550 (also referred to as docking
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`station 550) through high pin count connectors 501 and 502, which are normally mating
`
`connectors. The high pin count connectors 501 and 502 contain a sufficiently large number
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`Ex. 1020, Page 8
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`Ex. 1020, Page 8
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`of pins so as to carry PCI bus signals between the two PCI buses without any translation.
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`The main purpose for interfacing the two independent PCI buses is to allow transactions to
`
`occur between a master on one PCI bus and a target on the other PCI bus. The interface
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`between these two independent PCI buses additionally includes an optional PCI to PCI bridge
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`560, located in the docking station 550, to expand the add on capability in docking station
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`550. The bridge 560 creates a new bus number for devices behind the bridge 560 so that they
`
`are not on the same bus number as other devices in the system thus increasing the add on
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`capability in the docking station 550.
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`[0013] An interface such as that shown in Fig. 5 provides an adequate interface between the
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`primary and secondary PCI buses. However, the interface is limited in a number of ways.
`
`The interface transfers signals between the primary and secondary PCI buses using the
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`protocols of a PCI bus. Consequently, the interface is subject to the limitations under which
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`PCI buses operate. One such limitation is the fact that PCI buses are not cable friendly. The
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`cable friendliness of the interface was not a major concern in the prior art. However, in the
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`context of the computer system of the present invention, which is described in the present
`
`inventor's (William W.Y. Chu's) application for "Personal Computer Peripheral Console With
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`Attached Computer Module" filed concurrently with the present application on Sep. 8, 1998
`
`and incorporated herein by reference, a cable friendly interface is desired for interfacing an
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`attached computer module (ACM) and a peripheral console of the present invention.
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`Furthermore, as a result of operating by PCI protocols, the prior art interface includes a very
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`large number of signal channels with a corresponding large number of conductive lines (and a
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`similarly large number of pins in the connectors of the interface) that are commensurate in
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`number with the number of signal lines in the PCI buses which it interfaces. One
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`disadvantage of an interface having a relatively large number of conductive lines and pins is
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`that it costs more than one that uses a fewer number of conductive lines and pins.
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`Additionally, an interface having a large number of conductive lines is bulkier and more
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`cumbersome to handle. Finally, a relatively large number of signal channels in the interface
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`renders the option of using differential voltage signals less Viable because a differential
`
`voltage signal method would require duplicating a large number of signal lines. It is
`
`desirable to use a low voltage differential signal (LVDS) channel in the computer system of
`
`the present invention because an LVDS channel is more cable friendly, faster, consumes less
`
`power, and generates less noise, including electromagnetic interferences (EMI), than a PCI
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`Ex. 1020, Page 9
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`Ex. 1020, Page 9
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`channel. The term LVDS is herein used to generically refer to low voltage differential
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`signals and is not intended to be limited to any particular type of LVDS technology.
`
`[0014]
`
`Thus, what is needed are computer systems that can have multiple computer
`
`modules. Each computer module has dedicated memory and disk drive, and can operate
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`5
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`independently.
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`BRIEF SUMMARY OF THE INVENTION
`
`[0015] According to the present invention, a technique including a method and device for
`
`multi—module computing is provided. In an exemplary embodiment, the present invention
`
`provides a system including a plurality of computer modules that can independently operate
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`10
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`to provide backup capability, dual processing, and the like.
`
`[0016]
`
`In a specific embodiment, the present invention provides a computer system for
`
`multi-processing purposes. The computer system has a console comprising a first coupling
`
`site and a second coupling site, e. g., computer module bay. Each coupling site comprises a
`
`connector. The console is an enclosure that is capable of housing each coupling site. The
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`15
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`system also has a plurality of computer modules, where each of the computer modules is
`
`coupled to one of the connectors. Each of the computer modules has a processing unit, a
`
`main memory coupled to the processing unit, a graphics controller coupled to the processing
`
`unit, and a mass storage device coupled to the processing unit. Each of the computer
`
`modules is substantially similar in design to each other to provide independent processing of
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`20
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`each of the computer modules in the computer system.
`
`[0017]
`
`In an alternative specific embodiment, the present invention provides a multi-
`
`processing computer system. The system has a console comprising a first coupling site and a
`
`second coupling site. Each coupling site comprises a connector. The console is an enclosure
`
`that is capable of housing each coupling site. The system also has a plurality of computer
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`25
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`modules, where each of the computer modules is coupled to one of the connectors. Each of
`
`the computer modules has a processing unit, a main memory coupled to the processing unit, a
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`graphics controller coupled to the processing unit, a mass storage device coupled to the
`
`processing unit, and a video output coupled to the processing unit. Each of the computer
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`modules is substantially similar in design to each other to provide independent processing of
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`30
`
`each of the computer modules in the computer system. A video switch circuit is coupled to
`
`Ex. 1020, Page 10
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`Ex. 1020, Page 10
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`

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`each of the computer modules through the video output. The video switch is configured to
`
`switch a video signal from any one of the computer modules to a display.
`
`[0018] Numerous benefits are achieved using the present invention over previously existing
`
`techniques. In one embodiment, the invention provides improved processing and
`
`maintenance features. The invention can also provide increased CPU performance for the
`
`whole system. The invention also can be implemented without changes in operating system
`
`and application software. The present invention is also implemented using conventional
`
`technologies that can be provided in the present computer system in an easy and efficient
`manner.
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`[0019]
`
`In another embodiment, the invention provides at least two users to share the same
`
`modular desktop system. Each user operates on a different computer module. The other
`
`peripheral devices, i.e. CDROM, printer, DSL connection, etc. can be shared. This provides
`
`lower system cost, less desktop space and more efficiency. Depending upon the embodiment,
`
`one or more of these benefits can be available. These and other advantages or benefits are
`
`described throughout the present specification and are described more particularly below.
`
`[0020]
`
`In still further embodiments, the present invention provides methods of using
`
`multiple computer modules.
`
`[0021] The present invention encompasses an apparatus for bridging a first computer
`
`interface bus and a second computer interface bus, where each of the first and second
`
`computer interface buses have a number of parallel multiplexed address/data bus lines and
`
`operate at a clock speed in a predetermined clock speed range having a minimum clock speed
`
`and a maximum clock speed. The apparatus comprises an interface channel having a clock
`
`line and a plurality of bit lines for transmitting bits; a first interface controller coupled to the
`
`first computer interface bus and to the interface channel to encode first control signals from
`
`the first computer interface bus into first control bits to be transmitted on the interface
`
`channel and to decode second control bits received from the interface channel into second
`
`control signals to be transmitted to the first computer interface bus; and a second interface
`
`controller coupled to the interface channel and the second computer interface bus to decode
`
`the first control bits from the interface channel into third control signals to be transmitted on
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`30'
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`the second computer interface bus and to encode fourth control signals from the second
`
`computer interface bus into the second control bits to be transmitted on the interface channel.
`
`Ex. 1020, Page 11
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`Ex. 1020, Page 11
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`

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`[0022]
`
`In one embodiment, the first and second interface controllers comprise a host
`
`interface controller (HIC) and a peripheral interface controller (PIC), respectively, the first
`
`and second computer interface buses comprise a primary PCI and a secondary PCI bus,
`
`respectively, and the interface channel comprises an LVDS channel.
`
`[0023] The present invention overcomes the aforementioned disadvantages of the prior art
`
`by interfacing two PCI or PCI-like buses using a non—PCI or non-PCI—like channel. In the
`
`present invention, PCI control signals are encoded into control bits and the control bits, rather
`
`than the control signals that they represent, are transmitted on the interface channel. At the
`
`receiving end, the control bits representing control signals are decoded back into PCI control
`
`signals prior to being transmitted to the intended PCI bus.
`
`[0024] The fact that control bits rather than control signals are transmitted on the interface
`
`channel allows using a smaller number of signal channels and a correspondingly small
`
`number of conductive lines in the interface channel than would otherwise be possible. This is
`
`because the control bits can be more easily multiplexed at one end of the interface channel
`
`and recovered at the other end than control signals. This relatively small number of signal
`
`channels used in the interface channel allows using LVDS channels for the interface. As
`
`mentioned above, an LVDS channel is more cable fi'iendly, faster, consumes less power, and
`
`generates less noise than a PCI bus channel, which is used in the prior art to interface two
`
`PCI buses. Therefore, the present invention advantageously uses an LVDS channel for the
`
`hereto unused purpose of interfacing PCI or PCI—like buses. The relatively smaller number of
`
`signal channels in the interface also allows using connectors having smaller pins counts. As
`
`mentioned above an interface having a smaller number of signal channels and, therefore, a
`
`smaller number of conductive lines is less bulky and less expensive than one having a larger
`
`number of signal channels. Similarly, connectors having a smaller number of pins are also
`
`less expensive and less bulky than connectors having a larger number of pins.
`
`[0025]
`
`In one embodiment, the present invention encompasses an apparatus for bridging a
`
`first computer interface bus and a second computer interface bus, in a microprocessor based
`
`computer system where each of the first and second computer interface buses have a number
`
`of parallel multiplexed address/data bus lines and operate at a clock speed in a predetermined
`
`clock speed range having a minimum clock speed and a maximum clock speed. The
`
`apparatus comprises an interface channel having a clock channel and a plurality of bit
`
`channels for transmitting bits; a first interface controller coupled to the first computer
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`30
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`Ex. 1020, Page 12
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`Ex. 1020, Page 12
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`

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`interface bus and to the interface channel to encode first control signals from the first
`
`computer interface bus into first control bits to be transmitted on the interface channel and to
`
`decode second control bits received from the interface channel into second control signals to
`
`be transmitted to the first computer interface bus; and a second interface controller coupled to
`
`5
`
`the interface channel and the second computer interface bus to decode the first control bits
`
`from the interface channel into third control signals to be transmitted on the second computer
`
`interface bus and to encode fourth control signals from the second computer interface bus
`
`into the second control bits to be transmitted on the interface channel.
`
`[0026]
`
`In one embodiment, the first and second interface controllers comprise a host
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`10
`
`interface controller (HIC) and a peripheral interface controller (PIC), respectively, the first
`
`and second computer interface buses comprise a primary PCI and a secondary PCI bus,
`
`respectively, and the interface channel comprises an LVDS channel.
`
`[0027]
`
`In a preferred embodiment, the interface channel has a plurality of serial bit
`
`channels numbering fewer than the number of parallel bus lines in each of the PCI buses and
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`15
`
`operates at a clock speed higher than the clock speed at which any of the bus lines operates.
`
`More specifically, the interface channel includes two sets of unidirectional serial bit channels
`
`which transmit data in opposite directions such that one set of bit channels transmits serial
`
`bits from the HIC to the PIC while the other set transmits serial bits from the PIC to the HIC.
`
`For each cycle of the PCI clock, each bit channel of the interface channel transmits a packet
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`20
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`of serial bits.
`
`[0028]
`
`The HIC and PIC each include a bus controller to interface with the first and second
`
`computer interface buses, respectively, and to manage transactions that occur therewith. The
`
`HIC and PIC also include a translator coupled to the bus controller to encode control signals
`
`from the first and second computer interface buses, respectively, into control bits and to
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`25
`
`decode control bits from the interface channel into control signals. Additionally, the HIC and
`
`PIC each include a transmitter and a receiver coupled to the translator. The transmitter
`
`converts parallel bits into serial bits and transmits the serial bits to the interface channel. The
`
`receiver receives serial bits from the interface channel and converts them into parallel bits.
`
`[0029]
`
`These and other embodiments of the present invention, as well as its advantages and
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`30
`
`features, are described in more detail in conjunction with the text below and attached Figs.
`
`Ex. 1020, Page 13
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`Ex. 1020, Page 13
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`

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`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0030]
`
`Fig. 1 is a simplified diagram of a computer system according to an embodiment of
`
`the present invention;
`
`[0031]
`
`Fig. 2 is a simplified block diagram of a computer system according to an
`
`alternative embodiment of the present invention;
`
`[0032]
`
`Fig. 3 is a simplified block diagram of a compeer system according to a further
`
`alternative embodiment of the present invention; and
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`15
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`
`[0033]
`
`Fig. 4 is a simplified flow diagram of a method according to an embodiment of the
`
`present invention.
`
`[0034]
`
`Fig. 5 is a block diagram of a computer system using a prior art interface between a
`
`primary and a secondary PCI bus.
`
`[0035]
`
`Fig. 6 is a block diagram of one embodiment of a computer system using the
`
`interface of the present invention.
`
`[0036]
`
`Fig. 7 is a partial block diagram of a computer system using the interface of the
`
`present invention as a bridge between the north and south bri