Intel Corporation v. ACQIS LLC
`Intel Corp.'s Exhibit 1009
`Ex. 1009, Page 1
`
`

`

`PTO/SB/14 (11-08)
`Approved for use through 09/30/2010. OMB 0651-0032
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection ofinformation unless it contains a valid OMB control number.
`
`
`Attorney Docket Number|ACQI-010/19US 310578-2066
`
`Application Data Sheet 37 CFR 1.76
`
`
`
`Application Number
`
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL CHANNEL
`Title of Invention|GomprisiNG UNIDIRECTIONAL SERIAL BIT CHANNELS
`
`
`
`
`
`The application data sheetis part of the provisional or nonprovisional application for whichit is being submitted. The following form contains the
`bibliographic data arranged in a format specified by the United States Patent and Trademark Office as outlined in 37 CFR 1.76.
`This document may be completed electronically and submitted to the Office in electronic format using the Electronic Filing System (EFS) or the
`document may be printed and included in a paper filed application.
`
`
`58249
`
`
`Secrecy Order 37 CFR 5.2
`[_] Portions orall of the application associated with this Application Data Sheet mayfall under a Secrecy Order pursuantto
`37 CFR 5.2 (Paperfilers only. Applications that fall under Secrecy Order may not befiled electronically.)
`
`Applicant Information:
`
`
`Applicant 1
`Applicant Authority @Inventor | ©)Legal Representative under 35 U.S.C. 117
`
`
`|Party ofInterest under 35 U.S.C. 118
`
`Prefix) Given Name
`
`Middle Name
`
`Family Name
`
`Suffix
`
`
`
`() Active US Military Service
`©) NonUS Residency
`(@) US Residency
`Residence Information (Select One)
`
`
`City|Los Altos State/Province|CA Country of Residencei|US
`
`Citizenship under 37 CFR 1.41(b)i
`
`
`US
`
`Mailing Address of Applicant:
`Address 1
`1320 Miravalle Avenue
`
`Address 2
`
`City
`
`Los Altos
`
`State/Province
`
`CA
`
`Inventor Information blocks may be
`Inventors Must Be Listed - Additional
`All
`Add
`
`generated within this form by selecting the Add button.
`
`CorrespondenceInformation:
`
`Enter either Customer Number or complete the Correspondence Information section below.
`For further information see 37 CFR 1.33({a).
`
`[|] An Addressis being provided for the correspondenceInformation of this application.
`
`Customer Number
`
`
`
`Email Address Add Email |
`
`
`
`Application Information:
`;
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL
`Title of the Invention
`CHANNEL COMPRISING UNIDIRECTIONAL SERIAL BIT CHANNELS
`
`Attorney Docket Number]ACQI-010/19US310578-2066 Small Entity Status Claimed [|
`Application Type
`Nonprovisional
`
`Subject Matter
`Utility
`Suggested Class(if any)PO Sub Class(if any)
`Suggested Technology Center(if any)
`
`Total Number of Drawing Sheets (if any)
`
`Suggested Figure for Publication (if any)
`
`EFS Web 2.2.2
`
`Ex. 1009, Page 2
`
`
`
`Ex. 1009, Page 2
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`

`

`PTO/SB/14 (11-08)
`Approved for use through 09/30/2010. OMB 0651-0032
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`Underthe Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it contains a valid OMB control number.
` Application Data Sheet 37 CFR 1.76
`
`Attorney Docket Number|ACQI-010/19US 310378-2066
`
`
`
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL CHANNEL
`
`Title of Invention
`COMPRISING UNIDIRECTIONAL SERIAL BIT CHANNELS
`
`
`
`Application Number
`
`Publication Information:
`
`[_] Request Early Publication (Fee required at time of Request 37 CFR 1.219)
`
`Req uest Not to Publish. | hereby request that the attached application not be published under 35 U.S.
`[-] ©. 122(b) and certify that the invention disclosedin the attached application has not and will not be the subject of
`an application filed in ancther country, or under a multilateral international agreement, that requires publication at
`eighteen monthsafterfiling.
`
`Representative Information:
`
`Representative information should be provided for all practitioners having a power of attorney in the application. Providing
`this information in the Application Data Sheet does not constitute a power of attorney in the application (see 37 CFR 1.32).
`
`
`
`
`
`
`Enter Representative Name_sectioneither Customer Number or complete the below. If both sections
`
`
`are completed the Customer Numberwill be used for the Representative Information during processing.
`
`
`
`
`Please Select One:
`
`(#) Customer Number
`
`(©) US PatentPractitioner
`
`
`
`C) Limited Recognition (37 CFR 11.9}
`
`Customer Number
`
`58249
`
`Domestic Benefit/National Stage Information:
`
`This section allows for the applicant to either claim benefit under 35 U.S.C. 119(e), 120, 121, or 365(c) or indicate National Stage
`entry from a PCT application. Providing this information in the application data sheet constitutes the specific reference required by
`
`Prior Application Status|Pending
`
`Application Number
`
`Continuity Type
`
`Prior Application Number
`
`Filing Date (YYYY-MM-DD}
`
`Continuation of
`
`12504534
`
`2009-07-16
`
`
`
`
`
`
`
`
`
`35 U.S.C. 119(e) or 120, and 37 CFR 1.78{a)(2) or CFR 1.78(a}(4), and need not otherwise be made part of the specification.
`
`Prior Application Status
`
`Application Number
`
`Continuity Type
`
`Prior Application Number
`
`Filing Date (YYYY-MM-DD}
`
`12504534
`
`Continuation of
`
`12077503
`
`2008-03-18
`
`Prior Application Status
`
`Application Number
`
`Continuity Type
`
`Prior Application Number
`
`Filing Date (YYYY-MM-DD}
`
`12077503
`
`Continuation of
`
`11166656
`
`2005-06-24
`
`Prior Application Status
`
`Application Number
`11166656
`
`Continuity Type
`Continuation of
`
`Prior Application Number
`11097694
`
`Filing Date (YYYY-MM-DD}
`2005-03-31
`
`Prior Application Status
`
`Application Number
`11097694
`
`Continuity Type
`Continuation of
`
`Prior Application Number
`10772214
`
`Filing Date (YYYY-MM-DD}
`2004-02-03
`
`Prior Application Status
`
`EFS Web 2.2.2
`
`Ex. 1009, Page 3
`
`Ex. 1009, Page 3
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`

`

`PTO/SB/14 (11-08)
`Approved for use through 09/30/2010. OMB 0651-0032
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`Underthe Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it contains a valid OMB control number.
` Application Data Sheet 37 CFR 1.76
`
`Attorney Docket Number|ACQI-010/19US 310378-2066
`
`
`
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL CHANNEL
`
`Title of Invention
`COMPRISING UNIDIRECTIONAL SERIAL BIT CHANNELS
`
`Application Number
`
`Prior Application Status
`
`
`
`
`
`
`
`
`
`
`
`
`Application Number
`10772214
`
`Continuity Type
`Continuation of
`
`Prior Application Number
`09569758
`
`Filing Date (YYYY-MM-DD}
`2000-05-12
`
`Application Number
`
`Continuity Type
`
`Prior Application Number
`
`Filing Date (YYYY-MM-DD}
`
`09569758
`
`non provisional of
`
`60134122
`
`1999-05-14
`
`
`
`Additional Domestic Benefit/National Stage Data may be generated within this form
`by selecting the Add button.
`Ace
`
`
`Foreign Priority Information:
`This section allows for the applicant to claim benefit of foreign priority and to identify any prior foreign application for which priority is
`not claimed. Providing this information in the application data sheet constitutes the claim for priority as required by 35 U.S.C. 119(b)
`and 37 CFR 1.55(a).
`
`Application Number
`Country |
`ParentFiling Date (YYYY-MM-DD}
`Priority Claimed
`
`
`(@) Yes ©) No
`
`Additional Foreign Priority Data may be generated within this form by selecting the
`Add button.
`
`Add
`
`Assignee Information:
`Providing this information in the application data sheet does not substitute for compliance with any requirement of part 3 of Title 37
`of the CFR to have an assignmentrecorded in the Office.
`
`Assignee 1
`
`If the Assignee is an Organization check here.
`
`Organization Name
`
`ACQIS LLC
`
`Mailing Address Information:
`
`Address 1
`
`Address 2
`
`411 Interchange Street
`
`Email Address
`
`Additional Assignee Data may be generated within this form by selecting the Add
`button.
`
`Aad
`
`Signature:
`
`A signature of the applicant or representative is required in accordance with 37 CFR 1.33 and 10.18. Please see 37
`CFR 1.4(d) for the form of the signature.
`
`EFS Web 2.2.2
`
`Ex. 1009, Page 4
`
`
`
`Ex. 1009, Page 4
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`

`

`PTO/SB/14 (11-08)
`Approved for use through 09/30/2010. OMB 0651-0032
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`Underthe Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it contains a valid OMB control number.
`
`oo Attorney Docket Number|ACQI-010/19US 310378-2066
`
`Application Data Sheet 37 CFR 1.76
`
`— Title of Invention
`
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL CHANNEL
`COMPRISING UNIDIRECTIONAL SERIAL BIT CHANNELS
`
`This collection of information is required by 37 CFR 1.76. The information is required to obtain or retain a benefit by the public which
`is to file (and by the USPTO to process) an application. Confidentiality is governed by 35 U.S.C. 122 and 3 CFR 1.14. This
`collection is estimated to take 23 minutes to complete, including gathering, preparing, and submitting the completed application data
`sheet form to the USPTO. Time will vary depending upon the individual case. Any comments on the amountof time you require to
`complete this form and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, U.S. Patent and
`Trademark Office, U.S. Department of Commerce, P.O. Box 1450, Alexandria, VA 22313-1450. DO NOT SEND FEES OR
`COMPLETED FORMS TO THIS ADDRESS. SEND TO: Commissionerfor Patents, P.O. Box 1450, Alexandria, VA 22313-1450.
`
`EFS Web 2.2.2
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`Ex. 1009, Page 5
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`Ex. 1009, Page 5
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`

`Privacy Act Statement
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`CFR 1.14, as a routine use, to the public if the record wasfiled in an application which became abandonedorin which the proceedings were
`terminated and which application is referenced by either a published application, an application open to public inspections or an issued
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`
`A record from this system of records may be disclosed, as a routine use, to a Federal, State, or local law enforcement agency,if the
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`
`
`Ex. 1009, Page
`
`EFS Web 2.2.2
`
`6
`
`Ex. 1009, Page 6
`
`

`

`Attorney Docket No: ACQL-O1G/I0US 310578-2032
`
`PATENT
`
`DECLARATION
`“Agaa below named inventor, I hereby declare that:
`ya
`My residence, post office address and citizenship are as slated next to my name:
`3
`yr
`;
`below) ar an
`i balfeve | am the original, first and sole mentor
`if only one name is listed
`
`original, first and joitt inventor (if ohual names are Hsted below) of the subject matter which 1s
`claimed and for winch a patent is sought on the invention entitled:
`
`TULTIPLE MODULE COMPUTER SXSTEMLANDSMETHODINCUDING
`DIFFERENTIAL MGRAL CHANNEL
`‘
`AL BYE
` CHANNELS
`
`attencs
`
`the specification of which:
`t
`:
`feheck one}
`
`PX} ig attached hereta:
`
`[}] was filed as United States Application Serial No.on, aid was amended on
`(applicable):
`
`[] was filed ag FCT International Application No.onand was amended under PCT
`Articls 19 or Article 34 on(ifapplicable):
`
`[ have reviewed and understand the contents of the above-ddentified specification,
`meluding the clairas, as amended by any amendmentreferred to above;
`I acknowledge the duty to disclose to the US. Patent and Trademark Office
`information wviet
`ig knows to me to be material
`ro the ;patentability of said invention in
`
`
`ardance with 37 OFBR. $1.56:
`
`[hereby clairforeign priority benefite under 35 LLS.C. 119 and/or $355 of any foreign
`application(s)
`for patent, any foreign application(s)
`for
`inventor's certificate, OF any PCT
`international application(s) designating at
`least one country other than the Untied Stares o
`Aimerica fisted below,
`1 have also identified below any forcign application(s} for patent, any
`foreign application(s)
`for
`inventor's certificate, or any BOT international applicatian’s
`be
`designating at least one country offer than the United States of Ameria filed|by me on the same
`subject matier having a filing date before thatofthe app!Hcation(s) of which priority is claimed:
`
`PETIA
`
`Ex. 1009, Page 7
`
`Ex. 1009, Page 7
`
`

`

`Atiomey Gocket No. ACOLGIOIOUS D10578-20825
`Page
`
`
`PreeoeFOIIAAN pene
`—ee
`COLUNTRYANTERNATIONAL
`|
`APPLICA TION
`GATE GF FILING
`PRIORITY
`j
`_ eternapontefervertvennvaneNMBER|uy.monthyeary|CLAIMED
`
`
`
`
`
`
`
`hereby claim the benefit under 35 U.S.C. $119(e) of any United States provisional
`
`apaltoationts3) listed below:
`
` OS/1999
`
`
`
`{Application Number)
`a
`iBag Date) way. one, vag
`
`
`{A pplication:Number)"
`
`
`ts
`hereby claim the benefit under 39 U.S.C. §120 and/or $364 of any Linited State
`application(s) or of any imeraational application(s} designating the United States ofAmerica that
`is/are fisted belowand, insofar as the subject matter of each of the claima of this application is
`not disclosed in the peor application(s) in the manrier provided by the first paragraph of 35
`USC. §bi2z,} acknowledge@ the duty to disclose to the U.S. Patent and Trademark Office all
`information known to me to be material to patentalability as defined in 37 CLLR. 81.56 which
`became avvailabie between the filing date(s} of the prior application(s) and the national or PCT
`imtcmadatal iting date of this application:
`
`Poor US. applicationsa}orPOTInternationalApel
`
`benefit under 35LES. 8}o6
`
`ween
`
`TABS,6 ~~
`11097,554
`
`_
`
`ATION
`ary }
`
`all ctatoraents Mads on informacic
`and belef are believed to be truc: andfurther thar these
`hereby declare that all statements made herein ofmy own knowledge are true and he
`Statementswere made with the kodWitdgethat willl falsestatements and the like sameeea
`
`are
`punishable byfine or iinprisonment, or both, under Seotiog 1501 of Title [8 of ththe United State
`
`SSTGTL VLA
`
`Ex. 1009, Page 8
`
`Ex. 1009, Page 8
`
`

`

`Attorney Docket No. ACOLO1O/
`
`3105 78-2082
`3
`
`Code and that such willfil false statements may joopardize the validity of the aoplleation or any
`patent iasued thereon,
`
`Full name ofeee a
`inventor'ssignatateProblemwhee.Molen
`wane
`} fi
`Residence: william WW. ¥. Che
`_—
`
`pac7/tb(eed
`;
`/
`~
`,
`7
`
`United Séintes
`Cigzen ah
`Post Office Address:
`1320 Miravalle Avenue, Las Alias, CA 94824
`
`PRTG PS LPR
`
`Lad
`
`Ex. 1009, Page 9
`
`Ex. 1009, Page 9
`
`

`

`Attorney Docket No. ACOLG10/10U5 3 10578-2032
`
`PATENT
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`in Re Application of William W. Y. Cha
`
`Confirmation No. Not Yet Assigned
`
`Serial No.
`
`Nat Yet Assigned
`
`Group Art Unit:
`
`Not Yet Assigned
`
`Filed:
`
`Judy 16, 2009
`
`Examiner:
`
`Not Yet Assigned
`
`For: MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING
`DIFFERENTIAL SIGNAL CHANNEL COMPRISING UNDIRECTIONAL SERIAL
`BIT
`
`
`
`Commissioner for Patents
`PO. Box 1450
`Alexandria, VA 22313-1450
`
`POWER BY ASSEGNER
`AND STATEMENT UNDER 37 C.PLR. §3.73(b)
`
`The Assignee of the entire right,
`
`tile, and interest m the above-identified
`
`application hereby grants the registered practitioners of Cooley Godward Kronish LLP
`
`included in the Customer Number provided below power to act, prosecute, and transact
`
`all business in the U.S. Patent and Trademark Office in connection with this application,
`
`any applications claimingpriority to this application, and any patents issuing thercirom.
`
`The Assigneecertifies that to the best of its knowledge and beliefit is the owner
`
`of the entire night,
`
`tile, and interest
`
`in and to the above-identified application as
`
`(
`
`[Xk]
`
`An assignment document, a copy of which is enclosed herewith,
`
`An assignment previously recorded in the U.S. Patent and Trademark
`CHfice at Reel 022460, Frame 0848; and Reel 22461, Frame 0782.
`
`Please direct all telephone calls and correspondenceto;
`
`CUSTOMER NUMBER:
`
`S8I49
`
`TE7G96 VLIPA
`
`Ex. 1009, Page 10
`
`Ex. 1009, Page 10
`
`

`

`seaterelayeOPASSE
`
`Atiomey Docket No, ACOLO1G/1 00S 316578.2052
`Application Serial No.
`Page 2
`
`COOLSY GODWARD KRCwISH LLP
`
`ATTN: Pater: Group
`777 6" Street NW, Suite 1100
`Washington, DC 2600!
`Tels (6303 £43.5852
`Fax: (202) $42-7899
`
`The undersigned (whose ttle is supplied below?)is empowered fo sign this
`statement on behalf ofthe Assignee.
`
`Cate:Ub[2004
`
`fig
`
`snerntAERIE
`
`een
`
`net
`
`Signature:KestbednBexoo
`
`£“MhcA
`af
`Willem WY. Chu mf
`Name:
`
`President
`Pithe:
`Company: ACQILLC
`
`FONGa VPA
`
`ETNpntennaeee
`
`Ex. 1009, Page 11
`
`Ex. 1009, Page 11
`
`

`

`Attorney Docket No. ACQI-010/19US 310578-2066
`
`PATENT
`
`IN THE UNITED STATES PATENT AND TRADEMARKOFFICE
`
`
`
`In re Application of: William W.Y. Chu Confirmation No.:|Unassigned
`
`Application No.:
`
`Unassigned
`
`Group Art Unit:
`
`Unassigned
`
`Filed:
`
`Herewith
`
`Examiner:
`
`Unassigned
`
`Title:.MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL
`CHANNEL COMPRISING UNIDIRECTIONAL SERIAL BIT CHANNELS
`
`
`
`Mail Stop: Amendment
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`PRELIMINARY AMENDMENT
`
`Prior to examination of the above-identified application, please amend the subject
`
`application as follows:
`
`Amendments to the Drawings begin on page 2 of this paper.
`
`Amendmentsto the Title begin on page 3 of this paper.
`
`Amendmentsto the Specification begin on page 4 ofthis paper.
`
`Amendments to the Claims begin on page6 of this paper.
`
`Remarks/Arguments begin on page 15 of this paper.
`The Director is hereby authorized to charge any appropriate fees under 37 C.F.R. §§1.16,
`1.17, and 1.21 that may be required by this paper, and to credit any overpayment, to Deposit
`Account No. 50-1283.
`
`|
`
`933063 VIVHN
`
`Ex. 1009, Page 12
`
`Ex. 1009, Page 12
`
`

`

`Atty. Docket No. ACQI-010/19US 310578-2066
`Page 2
`
`IN THE DRAWINGS
`
`Attachment: New Sheets FIG. 8A and FIG. 8B
`
`The subject application is amended to specifically include certain figures from U.S.
`
`Provisional Application No. 60/083,886.
`
`933063 v1/HN
`
`Ex. 1009, Page 13
`
`Ex. 1009, Page 13
`
`

`

`Atty. Docket No. ACQI-010/19US 3 10578-2066
`Page 3
`
`IN THE TITLE
`
`Please amendthetitle as follows:
`
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL
`
`CHANNEL COMPRISING UNDIRECFIONAL UNIDIRECTIONAL SERIAL BIT CHANNELS
`
`933063 v1/HN
`
`Ex. 1009, Page 14
`
`Ex. 1009, Page 14
`
`

`

`Atty. Docket No. ACQI-010/19US 310578-2066
`Page 4
`
`IN THE SPECIFICATION
`
`Please replace paragraph no.
`
`[0001] with the following paragraph.
`
`The amendments to
`
`paragraph no. [0001] are indicated by strikethrough and underlining.
`
`[0001] This application is a continuation of U.S. Application No. 12/504,534 filed July
`
`
`16, 2009, which is a continuation of U.S. Application No. 12/077,503 filed March 18, 2008
`
`(Now U.S. Patent No. 7,676,624), which is a continuation of U.S. nonprovisional Application
`No. 11/166,656, filed June 24, 2005 (Now U.S. Patent No. 7,376,779), which is a continuation
`of U.S. nonprovisional Application No. 11/097,694, filed March 31, 2005 (Now U.S. Patent No.
`
`7,363,415), which is a continuation of U.S. nonprovisional Application No. 10/772,214, filed
`
`February 3, 2004 (Now U.S. Patent No. 7,099,981), which is a continuation of USS.
`
`nonprovisional Application No. 09/569,758,
`
`filed May 12, 2000 (Now U.S. patent no.
`
`6,718,415), and which claimed priority to U.S. Provisional Application No. 60/134,122 filed
`
`May 14, 1999. These applications are hereby incorporated by referencein their entirety.
`
`Please add paragraph nos. [0041.1] and [0041.2] as set forth below immediately after original
`
`paragraph no. [0041]:
`
`[0041.1] Fig. 8A showsan attached computer module with Integrated CPU/NB/Graphics
`
`and Integrated HIC/SB.
`[0041.2] Fig. 8B shows an attached computer module with single chip fully integrated:
`
`CPU, Cache, Core Logic, Graphics controller and Interface controller.
`
`[0093] with the following paragraph.
`Please replace paragraph no.
`paragraph no. [0093] are indicated by strikethrough and underlining.
`
`The amendments to
`
`[0093] In the embodiment shownin Fig. 6, HIC 619 is coupled to an integrated unit 621
`that includes a CPU, a cache and a north bridge.
`In another embodiment, such as that shown in
`Fig. 7, the CPU 705 and north bridge 710 are separate rather than integrated units. In yet another
`embodiment, such as that shown in Fig. 8, the HIC and PIC are integrated with the north and
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`Ex. 1009, Page 15
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`south bridges, respectively, such that integrated HIC and north bridge unit 805 includes an HIC
`
`and a north bridge, while integrated PIC and south bridge unit 810 includes a PIC and a south
`
`bridge. Fig. 8A shows an attached computer module with integrated CPU/NB/Graphics 815 and
`
`Integrated HIC/SB 820. Fig. 8B shows an attached computer module with single chip 825 fully
`
`integrated: CPU, Cache, Core Logic, Graphics controller and Interface controller.
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`Ex. 1009, Page 16
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`IN THE CLAIMS
`
`1-43.
`
`(Cancelled)
`
`44.
`
`(New) A computer system comprising:
`
`a processing unit;
`
`a peripheral bridge to communicate serial bits of Peripheral Component Interconnect
`
`(PCI) bustransaction, the peripheral bridge directly coupled to the processing unit;
`
`a low voltage differential signal (LVDS) channel comprising at least two unidirectional,
`
`differential signal pairs to convey data in opposite directions, the LVDS channel extending from
`
`the peripheral bridge to convey the serial bits of PCI bus transaction, the serial bits of PCI bus
`
`transaction comprising PCI address and databits;
`
`a main memory coupled to the processing unit through the peripheral bridge; and
`
`a peripheral component coupledto the peripheral bridge.
`
`45.
`
`(New) The computer system of claim 44, wherein the peripheral componentis coupled to
`
`the peripheral bridge through the LVDSchannel.
`
`46.|(New) The computer system of claim 45, wherein the peripheral componentis coupled to
`
`the processing unit through the LVDS channel and the peripheral bridge.
`
`47.
`
`(New) The computer system of claim 45, wherein the peripheral component comprises a
`
`serial communication controller,
`
`48.
`
`(New) The computer system of claim 44, further comprising a graphics subsystem
`
`coupled to the processing unit through the peripheral bridge.
`
`49.
`
`(New) The computer system of claim 44, wherein the peripheral bridge comprises a north
`
`bridge.
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`Ex. 1009, Page 17
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`

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`50.|(New) The computer system of claim 49, wherein the peripheral bridge comprises an
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`interface controller integrated with the north bridge, the interface controller is coupled to the
`
`processing unit without any intervening PCI bus, and the interface controller is configured to
`
`output encoded address and data bits of PCI bus transaction in serial form that are conveyed over
`
`the LVDS channel.
`
`51.
`
`(New) The computer system of claim 44, wherein the serial bits of PCI bus transaction
`
`comprise information to permit decoding to create a PCI bustransaction.
`
`52.
`
`(New) The computer system of claim 44, wherein the LVDS channel comprisesa first
`
`plurality of unidirectional, differential signal pairs to convey data inafirst direction and a second
`
`plurality of unidirectional, differential signal pairs to convey data in a second, opposite direction.
`
`53.
`
`(New) A computer system comprising:
`
`a computer module insertable into a console for operation,
`
`the computer module
`
`comprising
`
`a processing unit,
`
`an integrated interface controller and bridge unit to output encoded address and
`
`data bits of Peripheral Component Interconnect (PCI) bus transaction in serial
`
`form,
`
`the
`
`integrated interface controller and bridge unit coupled to the processing unit without any
`
`intervening PCI bus,
`
`a low voltage differential signal (LVDS) channel coupled to the integrated
`
`interface controller and bridge unit to convey the encoded address and data bits of PCI bus
`
`transaction in serial form, and
`
`a main memory coupled to the processing unit through the integrated interface
`
`controller and bridge unit.
`
`54.
`
`(New) The computer system of claim 53, further comprising a peripheral component
`
`coupled to the integrated interface controller and bridge unit through the LVDSchannel.
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`Ex. 1009, Page 18
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`Ex. 1009, Page 18
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`

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`55. (New) The computer system of claim 53, wherein the LVDS channel comprisesafirst
`
`plurality of unidirectional, differential signal pairs to convey datain a first direction and a second
`plurality of unidirectional, differential signal pairs to convey data in a second,opposite direction.
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`Atty. Docket No. ACQI-010/19US 310578-2066
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`(New) The computer system of claim 53, wherein the integrated interface controller and
`56.
`bridge unit comprises a north bridge and an interface controller integrated with the north bridge.
`
`(New) The computer system of claim 53, wherein the computer module comprises an
`57.
`enclosure housing the processing unit, the integrated interface controller and bridge unit, the
`LVDSchannel, and the main memory.
`
`(New) The computer system of claim 53, further comprising the console, and the console
`58.
`comprises a power supply to supply power to the computer module upon insertion into the
`console.
`
`(New) The computer system of claim 58, wherein the console comprises a couplingsite
`59.
`and a multi-port, serial communication hub controller, and the computer module comprises a
`serial communication controller to communicate, via a point-to-point link, with the multi-port,
`serial communication hub controller through the coupling site of the console.
`
`60.
`
`(New) A computer system comprising:
`
`a processing unit;
`
`a low voltage differential signal (LVDS) channel comprising at least two unidirectional
`
`serial bit channels to convey data in opposite directions;
`
`a north bridge coupled to the processing unit, the north bridge comprising an interface
`
`controller to transmit and receive serial bits of Peripheral Component Interconnect (PCI) bus
`
`transaction over the LVDS channel;
`
`a main memory coupled to the processing unit through the north bridge; and
`
`a south bridge coupled to the processing unit through the north bridge.
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`Ex. 1009, Page 19
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`Ex. 1009, Page 19
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`

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`61.|(New) The computer system of claim 60, wherein the south bridge is coupled to the north
`
`bridge through the LVDS channel.
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`62.
`
`(New) The computer system of claim 61, further comprising a peripheral component
`
`coupled to the processing unit through the south bridge, the LVDS channel, and the north bridge.
`
`63.
`
`(New) The computer system of claim 60, wherein the north bridge is directly coupled to
`
`the processing unit.
`
`64.
`
`(New) The computer system of claim 60, wherein the north bridge and the interface
`
`controller are coupled to the processing unit without any intervening PCI bus, and the interface
`
`controller is integrated with the north bridge.
`
`65.
`
`(New) The computer system of claim 60, wherein the serial bits of PCI bus transaction
`
`comprise encoded PCI address and data bits, the LVDS channel extends from the north bridge to
`
`convey the encoded PCI address and data bits, and the LVDS channel comprisesafirst plurality
`of unidirectional, differential signal pairs to convey data in a first direction and a secondplurality
`of unidirectional, differential signal pairs to convey data in a second, opposite direction.
`
`66.
`
`(New) A computer system comprising:
`
`a processing unit;
`
`a main memorycoupledto the processing unit;
`a first
`low voltage differential
`signal
`(LVDS) channel comprising at
`unidirectionalserial bit channels to convey data in opposite directions;
`
`least
`
`two
`
`a first peripheral bridge coupledto the processing unit without any intervening Peripheral
`ComponentInterconnect (PCI) bus,the first peripheral bridge coupled to the first LVDS channel
`to communicate address and data information of PCI bus transaction in serial form over the first
`
`LVDSchannel; and
`
`a secondperipheral bridge coupled to the first peripheral bridge.
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`Ex. 1009, Page 20
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`67.
`
`(New) The computer system of claim 66, wherein the main memory is coupled to the
`
`processing unit through thefirst peripheral bridge.
`
`68.
`
`(New) The computer system of claim 66, wherein the second peripheral bridge is coupled
`
`to the first peripheral bridge through the first LVDS channel.
`
`69.
`
`(New) The computer system of claim 66, wherein the first LVDS channel comprises two
`
`sets of unidirectional, multiple serial bit channels to convey data in opposite directions.
`
`70.
`
`(New) The computer system of claim 66, further comprising a mass storage device
`
`coupled to the second peripheralbridge.
`
`(New) The computer system of claim 66, further comprising a second LVDSchannel
`71.
`comprising at least two unidirectional serial bit channels to convey data in opposite directions,
`and the second peripheral bridge is coupled to the second LVDS channel to communicate PCI
`
`bus transaction in serial form over the second LVDSchannel.
`
`(New) The computer system of claim 66, wherein the first peripheral bridge comprises a
`72.
`north bridge, and the second peripheral bridge comprises a south bridge.
`
`(New) The computer system of claim 72, wherein the first peripheral bridge comprises an
`73.
`interface controller integrated with the north bridge, the i