Intel Corporation v. ACQIS LLC
`Intel Corp.'s Exhibit 1019
`Ex. 1019, Page 1
`
`

`

`
`Effective on 12/08/2004.
`
`
`Fees pursuant to the Consolidated Appropriations Act, 2005 (HR. 4818).
`
`
`
`
`FEE TRANSMITTAL
`
`
`For FY 2005
`
`
`
`,
`,
`.
`E Applicant claims small entIty status. See 37 CFR 1.27
`
`
`(5) 4050
`METHOD or PAYMENT check all that a |
`
`
`
`Alication Number
`
`me Date
`
`First Namedlnventor
`Examiner Name
`
`An Unit
`
`To Be Assigned
`
`To Be Assigned
`
`Attorney Docket No.
`
`
`o19152-oo1112us
`
`PTO/SB/17 (12-04)
`
`
`
`
`
`
`D Check D Credit Card E] Money Order CI None C] Other (please identify):
`E DCPOSit Account
`061305“ Account Number: 20-1430
`Deposit Account Name: Townsend and Townsend and Crew LLP
`For the above-identified deposit account, the Director is hereby authorized to: (check all that apply)
`
`D Charge fee(s) indicated below, except for the filing fee
`[XI Charge fee(s) indicated below
`.
`Charge any additional fee(s) or underpayments of fee(s)
`E Credit any overpayments
`under 37 CFR 1.16 and 1.17
`WARNING: Information on this form may become public. Credlt card Information should not be Included on thls form. Provide credlt card ,
`Information and authorization on PTO-2038
`
`FEE CALCULATION
`
`1. BASIC FILING, SEARCH, AND EXAMINATION FEES
`FILING FEES
`SEARCH FEES
`Small Entig
`Small Entity
`Fee l§l Fee (El
`Fee l§i Fee (fl
`
`Application Type
`
`Utility
`
`Design
`
`Plant
`Reissue
`
`Provisional
`
`300
`
`200
`
`200
`300
`
`200
`
`150
`
`100
`
`100
`150
`
`100
`
`.
`
`-
`
`500
`
`100
`
`300
`500
`
`0
`
`250
`
`50
`
`150
`250
`
`0
`
`4
`
`'
`
`EXAMINATION FEES
`Small Entig
`Fee (fl Fee (5!
`
`100
`
`65
`
`80
`
`200
`
`130
`
`160 ‘
`600
`
`0
`
`Fees Paid (51
`
`500
`
`A
`
`Small Entig
`2. EXCESS CLAIM FEES
`Fee (fl Fee m
`'
`Fee Description
`50
`25
`Each claim over 20 or, for Reissues, each claim over 20 and more than in the original patent
`Each independent claim over 3 or, for Reissues, each independent claim more than in the original patent 200
`100
`Multiple dependent claims
`360
`180
`Fee (fl
`Total Claims
`Extra Claims
`$25
`x
`-20 or HP =
`94
`74
`HP = highest number of total claims paid for, if greater than 20
`lndep. Claims
`Extra Claims
`Fee l§l
`x
`—3 or HP=
`20
`17
`$100
`HP = highest number of independent claims paid for, if greater than 3
`3. APPLICATION SIZE FEE
`
`'
`
`Fee Paid (fl
`$1,850
`
`Fee Paid [$1
`$1,700
`
`=
`
`=
`
`Multiple Dependent Claims
`Fee (fl
`Fee Pald (fl
`
`650-326-2400
`
`If the specification and drawings exceed 100 sheets of paper, the application size fee due is $250 ($125 for small entity)
`for each additional 50 sheets or fraction thereof. See 35 U.S.C. 41(a)(1)(G) and 37 CFR 1.16(s).
`Total Sheets
`Extra Sheets
`Number of each additional 50 or fraction thereof
`Fee (fl
`(round up to a whole number)
`x
`
`Fee Pald (fl
`
`=
`
`- 100 =
`
`/ 50 =
`
`4. OTHER FEE(S)
`
`‘
`
`Fees Paid (fl
`
`Non-English Specification,
`
`$130 fee (no small entity discount)
`
`Other:
`
`BMITTED B
`
`.
`Signature
`Name (Print/Type) KentJ.To in
`
`Registration No.
`(Attorney/Agent)
`
`39,496
`
`Telephone
`Date March 31,2005
`
`60458133 v1
`
`Ex. 1019, Page 2
`
`Ex. 1019, Page 2
`
`

`

`UTILITY
`PATENT APPLICATION
`TRANSMITTAL
`
`Attorney Docket No.
`First Inventor
`
`o19152-oo1112us
`Chu, William w. Y
`MULTIPLE MODULE COMPUTER
`
`PTO/SB/OS (09-0
`
`S.PTO
`
`3.;
`
`997694IIllIIIIIIIIIIIIIIILIIIIIIIIIII
`
`.‘
`
`(Only for new nonprovisional applications under 37 CFR 1.53(b))4
`
`Express Mail Label No.
`
`- APPL'CAT'ON ELEMENTS
`See MPEP chapter 600 concerning utility patent application contents.
`
`ADDRESS TO:
`
`EV 338 443 103 US
`Commissioner for Patents
`PO. Box 1450
`Alexandria, VA 22313-1450
`
`1. IX] Fee Transmittal Form (e.g., PTO/SB/t?)
`(Submit an original and a duplicate for fee processing)
`2. E Applicant claims small entity status.
`See 37 CFR 127.
`1
`34
`[Total Pages
`3. IE Specification
`Both the claims and abstract must start on a new page
`(For information on the preferred arrangement, see MPEP 608.01(a))
`4E Drawing(s) (35 U.S.C.113)
`[Total Sheets
`16
`
`]
`
`2
`
`5. Declaration & Power of Atty [Total Sheets
`a. El Newly executed (original or copy)
`b. E A copy from a prior application (37 CFR 1.63 (d))
`(for a continuation/divisional with Box 18 completed)
`i' E] DELETION OF INVENTOR S
`Signed statementvattached deleting inventor(s)
`named in the prior application, see 37 CFR
`1.63(d)(2) and 1.3303).
`
`.
`9. E] Assignment Papers (cover sheet & document(s))
`_ Name of Assignee
`
`[I Power of
`'10. El 37 CFR 3.73(b) Statement
`Attorney
`(when there is an assignee)
`,
`_
`,
`.
`11- B English Translation Document (’f applicable)
`12. E Information Disclosure Statement (PTO/SBl08 or PTO-1449)
`.
`.
`_
`E Games of Cltatlons attached
`
` ACCOMPANYING APPLICATION PARTS
`
`6. X Application Data Sheet. See 37 CFR 1.76
`
`7. [:1 CD-ROM or CD-R in duplicate, large table or
`Computer Program (Appendix)
`
`D Landscape Table on CD
`.
`.
`.
`.
`T
`8. Nucleotide and/or Amino Acrd Sequence Submissron
`(if applicable, items a. - c. are required)
`a. I] Computer Readable Form (CRF)
`b-
`SpeCIfication sequence Listing 0":
`i- D CD'ROM 0" CD'R (2 C0995); 0"
`ii. El Paper
`
`c. I] Statements verifying identity of above copies
`
`
`
`13. E Preliminary Amendment
`
`14. X Return Receipt Postcard (MPEP 503)
`(Should be specifically itemized)
`[I
`
`Certified Copy of Priority Document(s)
`(if foreign priority is claimed)
`
`15.
`
`16. E] Nonpublication Request under 35 U.S.C. 122 (b)(2)(B)(i).
`Applicant must attach form PTO/SB/35 or its equivalent.
`17. E Other: Title Page, Mark-Up Version of Specification;
`Appendix to Preliminary Amendment containing
`New Sheets Figs. 5-16
`
`18. If a CONTINUING APPLICATION, check appropriate box, and supply the requisite information below and in the first sentence of the
`specification following the title, or in an Application Data Sheet under 37 CFR 1. 76:
`IX Continuation
`D Divisional
`D Continuation—impart (CIP)
`Prior application information:
`Examiner Unassigned
`
`of prior application No: 019/1123.”___________
`Art Unit: 2183
`
`19. CORRESPONDENCE ADDRESS
`
`XI The address associated with Customer Number:
`
`OR E] Correspondence address below
`
`Kent J. Tobin
`
`Date
`
`Registration No.
`Attorne lA-ent
`
`60458160 v1
`
`Ex. 1019, Page 3
`
`Ex. 1019, Page 3
`
`

`

`Effective on 12/03/2004.
`Fees pursuant to the Consolidated Appropriations Act, 2005 (HR. 4818).
`A -Iication Number
`FEE TRANSMITTAL Fen. me
`
`Corn . lete if Known
`I I
`To Be ASSI ned
`
`PTO/SB/17 (12-04)
`
`For FY 2005
`,
`,
`E Applicant claims small entIty status. See 37 CFR 1.27
`
`(5) 4050
`METHOD OF PAYMENT check all that a I
`
`First Named Inventor Chu William W. Y.
`Examiner Name
`To Be Assigned
`.
`To Be Assrgned
`o19152-oo1112us
`
`Art Unit
`Attorney Docket No.
`
`D Check D Credit Card E] Money Order D None C] Other (please identify):
`IX] DCPOSit Account
`DEPOSit Account Number: 20-1430
`Deposit Account Name: Townsend and Townsend and Crew LLP
`For the above-identified deposit account, the Director is hereby authorized to: (check all that apply)
`[XI Charge fee(s) indicated below
`D Charge fee(s) indicated below, except for the filing fee
`Charge any additional fee(s) or underpayments of fee(s)
`.
`under 37 CFR 1.16 and 1.17
`g Credit any overpayments
`WARNING: Information on this form may become public. Credit card Information should not be Included on this form. Provide credit card i
`Information and authorization on PTO-2038
`
`FEE CALCULATION
`
`1. BASIC FILING, SEARCH, AND EXAMINATION FEES
`FILING FEES
`SEARCH FEES
`Small Entig
`Small Entity
`Fee (5) Fee (5)
`Fee I§I Fee (fl
`
`Application Type
`
`Utility
`
`Design
`
`Plant
`Reissue
`
`Provisional
`
`.
`
`-
`
`300
`
`200
`
`200
`300
`
`200
`
`150
`
`100
`
`100
`150
`
`100
`
`500
`
`100
`
`300
`500
`
`0
`
`250
`
`50
`
`150
`250
`
`0
`
`‘
`
`'
`
`EXAMINATION FEES
`Small Entig
`Fee (§) Fee (fl
`
`200
`
`130
`
`160 ‘
`600
`
`0
`
`100
`
`65
`
`80
`300
`
`0
`
`Fees Paid (fl
`
`500
`
`i
`
`Small Entig
`2. EXCESS CLAIM FEES
`Fee [fl Fee (g)
`'
`Fee Description
`50
`25
`Each claim over 20 or, for Reissues, each claim over 20 and more than in the original patent
`Each independent claim over 3 or, for Reissues, each independent claim more than in the original patent 200
`100
`Multiple dependent claims
`‘
`360
`180
`Fee (fl
`Total Claims
`Extra Claims
`Fee Paid (fl
`$25
`x
`-20 or HP =
`94
`74
`$1.850
`HP = highest number of total claims paid for, if greater than 20
`lndep. Claims
`Extra Claims
`Fee 1§|
`x
`—3 or HP =
`20
`17
`$100
`HP = highest number of independent claims paid for, if greater than 3
`3. APPLICATION SIZE FEE
`
`'
`
`=
`
`Fee Paid (§)
`$1,700
`
`Multiple Dependent Claims
`My my
`
`
`
`If the specification and drawings exceed 100 sheets of paper, the application size fee due is $250 ($125 for small entity)
`for each additional 50 sheets or fraction thereof. See 35 U.S.C. 41(a)(1)(G) and 37 CFR 1.16(s).
`Total Sheets
`Extra Sheets
`Number of each additional 50 or fraction thereof
`Fee (fl
`(round up to a whole number)
`x
`
`- 100 =
`
`/ 50 =
`
`Fee Paid (fl
`
`=
`
`4. OTHER FEE(S)
`Non-English Specification,
`Other:
`
`BMITTED B
`
`$130 fee (no small entity discount)
`
`‘
`
`Fees Paid (fl
`
`Signature DID! fifgfrfgmeflg 39,496
`Narne (Print/Type) Kent J. To—n
`60458133 v1
`
`650-326-2400
`Telephone
`Date March 31, 2005
`
`Ex. 1019, Page 4
`
`Ex. 1019, Page 4
`
`

`

`Attorney Docket No.: 019152-001112US
`
`CLEAN VERSION OF SUBSTITUTE SPECIFICATION
`
`UNDER 37 CFR 1.125
`
`PATENT APPLICATION
`
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD
`
`Inventor:
`
`William W. Y. Chu, a citizen of The United States, residing at
`1320 Miravalle Avenue
`
`Los Altos, CA 94024
`
`Assignee:
`
`ACQIS Technology, Inc.
`1621 W. El Camino Real
`
`Mountain View, CA 94040
`
`Entity:
`
`Small
`
`TOWNSEND and TOWNSEND and CREW LLP
`
`Two Embarcadero Center, Eighth Floor
`San Francisco, California 94111-3834
`Tel: 650-326-2400
`
`Ex. 1019, Page 5
`
`Ex. 1019, Page 5
`
`

`

`Attorney Docket No.: 019152-001112US
`
`PATENT
`
`CLEAN VERSION OF SUBSTITUTE SPECIFICATION UNDER 37 CFR 1.125
`
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD
`
`CROSS REFERENCE TO RELATED APPLICATIONS
`
`[0001]
`
`The present application claims priority as a continuation of US. nonprovisional
`
`patent application no. 10/772,214, filed February 3, 2004, which is a continuation of US.
`
`nonprovisional patent application no. 09/569,758, filed May 12, 2000 (Now US. patent no.
`
`6,718,415), which claimed priority to US. Provisional Application No. 60/134,122 filed May
`
`14, 1999, commonly assigned, and hereby incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`
`[0002]
`
`The present invention relates to computing devices. More particularly, the present
`
`invention provides a system including a plurality of computer modules that can independently
`
`operate to provide backup capability, dual processing, and the like. Merely by way of
`
`example, the present invention is applied to a modular computing environment for desk top
`
`computers, but it will be recognized that the invention has a much wider range of
`
`applicability. It can be applied to a server as well as other portable or modular computing
`
`applications.
`
`[0003] Many desktop or personal computers, which are commonly termed PCs, have been
`
`around and used for over ten years. The PCs ofien come with state—of—art microprocessors
`
`such as the Intel PentiumTM microprocessor chips. They also include a hard or fixed disk
`
`drive such as memory in the giga—bit range. Additionally, the PCs often include a random
`
`access memory integrated circuit device such as a dynamic random access memory device,
`
`which is commonly termed DRAM. The DRAM devices now provide up to millions of
`
`memory cells (i.e., mega—bit) on a single slice of silicon. PCs also include a high resolution
`
`display such as cathode ray tubes or CRTs. In most cases, the CRTs are at least 15 inches or
`
`17 inches or 20 inches in diameter. High resolution flat panel displays are also used with
`
`PCs.
`
`[0004] Many external or peripheral devices can be used with the PCs. Among others, these
`
`peripheral devices include mass storage devices such as a ZipTM Drive product sold by
`
`Iomega Corporation of Utah. Other storage devices include external hard drives, tape drives,
`
`and others. Additional devices include communication devices such as a modern, which can
`
`10
`
`15
`
`20
`
`25
`
`30
`
`Ex. 1019, Page 6
`
`Ex. 1019, Page 6
`
`

`

`be used to link the PC to a wide area network of computers such as the Internet.
`
`Furthermore, the PC can include output devices such as a printer and other output means.
`
`Moreover, the PC can include special audio output devices such as speakers the like.
`
`[0005]
`
`PCs also have easy to use keyboards, mouse input devices, and the like. The
`
`keyboard is generally configured similar to a typewriter format. The keyboard also has the
`
`length and width for easily inputting information by way of keys to the computer. The mouse
`
`also has a sufficient size and shape to easily move a curser on the display from one location
`
`to another location.
`
`[0006] Other types of computing devices include portable computing devices such as
`
`10
`
`"laptop" computers and the like. Although somewhat successful, laptop computers have
`
`many limitations. These computing devices have poor display technology. In fact, these
`
`devices ofien have a smaller flat panel display that has poor viewing characteristics.
`
`Additionally, these devices also have poor input devices such as smaller keyboards and the
`
`like. Furthermore, these devices have limited common platforms to transfer information to
`
`15
`
`and from these devices and other devices such as PCs.
`
`[0007] Up to now, there has been little common ground between these platforms including
`
`the PCs and laptops in terms of upgrading, ease-of—use, cost, performance, and the like.
`
`Many differences between these platforms, probably somewhat intentional, has benefited
`
`computer manufacturers at the cost of consumers. A drawback to having two separate
`
`computers is that the user must often purchase both the desktop and laptop to have "total"
`
`computing power, where the desktop serves as a "regular" computer and the laptop serves as
`
`a "portable" computer. Purchasing both computers is often costly and runs "thousands" of
`
`dollars. The user also wastes a significant amount of time transferring software and data
`
`between the two types of computers. For example, the user must often couple the portable
`
`computer to a local area network (i.e., LAN), to a serial port with a modern and then
`
`manually transfer over files and data between the desktop and the portable computer.
`
`Alternatively, the user often must use floppy disks to "zip" up files and programs that exceed
`
`the storage capacity of conventional floppy disks, and transfer the floppy disk data manually.
`
`[0008] Another drawback with the current model of separate portable and desktop
`
`computer is that the user has to spend money to buy components and peripherals the are
`
`duplicated in at least one of these computers. For example, both the desktop and portable
`
`computers typically include hard disk drives, floppy drives, CD—ROMs, computer memory,
`
`20
`
`25
`
`30
`
`Ex. 1019, Page 7
`
`Ex. 1019, Page 7
`
`

`

`host processors, graphics accelerators, and the like. Because program software and
`
`supporting programs generally must be installed upon both hard drives in order for the user to
`
`operate programs on the road and in the office, hard disk space is often wasted.
`
`[0009] One approach to reduce some of these drawbacks has been the use of a docking
`
`station with a portable computer. Here, the user has the portable computer for "on the road"
`
`use and a docking station that houses the portable computer for office use.
`
`[0010]
`
`Similar to separate desktop and portable computers, there is no commonality
`
`between two desktop computers. To date, most personal computers are constructed with a
`
`single motherboard that provides connection for CPU and other components in the computer.
`
`Dual CPU systems have been available through Intel’s slot 1 architecture. For example, two
`
`Pentium II cartridges can be plugged into two “slot 1” card slots on a motherboard to form a
`
`Dual-processor system. The two CPU’s share a common host bus that connects to the rest of
`
`the system, e.g. main memory, hard disk drive, graphics subsystem, and others. Dual CPU
`
`systems have the advantage of increased CPU performance for the whole system. Adding a
`
`CPU cartridge requires no change in operating systems and application software. However,
`
`dual CPU systems may suffer limited perfomiance improvement if memory or disk drive
`
`bandwidth becomes the limiting factor. Also, dual CPU systems have to time-share the
`
`processing unit in running multiple applications. CPU performance improvement efficiency
`
`also depends on software coding structure. Dual CPU systems provide no hardware
`
`redundancy to help fault tolerance. In running multiple applications, memory and disk drive
`
`data throughput will become the limiting factor in improving performance with multi-
`
`processor systems.
`
`[0011]
`
`The present invention generally relates to computer interfaces. More specifically,
`
`the present invention relates to an interface channel that interfaces two computer interface
`
`buses that operate under protocols that are different from that used by the interface channel.
`
`[0012]
`
`Interfaces coupling two independent computer buses are well known in the art. A
`
`block diagram of a computer system utilizing such a prior art interface is shown in Fig. 5. In
`
`Fig. 5, a primary peripheral component interconnect (PCI) bus 505 of a notebook PC 500 is
`
`coupled to a secondary PCI bus 555 in a docking system 550 (also referred to as docking
`
`station 550) through high pin count connectors 501 and 502, which are normally mating
`
`connectors. The high pin count connectors 501 and 502 contain a sufficiently large number
`
`of pins so as to carry PCI bus signals between the two PCI buses without any translation.
`
`10
`
`15
`
`20
`
`25
`
`3O
`
`Ex. 1019, Page 8
`
`Ex. 1019, Page 8
`
`

`

`The main purpose for interfacing the two independent PCI buses is to allow transactions to
`
`occur between a master on one PCI bus and a target on the other PCI bus. The interface
`
`between these two independent PCI buses additionally includes an optional PCI to PCI bridge
`
`560, located in the docking station 550, to expand the add on capability in docking station
`
`550. The bridge 560 creates a new bus number for devices behind the bridge 560 so that they
`
`are not on the same bus number as other devices in the system thus increasing the add on
`
`capability in the docking station 550.
`
`[0013] An interface such as that shown in Fig. 5 provides an adequate interface between the
`
`primary and secondary PCI buses. However, the interface is limited in a number of ways.
`
`The interface transfers signals between the primary and secondary PCI buses using the
`
`protocols of a PCI bus. Consequently, the interface is subject to the limitations under which
`
`PCI buses operate. One such limitation is the fact that PCI buses are not cable friendly. The
`
`cable friendliness of the interface was not a major concern in the prior art. However, in the
`
`context of the computer system of the present invention, which is described in the present
`
`inventor's (William W.Y. Chu's) application for "Personal Computer Peripheral Console With
`
`Attached Computer Module" filed concurrently with the present application on Sep. 8, 1998
`
`and incorporated herein by reference, a cable fi’iendly interface is desired for interfacing an
`
`attached computer module (ACM) and a peripheral console of the present invention.
`
`Furthermore, as a result of operating by PCI protocols, the prior art interface includes a very
`
`large number of signal channels with a corresponding large number of conductive lines (and a
`
`similarly large number of pins in the connectors of the interface) that are commensurate in
`
`number with the number of signal lines in the PCI buses which it interfaces. One
`
`disadvantage of an interface having a relatively large number of conductive lines and pins is
`
`that it costs more than one that uses a fewer number of conductive lines and pins.
`
`Additionally, an interface having a large number of conductive lines is bulkier and more
`
`cumbersome to handle. Finally, a relatively large number of signal channels in the interface
`
`renders the option of using differential voltage signals less viable because a differential
`
`voltage signal method would require duplicating a large number of signal lines.
`
`It is
`
`desirable to use a low voltage differential signal (LVDS) channel in the computer system of
`
`the present invention because an LVDS channel is more cable friendly, faster, consumes less
`
`power, and generates less noise, including electromagnetic interferences (EMI), than a PCI
`
`channel. The term LVDS is herein used to generically refer to low voltage differential
`
`signals and is not intended to be limited to any particular type of LVDS technology.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`Ex. 1019, Page 9
`
`Ex. 1019, Page 9
`
`

`

`[0014]
`
`Thus, what is needed are computer systems that can have multiple computer
`
`modules. Each computer module has dedicated memory and disk drive, and can operate
`
`independently.
`
`BRIEF SUMMARY OF THE INVENTION
`
`[0015] According to the present invention, a technique including a method and device for
`
`multi—module computing is provided. In an exemplary embodiment, the present invention
`
`provides a system including a plurality of computer modules that can independently operate
`
`to provide backup capability, dual processing, and the like.
`
`[0016]
`
`In a specific embodiment, the present invention provides a computer system for
`
`multi-processing purposes. The computer system has a console comprising a first coupling
`
`site and a second coupling site, e.g., computer module bay. Each coupling site comprises a
`
`connector. The console is an enclosure that is capable of housing each coupling site. The
`
`system also has a plurality of computer modules, where each of the computer modules is
`
`coupled to one of the connectors. Each of the computer modules has a processing unit, a
`
`main memory coupled to the processing unit, a graphics controller coupled to the processing
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`unit, and a mass storage device coupled to the processing unit. Each of the computer
`
`modules is substantially similar in design to each other to provide independent processing of
`
`each of the computer modules in the computer system.
`
`[0017]
`
`In an alternative specific embodiment, the present invention provides a multi-
`
`processing computer system. The system has a console comprising a first coupling site and a
`
`second coupling site. Each coupling site comprises a connector. The console is an enclosure
`
`that is capable of housing each coupling site. The system also has a plurality of computer
`
`modules, where each of the computer modules is coupled to one of the connectors. Each of
`
`the computer modules has a processing unit, a main memory coupled to the processing unit, a
`
`graphics controller coupled to the processing unit, a mass storage device coupled to the
`
`processing unit, and a video output coupled to theprocessing unit. Each of the computer
`
`modules is substantially similar in design to each other to provide independent processing of
`
`each of the computer modules in the computer system. A video switch circuit is coupled to
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`each of the computer modules through the video output. The video switch is configured to
`
`switch a video signal from any one of the computer modules to a display.
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`10
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`15
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`20
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`25
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`30
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`Ex. 1019, Page 10
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`Ex. 1019, Page 10
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`

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`[0018] Numerous benefits are achieved using the present invention over previously existing
`
`techniques. In one embodiment, the invention provides improved processing and
`
`maintenance features. The invention can also provide increased CPU performance for the
`
`whole system. The invention also can be implemented without changes in operating system
`
`and application software. The present invention is also implemented using conventional
`
`technologies that can be provided in the present computer system in an easy and efficient
`11181111611
`
`[0019]
`
`In another embodiment, the invention provides at least two users to share the same
`
`modular desktop system. Each user operates on a different computer module. The other
`
`10
`
`peripheral devices, i.e. CDROM, printer, DSL connection, etc. can be shared. This provides
`
`lower system cost, less desktop space and more efficiency. Depending upon the embodiment,
`
`one or more of these benefits can be available. These and other advantages or benefits are
`
`described throughout the present specification and are described more particularly below.
`
`[0020]
`
`In still further embodiments, the present invention provides methods of using
`
`15
`
`multiple computer modules.
`
`[0021]
`
`The present invention encompasses an apparatus for bridging a first computer
`
`interface bus and a second computer interface bus, where each of the first and second
`
`computer interface buses have a number of parallel multiplexed address/data bus lines and
`
`operate at a clock speed in a predetermined clock speed range having a minimum clock speed
`
`and a maximum clock speed. The apparatus comprises an interface channel having a clock
`
`line and a plurality of bit lines for transmitting bits; a first interface controller coupled to the
`
`first computer interface bus and to the interface channel to encode first control signals from
`
`the first computer interface bus into first control bits to be transmitted on the interface
`
`channel and to decode second control bits received from the interface channel into second
`
`control signals to be transmitted to the first computer interface bus; and a second interface
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`controller coupled to the interface channel and the second computer interface bus to decode
`
`the first control bits from the interface channel into third control signals to be transmitted on
`
`the second computer interface bus and to encode fourth control signals from the second
`
`computer interface bus into the second control bits to be transmitted on the interface channel.
`
`[0022]
`
`In one embodiment, the first and second interface controllers comprise a host
`
`interface controller (HIC) and a peripheral interface controller (PIC), respectively, the first
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`25
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`30
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`Ex. 1019, Page 11
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`Ex. 1019, Page 11
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`

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`and second computer interface buses comprise a primary PCI and a secondary PCI bus,
`
`respectively, and the interface channel comprises an LVDS channel.
`
`[0023] The present invention overcomes the aforementioned disadvantages of the prior art
`
`by interfacing two PCI or PCI-like buses using a non-PCI or non-PCI-like channel. In the
`
`present invention, PCI control signals are encoded into control bits and the control bits, rather
`
`than the control signals that they represent, are transmitted on the interface channel. At the
`
`receiving end, the control bits representing control signals are decoded back into PCI control
`
`signals prior to being transmitted to the intended PCI bus.
`
`[0024] The fact that control bits rather than control signals are transmitted on the interface
`
`channel allows using a smaller number of signal channels and a correspondingly small
`
`number of conductive lines in the interface channel than would otherwise be possible. This is
`
`because the control bits can be more easily multiplexed at one end of the interface channel
`
`and recovered at the other end than control signals. This relatively small number of signal
`
`channels used in the interface channel allows using LVDS channels for the interface. As
`
`mentioned above, an LVDS channel is more cable friendly, faster, consumes less power, and
`
`generates less noise than a PCI bus channel, which is used in the prior art to interface two
`
`PCI buses. Therefore, the present invention advantageously uses an LVDS channel for the
`
`hereto unused purpose of interfacing PCI or PCI-like buses. The relatively smaller number of
`
`signal channels in the interface also allows using connectors having smaller pins counts. As
`
`mentioned above an interface having a smaller number of signal channels and, therefore, a
`
`smaller number of conductive lines is less bulky and less expensive than one having a larger
`
`number of signal channels. Similarly, connectors having a smaller number of pins are also
`
`less expensive and less bulky than connectors having a larger number of pins.
`
`[0025]
`
`In one embodiment, the present invention encompasses an apparatus for bridging a
`
`first computer interface bus and a second computer interface bus, in a microprocessor based
`
`computer system where each of the first and second computer interface buses have a number
`
`of parallel multiplexed address/data bus lines and operate at a clock speed in a predetermined
`
`clock speed range having a minimum clock speed and a maximum clock speed. The
`
`apparatus comprises an interface channel having a clock channel and a plurality of bit
`
`channels for transmitting bits; a first interface controller coupled to the first computer
`
`interface bus and to the interface channel to encode first control signals from the first
`
`computer interface bus into first control bits to be transmitted on the interface channel and to
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`20
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`25
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`30
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`Ex. 1019, Page 12
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`Ex. 1019, Page 12
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`

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`decode second control bits received from the interface channel into second control signals to
`
`be transmitted to the first computer interface bus; and a second interface controller coupled to
`
`the interface channel and the second computer interface bus to decode the first control bits
`
`from the interface channel into third control signals to be transmitted on the second computer
`
`5
`
`interface bus and to encode fourth control signals from the second computer interface bus
`
`into the second control bits to be transmitted on the interface channel.
`
`[0026]
`
`In one embodiment, the first and second interface controllers comprise a host
`
`interface controller (HIC) and a peripheral interface controller (PIC), respectively, the first
`
`and second computer interface buses comprise a primary PCI and a secondary PCI bus,
`
`10
`
`respectively, and the interface channel comprises an LVDS channel.
`
`[0027]
`
`In a preferred embodiment, the interface channel has a plurality of serial bit
`
`channels numbering fewer than the number of parallel bus lines in each of the PCI buses and
`
`operates at a clock speed higher than the clock speed at which any of the bus lines operates.
`
`More specifically, the interface channel includes two sets of unidirectional serial bit channels
`
`15
`
`which transmit data in opposite directions such that one set of bit channels transmits serial
`
`bits from the HIC to the PIC while the other set transmits serial bits from the PIC to the HIC.
`
`For each cycle of the PCI clock, each bit channel of the interface channel transmits a packet
`
`of serial bits.
`
`[0028]
`
`The HIC and PIC each include a bus controller to interface with the first and second
`
`20
`
`computer interface buses, respectively, and to manage transactions that occur therewith. The
`
`HIC and PIC also include a translator coupled to the bus controller to encode control signals
`
`from the first and second computer interface buses, respectively, into control bits and to
`
`decode control bits from the interface channel into control signals. Additionally, the HIC and
`
`PIC each include a transmitter and a receiver coupled to the translator. The transmitter
`
`25
`
`converts parallel bits into serial bits and transmits the serial bits to the interface channel. The
`
`receiver receives serial bits from the interface channel and converts them into parallel bits.
`
`[0029] These and other embodiments of the present invention, as well as its advantages and
`
`features, are described in more detail in conjunction with the text below and attached Figs.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
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`30
`
`[0030]
`
`Fig. 1 is a simplified diagram of a computer system according to an embodiment of
`
`the present invention;
`
`Ex. 1019, Page 13
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`Ex. 1019, Page 13
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`

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`[0031]
`
`Fig. 2 is a simplified block diagram of a computer system according to an
`
`alternative embodiment of the present invention;
`
`[0032]
`
`Fig. 3 is a simplified block diagram of a compeer system according to a further
`
`alternative embodiment of the present invention; and
`
`[0033]
`
`Fig. 4 is a simplified flow diagram of a method according to an embodiment of the
`
`present invention.
`
`[0034]
`
`Fig. 5 is a block diagram of a computer system using a prior art interface between a
`
`primary and a secondary PCI bus.
`
`[0035]
`
`Fig. 6 is a block diagram of one embodiment of a computer system using the
`
`10
`
`interface of the present invention.
`
`[0036]
`
`Fig. 7 is a partial block diagram of a computer system using the interface of the
`
`present invention as a bridge between the north and south bridges of the computer system.
`
`[0037]
`
`Fig. 8 is a partial block diagram of a computer system in which the north and south
`
`bridges are integrated with the host and peripheral interface controllers, respectively.
`
`15
`
`[0038]
`
`Fig. 9 is a block diagram of one embodiment of the host interface controller and the
`
`peripheral interface controller of the present invention.
`
`[0039]
`
`Fig. 10 is a detailed block diagram of one embodiment of the host interface
`
`controller of the present invention.
`
`[0040]
`
`Fig. 11 is a detai