United States Patent (19)
`Horan et al.
`
`54) DUAL PURPOSE APPARATUS, METHOD
`AND SYSTEM FOR ACCELERATED
`GRAPHICS PORT AND PERPHERAL
`COMPONENT INTERCONNECT
`
`75 Inventors: Ronald Timothy Horan, Houston;
`Sompong Paul Olarig, Cypress, both
`of TeX.
`ter Corp. Houst
`C
`: C
`73 Assi
`73)
`Signee
`gpaquomputer uorp., Houston,
`
`21 Appl. No.: 853,289
`22 Filed:
`May 9, 1997
`6
`51) Int. Cl. ...................................................... G06F 13/40
`52 U.S. Cl. ..................
`... 395/306; 395/281
`58 Field of Search ..................................... 395/306, 290,
`395/281, 293, 284, 800.32, 800.33, 800.36,
`800.38
`
`56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,717.873 2/1998 Rabe et al. .............................. 395/290
`5,734,847 3/1998 Garbus et al.
`... 395/308
`5,740,381 4/1998 Yen ......................................... 395/293
`
`USOO588997OA
`Patent Number:
`11
`(45) Date of Patent:
`
`5,889,970
`Mar. 30, 1999
`
`6/1998 Young et al. ........................... 395/308
`5,761,458
`5,796,963
`8/1998 Odom ...................................... 395/308
`Primary Examiner Meng-Ai T. An
`ASSistant Examiner Harold J. Kim
`Attorney, Agent, or Firm-Paul N. Katz
`57
`ABSTRACT
`A core logic chip Set is provided in a computer System that
`may be configured either as a bridge between an accelerated
`graphics port (“AGP) bus and host and memory buses, as
`a bridge between an additional peripheral component inter
`connect (“PCI”) bus and the host and memory buses, or as
`a bridge between a primary PCI bus and an additional PCI
`bus. A common bus having provisions for the PCI and AGP
`interface Signals is connected to the core logic chip Set and
`either an AGP or PCI device(s). The core logic chip set also
`has an AGP/PCI arbiter having additional Request (“REQ')
`and Grant (“GNT") signal lines so that more than one PCI
`device may be utilized on the additional PCI bus. Selection
`of the type of bus bridge (AGP or PCI) in the core logic chip
`Set may be made by a hardware signal input, Software during
`computer System configuration or power on Self test
`(“POST). Software configuration may also be determined
`upon detection of either an AGP or PCI device connected to
`the common bus.
`
`39 Claims, 18 Drawing Sheets
`
`
`
`O3
`
`-202
`CPU
`il CPU
`ADDRESS
`DATA
`ofESs | SCUES INTERFACE |
`
`CPU
`
`
`
`207 212
`
`- 218
`AGP REQUEST/
`REPLY QUEUES
`
`;
`
`AGP DATA
`& CONTORL
`
`AGP/PC
`ARBTER
`
`PC DATA
`CONTROL
`
`MEMORY
`INTERFACE
`& CONTROL
`
`HOST/PC
`NTERFACE
`
`CONFIG.
`LOGIC
`PC
`ARBER
`
`Intel Corporation v. ACQIS LLC
`Intel Corp.'s Exhibit 1032
`Ex. 1032, Page 1
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 1 of 18
`
`5,889,970
`
`
`
`
`
`
`
`112
`
`
`
`VIDEO DISPLAY
`
`11 O
`
`CENTRAL
`PROCESSING
`UNIT(S)
`1 O3
`
`1 O2
`
`1 OO
`
`5
`
`1 O4
`
`106
`
`VIDEO
`GRAPHICS
`CONTROLLER
`
`LOCAL FRAME
`BUFFER
`MEMORY
`
`CORE LOGIC
`
`SYSTEM RAM
`
`1 O7
`
`1 O5
`
`122
`
`108
`
`109
`
`
`
`NETWORK
`INTERFACE
`CARD
`
`PC/PC
`BRIDGE
`
`119
`
`124
`
`117
`
`118
`
`PC1/SCSI BUS
`ADAPTER
`
`PC/EISA/ISA
`BRIDGE
`
`PC/IDE
`CONTROLLER
`
`114
`DISK 2 -)-130
`TAPE
`132
`
`116
`14-O
`ROM BIOS 4
`NVRAM
`
`111
`
`113
`
`128
`
`CD ROM
`
`134
`
`120 121
`
`TO FIG 1A
`
`FIGURE 1
`
`Ex. 1032, Page 2
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 2 of 18
`
`5,889,970
`
`TO FIG. A
`
`INPUT/OUTPUT
`CONTROLLER
`
`15O
`
`152
`
`154
`
`
`
`KEYBOARD
`
`144
`
`146
`
`148
`
`FIGURE 1A
`
`Ex. 1032, Page 3
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 3 of 18
`
`5,889,970
`
`CPU
`ADDRESS
`QUEUES
`
`:
`
`AGP REQUEST/L
`210; REPLY QUEUES
`
`MEMORY
`INTERFACE
`& CONTROL
`
`AGP DATA
`& CONTORL
`
`AGP/PC
`ARBITER
`
`PCI DATA
`CONTROL
`
`208
`
`
`
`.
`
`PC/PC
`BRIDGE
`
`| HOST/PC
`INTERFACE
`
`CONFIG.
`LOGIC
`PC
`ARBTER
`
`FIGURE 2
`
`Ex. 1032, Page 4
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 4 of 18
`
`5,889,970
`
`1 O3
`
`
`
`
`
`CPU HOST
`BUS
`INTERFACE
`
`
`
`
`
`AGP/PCI LOGIC
`
`MEMORY
`INTERFACE
`& CONTROL
`
`
`
`
`
`MEM
`AGP/PC
`OUEUE
`AGP/PC
`TO MEM
`QUEUE
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`HOST/PC
`BRIDGE
`
`109
`
`FIGURE 2A
`
`Ex. 1032, Page 5
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 5 of 18
`
`5,889,970
`
`3O6
`
`AGP &c. PC
`
`F
`Fl
`
`F
`
`
`
`
`
`
`
`
`
`
`
`RESERVED
`
`GNO
`GND
`
`VCC3.3
`
`ESERVED
`
`CC3.3
`BA5
`BA2
`
`B STB
`
`SBA7
`
`
`
`KEY
`KEY
`KEY
`KEY
`FIGURE 3A
`
`Ex. 1032, Page 6
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 6 of 18
`
`5,889,970
`
`
`
`CN O
`
`3O4
`
`306
`
`AGP & PC
`
`PCI only
`
`3
`
`KEY
`
`
`
`
`
`
`
`Fl
`D3O
`D31
`D28
`D29
`CC3.3
`CC3.3
`D26
`D27
`D24
`Fl
`D25
`
`D STB1
`
`ESERVED
`
`D22
`
`GND
`GND
`
`Cr H
`?i õ
`
`Ex. 1032, Page 7
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 7 of 18
`
`5,889,970
`
`3O4.
`
`3O2
`AGP
`Pin #| AGP only
`
`i? a on
`
`3O6
`
`AGP 8. PC
`STOPil
`
`PCI only
`
`3.3V PC
`Pin #
`
`47 BVdda3.5
`dido 3.J.
`48 ASPARE
`48 BI
`49 A
`49 B
`50 A
`50 BT
`51 IA
`51 B
`52 AVdda5.3
`52 BVoda3.3
`53 A
`53 BI
`54 AT
`54 B
`55 Al
`55 B |
`56 A
`56 B
`57 A.
`57 B
`58 ATVdd 5.3
`58 Blvdda5.5
`14 A
`RESERVED
`59 A
`59 BAD STBO
`54 A
`AD6
`60 A
`53 B.
`AD7
`6O B
`48 A
`GND
`61 AT
`56 A
`GND
`61 B
`55 IA
`AD4
`62 IA
`55 B
`AD5
`62 B
`57 A.
`AD2
`65 IAI
`56 B
`AD3
`63 B.
`
`
`64 VoddO3.3 H 64 BTVdda3.3 | | |
`65
`ADO
`58 A
`AD 1
`8
`65 B
`A SMB1
`A SMB1
`66 B SMBO
`
`3 38 A
`
`|
`
`4O B
`37 A
`58 B
`43 A
`42 B
`44 A
`44 B
`|
`46 A
`|45 IB
`47 A
`47 B.
`42 A
`46 B
`49 A
`48 B
`52 A
`52 B
`
`
`
`|
`
`PERRil
`
`PAR
`SERRi
`AD 15
`C/BE 1 it
`|
`AD 13
`AD 14
`TAD11
`AD 12
`GND
`| CND
`AD9
`AD 10
`C/BE O#
`AD8
`
`|
`
`|
`
`|
`
`||
`
`
`
`FIGURE 3C
`
`Ex. 1032, Page 8
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 8 of 18
`
`5,889,970
`
`306
`
`408
`
`AGP & PC
`
`PCI only
`| 5 (/) ? H
`
`3
`Pin
`
`
`
`
`
`
`
`
`
`ESERVED
`CY
`
`VCC3.3
`RESERVED
`RESERVED
`
`PRSNT1
`
`RSNT2
`
`ESERVED
`
`ESERVED
`
`RESERVED
`
`CC5.3
`
`3
`VCC3
`AD29
`AD28
`
`AD26
`AD27
`FIGURE 4A
`
`Ex. 1032, Page 9
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 9 of 18
`
`
`
`AGP
`Pin
`
`AGP only
`
`306
`
`408
`
`AGP & PC
`GND
`AD25
`AD24
`VCC3
`
`PCI only
`
`SEL
`
`D22
`
`AD 18
`VCC3
`3
`AD 16
`
`CC3.3
`CC3.3
`
`
`
`VCC3.3
`
`FIGURE 4B
`
`5,889,970
`
`402
`3V PC
`3
`$ ??
`C
`
`§ffffffffffffffffffffffffffffff
`
`Ex. 1032, Page 10
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 10 0f 18
`
`5,889,970
`
`306
`O
`
`408
`
`O2
`4
`
`
`
`57 A
`57 B
`|
`|
`
`C/BE Oil
`R?šis.
`AD8
`AD7
`AD6
`
`|
`
`|VCC3.3
`
`CC3.3
`
`DDR:
`53 B.
`B
`
`
`
`
`
`
`
`FIGURE 4C
`
`Ex. 1032, Page 11
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 11 of 18
`
`5,889,970
`
`AGP
`
`SO6
`
`408
`
`402
`3.3V PC
`
`|
`
`|
`|
`
`|
`|
`
`|
`
`|
`|
`
`|
`
`69
`| GND
`69 B
`AD61
`170 IA
`| AD60
`7O B
`VCC5.3
`71
`AD58
`71 B
`AD59
`72 IA
`| GND
`72 B
`AD57
`73
`EEE AD56
`73 B.
`GND
`
`EH AD54 74
`H AD55
`74 B
`VCC3.3
`HAE-ZE,
`76 A
`AD52
`76 B
`H GND
`77 A
`H AD5O
`|
`|
`| AD51
`77 B.
`|
`|
`| GND
`78 IA
`AD49
`78 IB
`AD48
`79 A
`| VCC3.3
`79 B
`|
`HAES 8A
`AD47
`80 B
`GND
`81 A
`AD45
`81 B
`AD44
`82 A
`GND
`82 B
`AD42
`85 A
`B
`A
`B
`
`|
`
`|
`
`EAECEIA
`B
`CND
`AD38
`86 A
`AD59
`86 B
`GND
`87 A
`AD37
`B
`
`VCC3.5
`ETTE
`AD34
`ETTE
`AD35
`|
`|
`|
`|
`| CND
`H AE:
`AD32
`|
`|
`CND
`FIGURE 4D
`
`|
`
`88 B
`89 A
`89 B
`90 A
`33
`91 A
`91 IB
`
`Ex. 1032, Page 12
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 12 of 18
`
`5,889,970
`
`JO6
`
`408
`
`AGP
`Pin
`
`AGP only
`
`AGP &c. PC
`
`3
`
`
`
`CN OD
`
`PCI only
`RESERVED
`RESERVED
`GND
`RESERVED
`RESERVED
`GND
`
`|<t|E|<|)|<\d|| || || || TITLITTLEIDDILLETTET
`
`FIGURE 4E
`
`Ex. 1032, Page 13
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 13 of 18
`
`5,889,970
`
`P IP
`c
`6
`4
`
`6
`4
`
`
`
`
`
`CENTRAL
`PROCESSING
`UNIT(S)
`1 O3
`
`104.
`
`CORE LOGIC
`
`2O7
`
`RAM
`
`1 O6
`
`1 O5
`
`214
`VCC
`
`a
`P
`
`109
`
`116
`PC/ISA/ESA
`BRIDGE
`
`
`
`
`
`
`
`516
`5O8O
`508b.
`
`514
`
`P.
`
`P.
`
`P.
`
`P
`
`| || || |
`
`512 512 512 512 506 506
`
`
`
`FIGURE 5
`
`Ex. 1032, Page 14
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 14 of 18
`
`5,889,970
`
`s 6OO
`
`CENTRAL
`PROCESSING
`UNIT(S)
`
`1 O3
`
`2O7
`
`1 O5
`
`1 O4
`
`CORE LOGIC
`
`214
`
`VCC
`
`1 O9
`
`116
`
`PC/ISA/ESA
`BRIDGE
`
`
`
`516
`
`514
`
`S
`A
`p.
`p.
`P.
`P.
`C C C C E
`| |
`| | |
`| | |
`| | |
`|
`S
`A
`
`512 512 512 512 506 506
`
`
`
`FIGURE 6
`
`6O2
`
`
`
`
`
`
`
`
`
`Ex. 1032, Page 15
`
`

`

`U.S. Patent
`US. Patent
`
`Mar. 30, 1999
`Mar. 30, 1999
`
`Sheet 15 0f 18
`Sheet 15 0f 18
`
`5,889,970
`5,889,970
`
`
`
`FIGURE7
`
`Ex. 1032, Page 16
`
`Ex. 1032, Page 16
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 16 of 18
`
`5,889,970
`
`8O17
`A
`
`PCI DEVICE A
`
`5O17
`A
`
`... onto
`
`
`
`
`
`
`
`
`
`
`
`AGP/PC
`ARBITER
`
`PC DEVICE B Hist, - - - - - - - - - - - - - - - - - - - - - -
`
`FIGURE 8
`
`
`
`
`
`POWER TO PC
`CONNECTOR(S)
`
`906
`
`9 O2
`
`POWER TO AGP
`CONNECTOR
`
`SYSTEM POWER
`
`w
`V
`v
`
`91 O X
`
`CONTROLLED BY
`AGP/PCI SELECTION
`
`FIGURE 9
`
`Ex. 1032, Page 17
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 17 of 18
`
`5,889,970
`
`508O
`
`508b.
`
`516
`
`1012 1 OO8 1012 1008 M 1014 101 O
`
`1 OO2
`
`FIGURE 1 OA
`
`Ex. 1032, Page 18
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 18 0f 18
`
`5,889,970
`
`1 OO8
`
`1 OO8
`
`1 OO2
`
`1 O1 O
`
`TO 214 INPUT
`
`FIGURE 1 OB
`
`-O 1 OO6
`1 O12
`1 O12
`
`
`
`1 OO2
`
`1 O14
`
`TO 214 INPUT
`
`FIGURE 1 OC
`
`Ex. 1032, Page 19
`
`

`

`1
`DUAL PURPOSE APPARATUS, METHOD
`AND SYSTEM FOR ACCELERATED
`GRAPHICS PORT AND PERPHERAL
`COMPONENT INTERCONNECT
`
`BACKGROUND OF THE INVENTION
`
`Field of the Invention
`The present invention relates to computer Systems using
`a bus bridge(s) to interface a central processor(s), video
`graphics processor, memory and input-output peripherals
`together, and more particularly, in utilizing the same logic
`circuits as a bus bridge for either an accelerated graphics
`port or an additional peripheral component interconnect bus.
`Description of the Related Technology
`Use of computers, especially personal computers, in busi
`neSS and at home is becoming more and more pervasive
`because the computer has become an integral tool of most
`information workers who work in the fields of accounting,
`law, engineering, insurance, Services, Sales and the like.
`Rapid technological improvements in the field of computers
`have opened up many new applications heretofore unavail
`able or too expensive for the use of older technology
`mainframe computers. These personal computers may be
`used as Stand-alone workStations (high end individual per
`Sonal computers) or linked together in a network by a
`“network server” which is also a personal computer which
`may have a few additional features Specific to its purpose in
`the network. The network server may be used to store
`massive amounts of data, and may facilitate interaction of
`the individual workstations connected to the network for
`electronic mail ("E-mail'), document databases, video
`teleconferencing, whiteboarding, integrated enterprise
`calendar, Virtual engineering design and the like. Multiple
`network Servers may also be interconnected by local area
`networks (“LAN”) and wide area networks (“WAN”).
`A significant part of the ever increasing popularity of the
`personal computer, besides its low cost relative to just a few
`years ago, is its ability to run Sophisticated programs and
`perform many useful and new tasks. Personal computers
`today may be easily upgraded with new peripheral devices
`for added flexibility and enhanced performance. A major
`advance in the performance of personal computers (both
`workstation and network servers) has been the implemen
`tation of Sophisticated peripheral devices Such as Video
`graphics adapters, local area network interfaces, SCSI bus
`adapters, full motion video, redundant error checking and
`correcting disk arrays, and the like. These Sophisticated
`peripheral devices are capable of data transfer rates
`approaching the native Speed of the computer System micro
`processor central processing unit (“CPU”). The peripheral
`devices data transfer Speeds are achieved by connecting the
`peripheral devices to the microprocessor(s) and associated
`System random acceSS memory through high Speed expan
`Sion local buses. Most notably, a high Speed expansion local
`bus Standard has emerged that is microprocessor indepen
`dent and has been embraced by a Significant number of
`peripheral hardware manufacturers and Software program
`mers. This high Speed expansion bus Standard is called the
`“Peripheral Component Interconnect” or “PCI” A more
`complete definition of the PCI local bus may be found in the
`PCI Local Bus Specification, revision 2.1; PCI/PCI Bridge
`Specification, revision 1.0; PCI System Design Guide, revi
`sion 1.0; and PCI BIOS Specification, revision 2.1, the
`disclosures of which are hereby incorporated by reference.
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`5,889,970
`
`2
`These PCI specifications are available from the PCI Special
`Interest Group, P.O. Box 14070, Portland, Oreg. 97214.
`A computer System has a plurality of information (data
`and address) buses Such as a hostbus, a memory bus, at least
`one high Speed expansion local bus Such as the PCI bus, and
`other peripheral buses such as the Small Computer System
`Interface (SCSI), Extension to Industry Standard Architec
`ture (EISA), and Industry Standard Architecture (ISA). The
`microprocessor(s) of the computer System communicates
`with main memory and with the peripherals that make up the
`computer System over these various buses. The
`microprocessor(s) communicates to the main memory over
`a hostbus to memory bus bridge. The peripherals, depending
`on their data transfer Speed requirements, are connected to
`the various buses which are connected to the microprocessor
`host bus through bus bridges that detect required actions,
`arbitrate, and translate both data and addresses between the
`various buses.
`Increasingly Sophisticated microprocessors have revolu
`tionized the role of the personal computer by enabling
`complex applications Software to run at mainframe com
`puter Speeds. The latest microprocessors have brought the
`level of technical Sophistication to personal computers that,
`just a few years ago, was available only in mainframe and
`mini-computer Systems. Some representative examples of
`these new microprocessors are the “PENTIUM” and “PEN
`TIUM PRO” (registered trademarks of Intel Corporation).
`Advanced microprocessors are also manufactured by
`Advanced Micro Devices, Cyrix, IBM and Motorola.
`These Sophisticated microprocessors have, in turn, made
`possible running complex application programs using
`advanced three dimensional (“3-D) graphics for computer
`aided drafting and manufacturing, engineering simulations,
`games and the like. Increasingly complex 3-D graphics
`require higher speed access to ever larger amounts of
`graphics data Stored in memory. This memory may be part
`of the Video graphics processor System, but, preferably,
`would be best (lowest cost) if part of the main computer
`System memory. Intel Corporation has proposed a low cost
`but improved 3-D graphics standard called the “Accelerated
`Graphics Port” (AGP) initiative. With AGP 3-D, graphics
`data, in particular textures, may be shifted out of the
`graphics controller local memory to computer System
`memory. The computer System memory is lower in cost than
`the graphics controller local memory and is more easily
`adapted for a multitude of other uses besides Storing graph
`ics data.
`The proposed Intel AGP 3-D graphics standard defines a
`high Speed data pipeline, or “AGP bus,” between the graph
`ics controller and system memory. This AGP bus has suffi
`cient bandwidth for the graphics controller to retrieve tex
`tures from System memory without materially affecting
`computer System performance for other non-graphics opera
`tions. The Intel 3-D graphics Standard is a Specification
`which provides signal, protocol, electrical, and mechanical
`specifications for the AGP bus and devices attached thereto.
`This specification is entitled “Accelerated Graphics Port
`Interface Specification Revision 1.0, dated Jul. 31, 1996,
`the disclosure of which is hereby incorporated by reference.
`The AGP interface specification uses the 66 MHz PCI
`(Revision 2.1) as an operational baseline, with three perfor
`mance enhancements to the PCI Specification which are used
`to optimize the AGP specification for high performance 3-D
`graphics applications. These enhancements are: 1) pipelined
`memory read and write operations, 2) demultiplexing of
`address and data on the AGP bus by use of Sideband Signals,
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`3
`and 3) data transfer rates of 133 MHz for data throughput in
`excess of 500 megabytes per second (“MB/sec.'). The
`remaining AGP specification does not modify the PCI
`Specification, but rather provides a range of graphics
`oriented performance enhancements for use by the 3-D
`graphics hardware and Software designers. The AGPSpeci
`fication is neither meant to replace nor diminish full use of
`the PCI standard in the computer system. The AGP speci
`fication creates an independent and additional high Speed
`local bus for use by 3-D graphics devices Such as a graphics
`controller, wherein the other input-output (“I/O”) devices of
`the computer System may remain on any combination of the
`PCI, SCSI, EISA and ISA buses.
`To functionally enable this AGP 3-D graphics bus, new
`computer System hardware and Software are required. This
`requires new computer System core logic designed to func
`tion as a host bus/memory bus/PCI bus to AGP bus bridge
`meeting the AGP specification, and new Read Only Memory
`Basic Input Output System (“ROM BIOS") and Application
`Programming Interface (“API”) software to make the AGP
`dependent hardware functional in the computer System. The
`computer System core logic must Still meet the PCI Stan
`dards referenced above and facilitate interfacing the PCI
`bus(es) to the remainder of the computer System. This adds
`additional costs to a personal computer System, but is well
`Worth it if 3-D graphics are utilized. Some personal com
`25
`puter uses Such as a network Server do not require 3-D
`graphics, but would greatly benefit from having an addi
`tional PCI bus with multiple PCI card slots for accepting
`additional input-output devices Such as a network interface
`card(s) (“NIC"), PCI/PCI bridge, PCI/SCSI adapter, PCI/
`EISA/ISA bridge, a wide area network digital router, mul
`tiple head graphics, and the like.
`AGP and PCI devices serve different purposes and the
`respective interface cards (e.g., AGP 3-D video controller
`and PCI NIC) are not physically or electrically interchange
`able even though there is Some commonality of Signal
`functions between the AGP and PCI interface specifications.
`While AGP capabilities are very desirable in a personal
`computer utilizing 3-D graphics, it is wasteful and redundant
`for those personal computers not requiring 3-D capabilities.
`The cost/performance (i.e., flexibility of the computer for a
`given price) of a personal computer is of paramount impor
`tance for commercial acceptance in the market place. In
`today's competitive computer industry, technical perfor
`mance alone does not guarantee commercial Success. Tech
`nical performance of any personal computer product must be
`maximized while constantly reducing its manufacturing
`costs. To achieve a high performance to cost ratio, com
`monality of components and high volume of use are key
`factors. Thus, commonality of components Such as logic
`circuits, printed circuit boards, microprocessors, computer
`boxes and power supplies, will drive the costs down for both
`WorkStations and Servers. Also the high end WorkStations
`and network Servers would benefit if one generic model of
`a personal computer could be effectively used in either
`capacity. Further benefits in reducing costs may be realized
`by using common components in portable and desktop
`(consumer and low end business) computers.
`What is needed is an apparatus, method, and System for a
`personal computer that provides a core logic chip Set con
`figurable for either an AGP bus or an additional PCI bus
`without requiring different logic and interface circuits for
`each type of bus.
`OBJECTS OF THE INVENTION
`It is therefore an object of the present invention to provide
`a core logic chip Set configurable for either an AGP bus or
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`an additional PCI bus without requiring different logic and
`interface circuits for each type of bus.
`It is a further object of the present invention to provide,
`in a personal computer System, a core logic chip Set that is
`configurable as a bridge between an AGP bus and host and
`memory buses, or as a bridge between an additional PCI bus
`and the host and memory buses.
`It is a further object of the present invention to provide a
`core logic chip Set that is Selectively configurable to be a
`bridge between an AGP bus and host and memory buses, or
`a bridge between an additional PCI bus and the host and
`memory buses.
`It is a further object of the present invention to provide a
`method and System for programming a core logic chip Set to
`be a bridge between an AGP bus and host and memory
`buses, or a bridge between an additional PCI bus and the
`host and memory buses.
`It is a further object of the present invention to provide an
`apparatus, method and System for detecting whether an AGP
`compliant device or PCI compliant device is connected to a
`common bus that may be Selectively utilized as either an
`AGP bus or an additional PCI bus, respectively, in a personal
`computer System.
`It is another object to use one of the arbiters of the
`multiple use core logic chip Set for arbitration of either an
`AGP device on the AGP bus, or a plurality of PCI devices
`on the additional PCI bus.
`It is yet a further object to provide request and grant lines
`for each PCI card slot and PCI device on the additional PCI
`bus.
`
`SUMMARY OF THE INVENTION
`The above and other objects of the present invention are
`Satisfied, at least in part, by providing in a computer System
`a multiple use core logic chip Set that may be configured
`either as a bridge between an AGP bus and host and memory
`buses, or as a bridge between an additional PCI bus and the
`host and memory buses. A common bus having provisions
`for all of the PCI and AGP interface signals is connected to
`the multiple use core logic chip Set and is adapted for
`connection to either an AGP or PCI device(s). The multiple
`use core logic chip Set of the present invention uses one of
`its arbiters for the single AGP device on the AGP bus or the
`PCI device(s) on the additional PCI bus, and has Request
`(“REQ') and Grant (“GNT") signal lines for each PCI
`device connected to the additional PCI bus.
`Selection of which type of bus bridge (AGP or PCI) the
`core logic of the present invention is to be configured as may
`be directed by a hardware signal input Such as a logic
`Signal(s) input (logic “1” or logic “0”) to a logic input(s) of
`the chip Set, or by Software during computer System con
`figuration or during the computer system Power On Self Test
`(“POST). Software configuration may be determined upon
`detection of either an AGP or PCI device connected to the
`common bus.
`The AGP or PCI device(s) may be embedded on the
`computer System motherboard, or may be on a Separate
`card(s) which plugs into a corresponding card edge
`connector(s) attached to the System motherboard and con
`nected to the common bus. An embodiment of the invention
`contemplates a multiple use core logic chip Set which may
`be one or more integrated circuit devices Such as an Appli
`cation Specific Integrated Circuit (“ASIC), Programmable
`Logic Array (“PLA”) and the like.
`This multiple use core logic chip Set may be used in
`conjunction with a specific use printed circuit motherboard
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`Ex. 1032, Page 21
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`S
`for a workStation (using AGP), personal computer (using
`AGP), portable computer (using AGP), or a network server
`(using additional PCI devices). In this embodiment, the type
`of motherboard may be adapted to apply hardware signal
`inputs to the core logic chip Set for determining the con
`figuration (AGP or additional PCI) thereof Software selec
`tion also may be used in determining the core logic chip Set
`configuration of this specific use printed circuit motherboard
`and is contemplated herein.
`An advantage of the present invention is being able to use
`the Same multiple use core logic chip Set acroSS different
`types of computer products. This feature increases the
`quantity of these chip Sets being manufactured, resulting in
`a corresponding decrease in the cost per chip Set.
`The multiple use core logic chip Set of the present
`invention may be used in conjunction with a multiple use or
`universal printed circuit motherboard having provisions for
`either or both AGP and/or additional PCI bus card edge
`connectors. The multiple use core logic chip Set is connected
`to a common AGP/PCI bus on the universal printed circuit
`motherboard. Either the AGP connector or the PCI
`connector(s) is attached to the motherboard and is connected
`to the common AGP/PCI bus. Alternatively, both AGP and
`PCI connector(s) may populate the universal motherboard
`and connect to the common AGP/PCI bus. Thus, one moth
`erboard and core logic chip Set can Satisfy the requirements
`for a computer System having either an AGP bus and
`primary PCI bus, or primary and secondary (additional) PCI
`buses.
`If an AGP device card is plugged into the AGP connector,
`the computer System can configure the core logic chip Set to
`support the AGP interface standard. If a PCI device card is
`plugged into the PCI connector, the computer System can
`configure the core logic chip Set to Support the PCI interface
`Standard. It is contemplated in the present invention that
`either a AGP compliant card or a PCI complaint card will be
`plugged into its respective motherboard connector, but not
`both at the same time.
`Interlocking of either an AGP or PCI card may be
`accomplished by mechanical or electrical means. In
`addition, the computer system during POST can detect
`whether both an AGP and PCI card has been mistakenly
`plugged into the computer System motherboard and can then
`display an error message to the computer user. Mechanical
`interlocking may be obtained with a bar having notches
`therein, wherein the notched bar is manually slidably posi
`tioned to allow insertion of either an AGP card or PCI
`card(s), but not both, into the appropriate connector(s) on the
`computer System motherboard. This interlocking bar may be
`electrically actuated with a solenoid operable from an AGP/
`PCI jumper on the system motherboard. The computer
`System may remove the power with a Switch(es) to either the
`AGP connector or PCI connector(s) depending on the selec
`tion made by the AGP/PCI jumper. This effectively disables
`the unwanted card so that it does not fatally interfere with
`the operation of the desired card.
`Yet another printed circuit motherboard, according to the
`present invention, may be adapted for only the AGP con
`nector connected to the common bus and multiple use core
`logic chip set. An additional PCI bus interface would be
`implemented with a daughterboard printed circuit riser card
`comprising a PCI connector(s) and a plug edge matching
`and mating with the AGP connector. The daughterboard
`would plug into the AGP connector on the motherboard and
`a PCI device card(s) (e.g., NIC, SCSI and the like) would
`plug into the daughterboard PCI connector(s). An extension
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`connector may also be utilized and is contemplated in the
`present invention. This extension connector is adapted to
`Supply additional Signals required by the 64 bit implemen
`tation of the PCI specification. The daughterboard may also
`have an additional plug edge matching and mating with this
`extension connector.
`The multiple use core logic chip Set used in conjunction
`with the universal motherboards or motherboard/
`daughterboard described above may be configured by Soft
`ware during computer system configuration or at POST. This
`feature of the invention allows a Standard generic computer
`System that may be utilized for either a WorkStation or
`network Server by just plugging in the appropriate peripheral
`card, i.e., AGP compliant video controller or additional PCI
`compliant NIC, respectively. One or more PCI device cards
`plugged into PCI connectors on the additional PCI bus are
`contemplated herein.
`When the computer system is first powered on and POST
`begins, the Startup configuration Software must Scan the PCI
`bus or buses to determine what PCI devices exist and what
`configuration requirements they may have. This process is
`commonly referred to as enumerating, Scaning, walking or
`probing the bus. It may also be referred to as the discovery
`process. The Software program which performs the discov
`ery process may be referred to as the PCI bus enumerator.
`According to the PCI specification, all PCI devices must
`implement a base Set of configuration registers. The PCI
`device may also implement other required or optional con
`figuration registers defined in the PCI specification. The
`AGP Specification also defines configuration registers and
`information to be contained therein for an AGP compliant
`device So as to indicate its capabilities and System require
`ments. The AGP compliant device has PCI compliant reg
`ister acceSS So that during the bus enumeration process, the
`AGP device information is readjust as any other PCI device.
`Once the information for all of the bus devices are so
`determined, the core logic may be configured by the Startup
`Software as either a bridge between the host and memory
`buses and the AGP bus, or as a bridge between the host and
`memory buses and an additional PCI bus. It is also contem
`plated that the core logic may be configured as a fully
`functional PCI-to-PCI bridge between the primary PCI bus
`and the additional PCI bus.
`An advantage of the present invention is that Software
`may determine at POST whether the AGP or additional PCI
`buS is to be Supported by the core logic chip Set. This feature
`makes the computer System easily converted in the field
`and/or in the factory (build to order) between a workstation
`or network server by just plugging in the desired AGP or PCI
`device card(s) and loading the appropriate operating Soft
`
`WC.
`Other and further objects, features and advantages will be
`apparent from the following description of presently pre
`ferred embodiments of the invention, given for the purpose
`of disclosure and taken in conjunction with the accompa
`nying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIGS. 1 and 1A are a schematic block diagram of a
`computer System;
`FIG. 2 is a schematic functional block diagram of the
`present invention according to the computer System of FIG.
`1;
`FIG. 2A is a data flow b diagram of FIG. 2;
`FIGS. 3A3B and 3C are tables of the AGP signals and the
`corresponding AGP connector pin outs;
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`Ex. 1032, Page 22
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`7
`FIGS. 4A,4B,4C and 4D,4E are tables of the PCI signals
`and the corresponding PCI connector pin outs;
`FIG. 5 is a schematic plan view of a computer system
`motherboard, according to the present invention;
`FIG. 6 is a schematic plan view of another computer
`System motherboard, according to the present invention;
`FIG. 7 is a schematic elevational view of a plug-in
`daughterboard with PCI connectors thereon, according to
`the present invention;
`FIG. 8 is a Schematic block wiring diagram of a portion
`of the embodiment of the present invention according to
`FIG. 5;
`FIG. 9 is a Schematic diagram of a power Switch accord
`ing an embodiment of the present invention;
`FIG. 10A is a plan view of a portion of the motherboard
`illustrated in FIG. 5 illustrating a card interlock according an
`embodiment of the present invention; and
`FIGS. 10B and 10C are schematic elevational views of the
`card interlock of FIG. 10A.
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`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`The present invention is an apparatus, method and System
`for providing in a computer System a multiple use core logic
`chip Set capable of implementing either a bridge between the
`host and memory buses and an AGP bus, or a bridge between
`the host and memory buses and an additional PCI bus.
`Another embodiment of the multiple use core logic chip Set
`of the present invention implements either a bridge between
`the host and memory buses and an AGP bus, or a bridge
`between the primary PCI bus and an additional PCI bus.
`Either implementation may be configured by hardware input
`Signals to the multiple use core logic chip Set or by Software
`programming thereof
`The AGP bus was developed to have sufficient data
`bandwidth for a Video controller in a computer System, up to
`532 megabytes per second (“MB/s”), to run increasingly
`complex three dimensional ("3-D) graphics applications
`Such as, for example, games and engineering Simulations.
`Not all computer Systems, however, need the capabilit