Intel Corporation v. ACQIS LLC
`Intel Corp.'s Exhibit 1009
`Ex. 1009, Page 1
`
`

`

`PTO/SBI'14 (11-08)
`Approved for use through 0980/2010. OMB 0651-0032
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it contains a valid OMB control number.
`
`
`
`Attorney Docket Number ACQI-O10/19US 310578-2066
`Application Number
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL CHANNEL
`COMPRISING UNIDIRECTIONAL SERIAL BIT CHANNELS
`
`
`
`Application Data Sheet 37 CFR 1.76
`
`
`
`T't'e °f Invent'on
`
`The application data sheet is part of the provisional or nonprovisional application for which it is being submitted. The following form contains the
`bibliographic data arranged in a format specified by the United States Patent and Trademark Office as outlined in 37 CFR 1.76.
`This document may be completed electronically and submitted to the Office in electronic format using the Electronic Filing System (EFS) or the
`document may be printed and included in a paper filed application.
`
`Secrecy Order 37 CFR 5.2
`
`|:| Portions or all of the application associated with this Application Data Sheet may fall under a Secrecy Order pursuant to
`37 CFR 5.2 (Paper filers only. Applications that fall under Secrecy Order may not be filed electronically.)
`
`
`
`A licant Information:
`
`
`Applicant 1
`
`Applicant Authority @Inventor | OLegal Representative under 35 U.S.C. 117
`IOParty of Interest under 35 U.S.C. 118
`Prefix Given Name
`Middle Name
`Family Name
`Suffix
`
`Residence Information (Select One) @ US Residency 0 Non US Residency 0 Active US Military Service
`
`
`
`
`58249
`
`
`City
`
`Los Altos
`
`StatelProvince
`
`CA
`
`Country of Residence i
`
`US
`
`
`Citizenship under 37 CFR 1.41(b) i
`
`US
`
`Mailing Address of Applicant:
`Address 1
`1320 Miravalle Avenue
`
`Address 2
`
`City
`
`Los Altos
`
`Statel Province
`
`CA
`
`Inventor Information blocks may be
`Inventors Must Be Listed - Additional
`All
`Add
`
`generated within this form by selecting the Add button.
`
`Correspondence Information:
`
`Enter either Customer Number or complete the Correspondence Information section below.
`For further information see 37 CFR 1.33(a).
`
`|:| An Address is being provided for the correspondence Information of this application.
`
`Customer Number
`
`
`
`Email Address Add Email |
`
`
`
`Application Information:
`.
`.
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL
`T't'e °f the Inventm"
`CHANNEL COMPRISING UNIDIRECTIONAL SERIAL BIT CHANNELS
`Attorney DocketNumber— Small Entity Status Claimed
`Application Type
`Nonprovisional
`
`|:|
`
`Subject Matter
`Utility
`Suggested Class (if any)— Sub Class (if any)
`Suggested Technology Center (if any)
`
`Total Number of Drawing Sheets (if any)
`
`Suggested Figure for Publication (if any)
`
`EFS Web 2.2.2
`
`Ex. 1009, Page 2
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`
`
`Ex. 1009, Page 2
`
`

`

`PTO/SBI'14 (11-08)
`Approved for use through 09I'30I'2010. OMB 0651-0032
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it contains a valid OMB control number.
`
` Attorney Docket Number
`ACQI-D10/19US 310578—2066
`
`Application Data Sheet 37 CFR 1.76
`
`Application Number
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL CHANNEL
`
`COMPRISING UNIDIRECTIONAL SERIAL BIT CHANNELS
`
`T't'e °f Invent'on
`
`Publication Information:
`|:| Request Early Publication (Fee required at time of Request 37 CFR 1.219)
`
`Request Not to Publish. I hereby request that the attached application not be published under 35 US.
`Cl C. 122(b) and certify that the invention disclosed in the attached application has not and will not be the subject of
`an application filed in another country, or under a multilateral international agreement, that requires publication at
`eighteen months after filing.
`
`Representative Information:
`
`Representative information should be provided for all practitioners having a power of attorney in the application. Providing
`this information in the Application Data Sheet does not constitute a power of attorney in the application (see 37 CFR 1.32).
`sections
`Enter
`either Customer Number
`or
`complete
`the
`Representative Name
`section
`below.
`If
`both
`are completed the Customer Number will be used for the Representative Information during processing.
`
`Please Select One:
`
`@ Customer Number
`
`
`
`Customer Number
`
`58249
`
`0 US Patent Practitioner 0 Limited Recognition (37 CFR 11.9)
`
`
`
`
`
`
`Domestic Benefit/National Stage Information:
`
`This section allows for the applicant to either claim benefit under 35 U_S_C_ 119(e), 120, 121, or 365(c) or indicate National Stage
`entry from a PCT application. Providing this information in the application data sheet constitutes the specific reference required by
`35 U.S.C. 119(e) or 120, and 37 CFR 1.78(a)(2) or CFR 1.78(a)(4), and need not otherwise be made part of the specification.
`
`Prior Application Status
`
`Pending
`
`Application Number
`
`Prior Application Status
`
`Application Number
`
`12504534
`
`Prior Application Status
`
`Application Number
`
`12077503
`
`Prior Application Status
`
`Application Number
`11166656
`
`Prior Application Status
`
`Application Number
`11097694
`
`Prior Application Status
`
`Continuity Type
`
`Continuation of
`
`Continuity Type
`
`Continuation of
`
`Continuity Type
`
`Continuation of
`
`Continuity Type
`Continuation of
`
`Continuity Type
`Continuation of
`
`
`
`Prior Application Number
`
`Filing Date (YYYY-MM-DD)
`
`12504534
`
`Prior Application Number
`
`12077503
`
`Prior Application Number
`
`11166656
`
`Prior Application Number
`11097694
`
`Prior Application Number
`10772214
`
`
`
`2009-07-16
`
`Filing Date (YYYY-MM-DD)
`
`2008-03-18
`
`Filing Date (YYYY-MM-DD)
`
`2005-06-24
`
`Filing Date (YYYY-MM-DD)
`2005-03-31
`
`Filing Date (YYYY-MM-DD)
`2004-02-03
`
`
`
`
`
`
`
`EFS Web 2.2.2
`
`Ex. 1009, Page 3
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`Ex. 1009, Page 3
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`

`

`
`
`Application Number
`10772214
`
`Continuity Type
`Continuation of
`
`Prior Application Number
`09569758
`
`Filing Date (YYYY-MM-DD)
`2000-05-12
`
`
`Prior Application Status
`
`
`
`
`
`
`
`PTO/SBI14 (11-08)
`Approved for use through 09I'30I'2010. OMB 0651-0032
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it contains a valid OMB control number.
`
` Attorney Docket Number
`ACQI-D10/19US 310578—2066
`
`Application Data Sheet 37 CFR 1.76
`
`Application Number
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL CHANNEL
`
`COMPRISING UNIDIRECTIONAL SERIAL BIT CHANNELS
`
`T't'e °f Invent'on
`
`
`
`Application Number
`
`Continuity Type
`
`Prior Application Number
`
`Filing Date (YYYY-MM-DD)
`
`09569758
`
`non provisional of
`
`60134122
`
`1999-05-14
`
`Additional Domestic Benefit/National Stage Data may be generated within this form
`by selecting the Add button.
`Add
`
`
`Foreign Priority Information:
`
`This section allows for the applicant to claim benefit of foreign priority and to identify any prior foreign application for which priority is
`not claimed. Providing this information in the application data Sheet constitutes the claim for priority as required by 35 U.S.C. 119(b)
`and 37 CFR 1.55(a).
`
`
`Application Number
`
`Country I
`Parent Filing Date (YYYY-MM-DD)
`
`
`Priority Claimed
`
`(9 Yes O No
`
`Additional Foreign Priority Data may be generated within this form by selecting the
`Add button.
`
`Add
`
`Assignee Information:
`Providing this information in the application data sheet does not substitute for compliance with any requirement of pan 3 of Title 37
`of the CFR to have an assignment recorded in the Office.
`
`Assi nee 1
`
`
`If the Assignee is an Organization check here.
`
`Organization Name
`
`ACQIS LLC
`
`Mailing Address Information:
`
`Address 1
`
`Address 2
`
`411 Interchange Street
`
`Email Address
`
`Additional Assignee Data may be generated within this form by selecting the Add
`button.
`
`Add
`
`A signature of the applicant or representative is required in accordance with 37 CFR 1.33 and 10.18. Please see 37
`CFR 1.4(d) for the form of the signature.
`
`Signature
`
`First Name
`
`Signature:
`
`
`EFS Web 2.2.2
`
`Ex. 1009, Page 4
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`
`
`Ex. 1009, Page 4
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`

`

`PTO/SBI14 (11-08)
`Approved for use through 0980/2010. OMB 0651-0032
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it contains a valid OMB control number.
`
`_
`_
`Application Data Sheet 37 CFR 1.76
`
`Attorney Docket Number
`_
`
`ACQI-D10/19US 310578—2066
`
`_ Title of Invention
`
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL CHANNEL
`COMPRISING UNIDIRECTIONAL SERIAL BIT CHANNELS
`
`This collection of information is required by 37 CFR 1.76. The information is required to obtain or retain a benefit by the public which
`is to file (and by the USPTO to process) an application. Confidentiality is governed by 35 U_S_C_ 122 and 37 CFR 1.14. This
`collection is estimated to take 23 minutes to complete, including gathering, preparing, and submitting the completed application data
`sheet form to the USPTO. Time will vary depending upon the individual case. Any comments on the amount of time you require to
`complete this form and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, US. Patent and
`Trademark Office, US. Department of Commerce, PO. Box 1450, Alexandria, VA 22313-1450. DO NOT SEND FEES OR
`COMPLETED FORMS TO THIS ADDRESS. SEND TO: Commissioner for Patents, P.0. Box 1450, Alexandria, VA 22313-1450.
`
`EFS Web 2.2.2
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`Ex. 1009, Page 5
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`Ex. 1009, Page 5
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`

`

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`EFS Web 2.2.2
`
`Ex. 1009, Page
`
`6
`
`Ex. 1009, Page 6
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`

`

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`Ex. 1009, Page 7
`
`

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`Ex. 1009, Page 9
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`
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`
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`
`?O’R: MULTEFLE MODULE COMPUTER SYS'E‘EM AND METE‘IO‘D ENCLUDING
`{NEWERENTIAL SIGNAL CHANNEL CGMEA‘RESENG UNDERECTEQNAL SERIAL
`BET
`
`
`
`Cemmissicmer for P21163313
`PO, Box 14:30
`Alexandria. \A 223 E 3.»! 456
`
`PG‘WER 3y ASSEGNEE
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`AND S"?AT§£MENT {INBER 37 {LER §3.’?3(b}
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`“5hr: Agsigncs 0f the: entim right, PMS, and intarest
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`Ex. 1009, Page 10
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`Ex. 1009, Page 10
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`

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`Ex. 1009, Page 11
`
`Ex. 1009, Page 11
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`

`

`Attorney Docket No. ACQI-010/19US 310578—2066
`
`PATENT
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Application of: William W.Y. Chu
`
`Confirmation NO.Z Unassigned
`
`Application No.1
`
`Unassigned
`
`Group Art Unit:
`
`Unassigned
`
`Filed:
`
`Herewith
`
`Examiner:
`
`Unassigned
`
`Title: MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL
`CHANNEL COMPRISING UNIDIRECTIONAL SERIAL BIT CHANNELS
`
`
`
`Mail Stop: Amendment
`Commissioner for Patents
`
`PO. Box 1450
`
`Alexandria, VA 22313-1450
`
`PRELIMINARY AMENDMENT
`
`Prior to examination of the above-identified application, please amend the subject
`
`application as follows:
`
`Amendments to the Drawings begin on page 2 of this paper.
`
`Amendments to the Title begin on page 3 of this paper.
`
`Amendments to the Specification begin on page 4 of this paper.
`
`Amendments to the Claims begin on page 6 of this paper.
`
`Remarks/Arguments begin on page 15 of this paper.
`
`The Director is hereby authorized to charge any appropriate fees under 37‘ CPR. §§ l .16,
`
`1.17, and 1.21 that may be required by this paper, and to credit any overpayment, to Deposit
`
`Account No. 50—1283.
`
`933063 Vl/HN
`
`Ex. 1009, Page 12
`
`Ex. 1009, Page 12
`
`

`

`Atty. Docket NO. ACQI~010/19US 310578—2066
`Page 2
`
`IN THE DRAWINGS
`
`Attaclmnent: New Sheets FIG. 8A and FIG. 8B
`
`The subject application is amended to specifically include certain figures from US.
`
`Provisional Application No. 60/083,886.
`
`933063 V1/HN
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`Ex. 1009, Page 13
`
`Ex. 1009, Page 13
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`

`

`Atty. DOCket N0. ACQI-010/19US 310578—2066
`Page 3
`
`IN THE TITLE
`
`Please amend the title as follows:
`
`MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL
`
`CHANNEL COMPRISING ENDIREGTIONAI: UNIDIRECTIONAL SERIAL BIT CHANNELS
`
`933063 Vl/HN
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`Ex. 1009, Page 14
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`Ex. 1009, Page 14
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`

`

`Atty. Docket No. ACQl-010/19US 3105782066
`
`Page 4
`
`IN THE SPECIFICATION
`
`Please replace paragraph no. [000]] with the following paragraph.
`
`The amendments to
`
`paragraph no. [0001] are indicated by strikethrough and underlining.
`
`[0001] This application is a continuation of U.S. Application No. 12/504,534 filed July
`
`
`16 2009 which is a continuation of U.S. Application No. 12/077,503 filed March 18, 2008
`
`[Now U.S. Patent No. 7,676,624), which is a continuation of U.S. nonprovisional Application
`No. 11/166,656, filed June 24, 2005 (Now U.S. Patent No. 7,376,779), .which is a continuation
`
`of U.S. nonprovisional Application No. 11/097,694, filed March 31, 2005 (Now U.S. Patent No.
`
`7,363,415), which is a continuation of U.S. nonprovisional Application No. 10/772,214, filed
`
`February 3, 2004 (Now U.S. Patent No. 7,099,981), which is a continuation of U.S.
`
`nonprovisional Application No. 09/569,758,
`
`filed May 12, 2000 (Now U.S. patent no.
`
`6,718,415), and which claimed priority to U.S. Provisional Application No. 60/134,122 filed
`
`May 14, 1999. These applications are hereby incorporated by reference in their entirety.
`
`Please add paragraph nos. [0041.1] and [0041.2] as set forth below immediately after original
`
`paragraph no. [004]]:
`
`[0041.1] Fig. 8A shows an attached computer module with Integrated CPU/NB/Graphics
`
`and Integrated HIC/SB.
`
`[0041.2] Fig. 8B shows an attached computer module with single chip fully integrated:
`
`CPU, Cache, Core Logic, Graphics controller and Interface controller.
`
`Please replace paragraph no.
`
`[0093] with the following paragraph.
`
`The amendments to
`
`paragraph no. [0093] are indicated by strikethrough and underlining.
`
`[0093] In the embodiment shown in Fig. 6, HIC 619 is coupled to an integrated unit 621
`
`that includes a CPU, a cache and a north bridge.
`
`In another embodiment, such as that shown in
`
`Fig. 7, the CPU 705 and north bridge 710 are separate rather than integrated units. In yet another
`
`embodiment, such as that shown in Fig. 8, the HIC and PIC are integrated with the north and
`
`933063 VI/HN
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`Ex. 1009, Page 15
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`Ex. 1009, Page 15
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`

`

`Atty. Docket No. ACQl—010/19US 310578-2066
`
`Page 5
`
`south bridges, respectively, such that integrated HIC and north bridge unit 805 includes an HIC
`
`and a north bridge, while integrated PIC and south bridge unit 810 includes a PIC and a south
`
`bridge. Fig. 8A shows an attached computer module with integrated CPUNB/Graphics 815 and
`
`Integrated HIC/SB 820. Fig. 8B shows an attached computer module with single chip 825 fully
`
`integrated: CPU, Cache, Core Logic, Graphics controller and Interface controller.
`
`933063 vl/HN
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`Ex. 1009, Page 16
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`Ex. 1009, Page 16
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`

`

`Atty. Docket NO. ACQl-OlO/19US 310578-2066
`
`,
`
`Page 6
`
`IN THE CLAIMS
`
`l~43.
`
`(Cancelled)
`
`44.
`
`(New) A computer system comprising:
`
`a processing unit;
`
`a peripheral bridge to communicate serial bits of Peripheral Component Interconnect
`
`(PCI) bus transaction, the peripheral bridge directly coupled to the processing unit;
`
`a low voltage differential signal (LVDS) channel comprising at least two unidirectional,
`
`differential signal pairs to convey data in opposite directions, the LVDS channel extending from
`
`the peripheral bridge to convey the serial bits of PCI bus transaction, the serial bits of PCI bus
`
`transaction comprising PCI address and data bits;
`
`a main memory coupled to the processing unit through the peripheral bridge; and
`
`a peripheral component coupled to the peripheral bridge.
`
`45.
`
`(New) The computer system of claim 44, wherein the peripheral component is coupled to
`
`the peripheral bridge through the LVDS channel.
`
`46.
`
`(New) The computer system of claim 45, wherein the peripheral component is coupled to
`
`the processing unit through the LVDS channel and the peripheral bridge.
`
`47.
`
`(New) The computer system of claim 45, wherein the peripheral component comprises a
`
`serial communication controller.
`
`48.
`
`(New) The computer system of claim 44, further comprising a graphics subsystem
`
`coupled to the processing unit through the peripheral bridge.
`
`49.
`
`(New) The computer system of claim 44, wherein the peripheral bridge comprises a north
`
`bridge.
`
`933063 v1/HN
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`Ex. 1009, Page 17
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`Ex. 1009, Page 17
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`

`

`Atty. Docket No. ACQI-OlO/19US 310578-2066
`
`Page 7
`
`50.
`
`(New) The computer system of claim 49, wherein the peripheral bridge comprises an
`
`interface controller integrated with the north bridge, the interface controller is coupled to the
`
`processing unit without any intervening PCI bus, and the interface controller is configured to
`
`output encoded address and data bits of PCI bus transaction in serial form that are conveyed over
`
`the LVDS channel.
`
`51.
`
`(New) The computer system of claim 44, wherein the serial bits of PCI bus transaction
`
`comprise information to permit decoding to create a PCI bus transaction.
`
`52.
`
`(New) The computer system of claim 44, wherein the LVDS channel comprises a first
`
`plurality of unidirectional, differential signal pairs to convey data in a first direction and a second
`
`plurality of unidirectional, differential signal pairs to convey data in a second, opposite direction.
`
`53.
`
`(New) A computer system comprising:
`
`a computer module insertable into a console for operation,
`
`the computer module
`
`comprising
`
`a processing unit,
`
`an integrated interface controller and bridge unit to output encoded address and
`
`data bits of Peripheral Component Interconnect (PCI) bus transaction in serial
`
`form,
`
`the
`
`integrated interface controller and bridge unit coupled to the processing unit without any
`
`intervening PCI bus,
`
`a low voltage differential signal (LVDS) channel coupled to the integrated
`
`interface controller and bridge unit to convey the encoded address and data bits of PCI bus
`
`transaction in serial form, and
`
`a main memory coupled to the processing unit through the integrated interface
`
`controller and bridge unit.
`
`54.
`
`(New) The computer system of claim 53, further comprising a peripheral component
`
`coupled to the integrated interface controller and bridge unit through the LVDS channel.
`
`933063 Vl/HN
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`Ex. 1009, Page 18
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`Ex. 1009, Page 18
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`

`

`Atty. Docket No. ACQl—OlO/19US 310578—2066
`
`Page 8
`
`55.
`
`(New) The computer system of claim 53, wherein the LVDS channel comprises a first
`
`plurality of unidirectional, differential signal pairs to convey data in a first direction and a second
`
`plurality of unidirectional, differential signal pairs to convey data in a second, opposite direction.
`
`56.
`
`(New) The computer system of claim 53, wherein the integrated interface controller and
`
`bridge unit comprises a north bridge and an interface controller integrated with the north bridge.
`
`57.
`
`(New) The computer system of claim 53, wherein the computer module comprises an
`
`enclosure housing the processing unit, the integrated interface controller and bridge unit, the
`
`LVDS channel, and the main memory.
`
`58.
`
`(New) The computer system of claim 53, further comprising the console, and the console
`
`comprises a power supply to supply power to the computer module upon insertion into the
`
`console.
`
`59.
`
`(New) The computer system of claim 58, wherein the console comprises a coupling site
`
`and a multi-port, serial communication hub controller, and the computer module comprises a
`
`serial communication controller to communicate, via a pointto—point link, with the multi~port,
`
`serial communication hub controller through the COupling site of the console.
`
`60.
`
`(New) A computer system comprising:
`
`a processing unit;
`
`a low voltage differential signal (LVDS) channel comprising at least two unidirectional
`
`serial bit channels to convey data in opposite directions;
`
`a north bridge coupled to the processing unit, the north bridge comprising an interface
`
`controller to transmit and receive serial bits of Peripheral Component Interconnect (PCI) bus
`
`transaction over the LVDS channel;
`
`a main memory coupled to the processing unit through the north bridge; and
`
`a south bridge coupled to the processing unit through the north bridge.
`
`933063 vl/HN
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`Ex. 1009, Page 19
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`Ex. 1009, Page 19
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`

`

`61.
`
`(New) The computer system of claim 60, wherein the south bridge is coupled to the north
`
`bridge through the LVDS channel.
`
`Atty. Docket NO. ACQI~010/19US 310578-2066
`Page 9
`
`62.
`
`(New) The computer system of claim 61, further comprising a peripheral component
`
`coupled to the processing unit through the south bridge, the LVDS channel, and the north bridge.
`
`63.
`
`(New) The computer system of claim 60, wherein the north bridge is directly coupled to
`
`the processing unit.
`
`64.
`
`(New) The computer system of claim 60, wherein the north bridge and the interface
`
`controller are coupled to the processing unit without any intervening PCI bus, and the interface
`
`controller is integrated with the north bridge.
`
`65.
`
`(New) The computer system of claim 60, wherein the serial bits of PCI bus transaction
`
`comprise encoded PCI address and data bits, the LVDS channel extends from the north bridge to
`
`convey the encoded PCI address and data bits, and the LVDS channel comprises a first plurality
`
`of unidirectional, differential signal pairs to convey data in a first direction and a second plurality
`
`of unidirectional, differential signal pairs to convey data in a second, opposite direction.
`
`66.
`
`(New) A computer system comprising:
`
`a processing unit;
`
`a main memory coupled to the processing unit;
`a first
`low voltage differential
`signal
`(LVDS) channel comprising at
`
`least
`
`two
`
`unidirectional serial bit channels to convey data in opposite directions;
`
`a first peripheral bridge coupled to the processing unit without any intervening Peripheral
`
`Component Interconnect (PCI) bus, the first peripheral bridge coupled to the first LVDS channel
`
`to communicate address and data information of PCI bus transaction in serial form over the first
`
`LVDS channel; and
`
`a second peripheral bridge coupled to the first peripheral bridge.
`
`933063 vl/HN
`
`Ex. 1009, Page 20
`
`Ex. 1009, Page 20
`
`

`

`67.
`
`(New) The computer system of claim 66, wherein the main memory is coupled to the
`
`processing unit through the first peripheral bridge.
`
`Atty. Docket No. ACQl-OIO/l9US 310578—2066
`Page 10
`
`68.
`
`(New) The comput