FILE HISTORY
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`us 6,345,330
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`PATENT:
`6,345,330
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`INVENTORS: Chu, William W. Y.
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`TITLE:
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`Communication channel and interface
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`devices for bridging computer interface
`buses
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`APPLICATION
`US1998149882A
`NO:
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`08 SEP 1998 05
`FILED:
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`FEB 2002
`ISSUED:
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`25 JAN 2021
`COMPILED:
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`Intel Corporation v. ACQIS LLC
`Intel Corp.'s Exhibit 1011
`Ex. 1011, Page 1
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`PATENT NUMBER
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`6345330
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`iliiiliiiiiiliiliilliiiiiil
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`FILEDWITHi-D DISK (CFiF).,« E] FICHE
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`(AttachedInpopyket.on right Inside lisp)
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`I” I
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`D b) T 9 term of this patent shall
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`notextend beyond the expiration date
`opus Patent: No.
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`(Assistant Examiner]
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`THOMAS LEE
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`SUPERVISORY PATENT EXAMINER:
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`' TECHNOLOGY CENTER 2100
`I
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`5:91.1- . Qfli
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`EC)The terminal __rnonths- of
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`this patent have been disclaimed. v '-
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`The Inib'rmationdisclosed herein may be restricted Unauthorized disclosure may be prohibited by the United States Code Title 35. Sections 122,181 a
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`Possession outside the US. Patent R- Trademark OillceIs restricted to authorized employeesand contractors only.
`' Form PTO-436A
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`0/91)
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`'malDrawmgqflHSM‘._
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`(FACE)
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`Ex. 1011, Page 2
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`Ex. 1011, Page 2
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`6,345,330
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`COMMUNICATION CHANNEL AND INTERFACE DEVICES FOR
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`BRIDGING COMPUTER INTERFACE BUSES
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`Date Assined
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`i
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`Transaction History
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`TransaFFtion Descri .tion
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`09—14-1998
`Initial Exam Team nn
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`09-18-1998
`IFW Scan & PACR Auto Securit Review
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`09-28-1998
`Notice Mailed--A. .1ication Incom._,1ete--Fi1in
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`12-07-1998
`Inforrnation Disclosure Statement IDS Filed
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`12-07-1998
`Information Disclosure Statement IDS Filed
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`A . .Iication Is Now Com . lete
`12-l0-1998
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`12-11-1998
`A..1ication Dis-atched from OIPE
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`Case Docketed to Examiner in GAU
`03-31—1999
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`05-05-1999
`Preexamination Location Chane
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`11-15~l999
`Information Disclosure Statement (IDS Filed
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`11-15-1999
`Information Disclosure Statement (IDS) Filed
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`Case Docketed to Examiner in GAU
`06-13-2000
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`06-13-2000
`Non-Final Re'ection
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`06—15-2000
`Mail Non—Final Re'ection
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`07—25-2000
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`07—25-2000
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`09-12-2000
`Mail Notice of Informal or Non-Res .onsive Amendment
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`09—12-2000
`Informal or Non—Res . onsive Amendment after Examiner Action
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`09-21—2000
`Date Forwarded to Examiner
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`09-25-2000
`Information Disclosure Statement IDS Filed
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`09-25-2000
`Information Disclosure Statement IDS Filed
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`10-06-2000
`Case Docketed to Examiner in GAU
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`12-16—2000
`Information Disclosure Statement IDS Filed
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`12-16—2000
`Information Disclosure Statement IDS Filed
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`12-18—2000 Restriction/Election Reguirement
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`Mail Restriction Re uirement
`12-19-2000
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`01-17-2001
`Continuin_ Prosecution A .lication - Continuation ACPA
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`01-17—2001
`Mail Ex-ress Abandonment During Examination
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`01-17-2001
`Ex.ress Abandonment durin_ Examination
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`01-17-2001 Workflow — Re uest for CPA - Be in
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`01-26-2001 i Date Forwarded to Examiner
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`03-22-2001 Non-Final Rejection
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`03-23-2001 Mail Non—Final Rejection
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`07-23—2001
`Information Disclosure Statement {IDS} Filed
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`0123-2001
`Information Disclosure Statement {IDSQ Filed
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`07-23-2001
`Res .onse after Non-Final Action
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`‘ 07—23-2001 Reuest for Extension of Time - Granted
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`07—3 1-2001 Date Forwarded to Examiner
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`08—17-2001 Mail Notice of Allowance
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`08-17-2001 Notice of Allowance Data Verification Com leted
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`08-21—2001
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`08-21-2001
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`08-22-2001 Workflow - File Sent to Contractor
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`11-16-2001
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`12-12-2001 Workflow - Drawin_s Matched with File at Contractor
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`12-12-2001
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`12-12-2001
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`A ..1ication Is Considered Read for Issue
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`01-08-2002
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`Ex. 1011, Page 3
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`Ex. 1011, Page 3
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`Issue Notification Mailed
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`02-05-2002 Recordation of Patent Grant Mail ed
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`02-05-2002
`Patent Issue Date Usedin PTA Calculation
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`03-26-2009 Chan:e in Power of Attorne Ma Include Associate POA
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`03-26-2009 Corres-ondence Address Chan;-e
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`05- 14-2009 Chan e in Power of Attome Ma Include Associate POA
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`Ex. 1011, Page 4
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`Ex. 1011, Page 4
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`ATENTAPP "3'
`mummy?‘
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`CQN'IENTS
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`Date received
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`(incl. 0. MM)
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`11.
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`LA‘IJAA 114 4.4M
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`13.:m. “g1."‘
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`”(FRONT)
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`Ex. 1011, Page 5
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`Ex. 1011, Page 5
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`INDEX OF CLAIMS
`vReJected, *
`v AN ...........................L..... Non.-elected
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`= ..........,E.................'..... Allowed
`FT}1.....'...................... lnterferetnc'e
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`Ifmore than 150 claims or 19 actionskr
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`Ex. 1011, Page 6
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`Ex. 1011, Page 6
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`SEARCH NOTES:
`.- (lNCLt’flfilNG'SEABCHSTFIA‘TEGY)
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`Ex. 1011, Page 7
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`Ex. 1011, Page 7
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`USOO6345330B2
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`US 6,345,330 132
`(10) Patent N0.:
`(12) United States Patent
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`(45) Date of Patent:
`*Feb. 5, 2002
`Chu
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`(54) COMMUNICATION CHANNELAND
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`INTERFACE DEVICES FOR BRIDGING
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`COMPUTER INTERFACE BUSES
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`JP
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`(75)
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`Inventor: William W. Y. Chu, Los Altos, CA
`(US)
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`(73) Ass1gnee: egg: 52c?3%30gy’ Inc., Mountain
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`(*) Notice:
`This patent issued on a continued pros-
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`ecution application filed under 37 CFR
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`1.53(d), and is subject to the twenty year
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`a
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`SUbjCCl to any disclaimer, 1116 WITH 0[ this
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`patent is extended or adjusted under 35
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`U.S.C. 154(b) by 0 days.
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`(21) Appl. No.: 09/149,882
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`Sep. 8, 1998
`(22) Filed:
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`(60)
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`(51)
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`Related US. Application Data
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`Provisional application No. 60/083,886, filed on May 1,
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`1998, and provisional application No. 60/092,706, filed on
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`JUI~1491998~
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`Int. Cl.7 ........................... G06F 3/00; G06F 13/12;
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`G06F 13/28‘ G06F 13/00
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`(52) US. Cl‘ ““““““““““““““ 710/65; 710/29; 710/101
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`(58) Fleld 0f Search ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 375/244; 710/29,
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`710/62, 65’ 70’ 71’ 101’ 128, 129’ 69’ 106;
`708/100
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`(56)
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`EP
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`References Cited
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`U’S’ PATENT DOCUMENTS
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`4,700,362 A * 10/1987 Todd et a1.
`................. 375/249
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`4,890,282 A
`12/1989 Lambert et a1.
`~~~~~~~~~~~~~~ 370/79
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`(LISt continued on next page.)
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`FOREIGN PATENT DOCUMENTS
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`0 722 138 A
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`7/1996
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`10/1994
`06 289953 A
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`a e )
`List continued on next
`P g '
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`OTHER PUBLICATIONS
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`Firm—Townsend&
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`BigiEaéOEegrrégconductor, 21152 PCI—to—PCI Bridge Product
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`(List continued on next page.)
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`Primary Examiner—Thomas Lee
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`Assistant Examiner—Chun Cao
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`(74) Attorney,
`Agent,
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`T0WHS€I1C1&CT€W LLP
`ABSTRACT
`(57)
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`The present invention encompasses an apparatus for bridg-
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`ing a first computer interface bus and a second computer
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`interface bus, Where each of the first and second computer
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`interface buses have a number of parallel multiplexed
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`address/data bus lines and operate at a clock speed in a
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`predetermined clock speed range havtng a minimum clock
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`peed and a maxrmum clock speed. The apparatus comprises
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`an interface channel having a clock line and a plurality of bit
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`lines for transmitting bits; a first interface controller coupled
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`to the first computer interface bus and to the interface
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`channel to encode first control signals from the first com-
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`puter interface bus into first control bits to be transmitted on
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`received from the interface channel
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`Sigtpals to bedtransrriitted to theufirst comlpulter infierface lfjus;
`a secon inter ace contro er cou e
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`channel and the second computer interfléice bus to decode the
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`first control bits from the interface channel into third control
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`signals to be transmitted on the second computer interface
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`bus and to encode fourth control signals from the second
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`computer interface bus into the second control bits to be
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`in one embodiment, the first and second interface controllers
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`comprise a host interface controller (HIC) and a peripheral
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`interface controller (PIC), respectively, the first and second
`
`
`
`
`
`
`
`
`computer interface buses comprise a primary PCI and a
`
`
`
`
`
`
`
`secondary PCI bus, respectively, and the interface channel
`
`
`
`comprises an LVDS channel.
`
`
`
`
`15 Claims, 57 Drawing Sheets
`
`530
`
`‘
`Primary PCI Butt
`V
`
`IO Control
`PCI Bus
`1
`
`Controller
`
`
`
`
`
`
`510/
`525
`
`XPBus
`Controller
`"520
`
`
`
`r“— '————— "n",
`XPBUS ~11 ‘‘‘‘‘ .
`é’: PDR[3 orpcm
`5%ch 592w
`W594
`—595 ‘
`FD[3 01%le
`
`F‘stlpheral
`Interface
`
`Controller
`
`PCI Clock
`
`Asynchrnnous
`
`Asynchroncus
`é
`
` l
`
`
`
`
`
`
`
`Controller
`575
`
`
`
` ID
`PCI Eu:
`i
`Controller
`
`Control
`
`
`
`
`PCI Clock
`
`
` Secondary
`PCI
`PCI Bus
`
`Device
`
`580
`
`H051
`Interface
`Controller
`505
`
`555
`
`Ex. 1011, Page 8
`
`Ex. 1011, Page 8
`
`

`

`
`
`US 6,345,330 B2
`
`
`Page 2
`
`US PATENT DOCUMENTS
`
`
`
`
`
`
`......... 714/798
`
`
`
`
`
`
`
`7/1990 Fredericks et a1.
`4,939,735 A *
`
`
`
`
`
`1/1994 Haynes etal-
`5278509 A
`1/1994 Kjkinis
`5,278,730 A
`
`
`
`3/1994 Free
`5,293,497 A
`
`
`
`7/1994 Kjkinis
`5,331,509 A
`
`
`
`
`
`
`
`
`10/1994 Horowitz et 21].
`5,355,391 A
`
`
`
`
`
`10/1995 Kobayashi
`.................. 395/281
`5,463,742 A
`
`
`
`7/1996 Kikinis
`5,539,616 A
`8/1996 Rahamim et al.
`5,550,710 A
`
`
`
`
`
`
`
`
`
`
`11/1996 Dillon et al.
`5,578,940 A
`
`
`
`
`
`2/1997 Klkmls 5’1 a1~
`5:600:800 A
`
`
`
`
`
`2/,1997 “99““ et 3“
`2’606’717 A
`6/1997 Klklnls
`.,640,302 A
`
`
`
`
`
`
`
`
`8/1997 Huynh et a1.
`5,659,773 A
`
`
`
`
`
`9/1997 Dillon et a1_
`5,663,661 A
`
`
`
`10/1997 Kikinis
`5,680,126 A
`
`
`
`
`
`
`
`.............. 395/281
`2/1998 Kikinis et a1.
`5,721,837 A
`
`
`
`
`
`
`
`
`10/1998 13001111118 0t al~
`5,819,050 A
`395/284
`
`
`
`
`
`
`
`
`
`5,826,048 A : 10/1998 Dempsey et al.
`710/129
`
`
`
`
`
`
`
`
`3:223:33 : * 131332 Sigieelfil'm'
`'. 5412/4109
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`.
`. 714/798
`5,907,566 A *
`5/1999 Benson et al.
`
`
`
`
`
`
`
`
`. 708/141
`.
`5,948,047 A
`9/1999 Jenkins et a1.
`
`
`
`
`
`
`
`5,960,213 A *
`9/1999 Wilson .........
`710/2
`
`
`
`
`
`
`
`
`~ 709/100
`5,968,144 A * 10/1999 Walker et a1.
`
`
`
`
`
`
`5,991,844 A * 11/1999 Khosrowpour
`710/129
`
`
`
`
`
`
`
`.............. 708/100
`5,999,952 A
`12/1999 Jenkins et al.
`
`........... 361/687
`
`
`.
`
`~
`
`
`
`6,029,183 A
`
`6,040,792 A *
`
`
`6,052,513 A *
`
`6,216,185 Bl
`
`.............. 708/100
`2/2000 Jenkins et al.
`
`
`
`
`3/2000 Watson et al.
`..
`341/100
`
`
`
`
`
`
`
`4/2000 MacLaren
`395/294
`
`
`
`4/2001 Chu ....................... 710/101
`
`FOREIGN PATENT DOCUMENTS
`
`
`
`W0
`W0
`W0
`
`10/1992
`1/1994
`5/1995
`
`
`
`9218924 A
`
`
`94 00970 A
`
`
`9513640 A
`
`OTHER PUBLICATIONS
`
`
`
`
`
`
`Intel Corporation, Intcl 430TX PCISET: 82439TX System
`
`
`
`
`Controller (MTXC) Architectural Overview (02/97).
`,
`
`
`
`
`
`Intel Corporatlon, Intel 82371AB PCIftoiISA/IDE XCEL—
`
`
`
`
`ERATOR (PIIX4) Architectural Overv1ew (04/97).
`
`
`
`
`
`
`Intel Corporation, Intel 440LX AGPSET: 82443LX PCI
`
`
`
`
`
`A.G.P. Controller (PAC) Advance Information (08/97).
`
`
`
`National Semiconductor, DS90CR215/DS90CR216 General
`
`Description (07/97).
`
`
`
`
`National Semiconductor, DS90CR215 Product Folder.
`
`
`
`
`
`
`Video Electronics Standards Association (VESA), Plug and
`
`
`
`
`
`
`Display/(P&D) Standard, P&D and Digital Transition Mini-
`
`
`
`
`
`mized Differential Signaling (TMDS) Video Transmission
`
`
`
`
`
`
`
`
`
`Overview, Version 1, Revision 0, pp. 1 & 31—34 (1997).
`
`
`
`
`* cited by examiner
`
`Ex. 1011, Page 9
`
`Ex. 1011, Page 9
`
`

`

`
`US. Patent
`
`
`
`200259b.eF
`
`S
`
`
`
`
`
`f01
`
`
`
`U
`
`
`2B033,54
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`S-22_on_
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`M,259m:0
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`$256n.
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`mum_0n_accooww
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`Foo_>®n_
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`:_n_cmfl.h.._
`t2200550_w2300
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`on.€8.30:
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`
`Ex. 1011, Page 10
`
`Ex. 1011, Page 10
`
`
`
`

`

`
`US. Patent
`
`
`
`Feb. 5, 2002
`
`
`
`
`Sheet2 0f57
`
`
`
`US 6,345,330 B2
`
`com\
`
`ENENmom5
`
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`23:00Ranatcn.as.9xmica—2hwusnEoU“5:033.
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`
`Ex. 1011, Page 11
`
`Ex. 1011, Page 11
`
`
`
`
`

`

`
`
`US. Patent
`
`
`
`
`Feb. 5, 2002
`
`
`
`
`Sheet 3 0f 57
`
`
`
`US 6,345,330 B2
`
`
`Computing System
`
`CPU/NB
`signals
`
`J North Bride 3 Primar PCI Bus
`
`l
`
`Host
`Interface
`Controller
`
`PCl Bus Bridge
`A’ with
`Interface Dev.
`Pair And PBus
`
`on Board 2
`
`Peripheral System
`
`CPU/NB.
`signals L
`
`Peripheral
`Interface
`Controller
`
`Secondar PCI Bus
`
`Device1
`
`
`FIG. 3
`
`Ex. 1011, Page 12
`
`Ex. 1011, Page 12
`
`

`

`
`
`US. Patent
`
`
`
`
`Feb. 5, 2002
`
`
`
`
`Sheet 4 0f 57
`
`
`
`US 6,345,330 B2
`
`
`Computing System
`
`PCI Busl —————————— 4
`
`.
`
`Subsystem
`
`
`
`
`
`Integrated
`Host
`
`Interface
`
`
`North Bridge
`
`Integrated
`Peripheral
`
`Interface
`Cntlr. &
`
`8. Bridge
`
`
`
`I
`
`
`FIG. 4
`
`405
`
`410
`
`Ex. 1011, Page 13
`
`Ex. 1011, Page 13
`
`

`

`
`US. Patent
`
`
`
`
`Feb. 5, 2002
`
`
`
`
`Sheet 5 0f 57
`
`
`
`US 6,345,330 B2
`
`530
`
`Primary PCI Bus
`
`PCI Clock
`
`
`
`
`HOSt
`Interface
`
`
`
`Controller
`
`505
`
`
`
`
`
`
`
`
`
`
`
`
`
`Asynchronous
`
`(i
`
`515
`
`XPBus NNNNN
`
`PD[3::0], PCN I
`
`
`
`
`
`
`
`Peripheral
`Interface
`
`Controller
`
`Asynchronous
`
`
`
`555
`
`Ex. 1011, Page 14
`
`Ex. 1011, Page 14
`
`

`

`
`US. Patent
`
`
`
`
`
`
`Feb. 5, 2002
`
`
`
`
`
`Sheet 6 0f 57
`
`
`
`US 6,345,330 B2
`
`Fla sh Memory
`
`8105/
`
`Configuration
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Host
`PCI
`
`Bus
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`XPBus
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`AD[31:20] out
`
`
`
`
`Serial
`Parallel to
`Convener
`
`I ' I 0
`
`
`
`
`
`
`
`PCN
`
`
`
`
`
`
`
`Convener I
`
`
`
`RESET#
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Serial to Parallel
`
`
`Converter
`
`PCNR
`
`
`
`
`
`
`
`Control
`
`Decoder &
`
`Separate
`
`Data Path
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`RDNVR
`Control
`
`
`
`
`
`
`
`
`‘
`
`
`
`
`
`CPU CNTL
`
`& GPIO
`
`
`Latch/Driver
`
`
`
`
`
`RESET#S
`
`
`North
`
`Bridge
`
`
`Encoder &
`MergeData Path
`
`........
`
`
`
`
`
`
`
`
`
`
`. g .
`
`um
`
`Serial lo
`
`Parallel
`
`
`
`
`
`
`
`
`
`
`
`________________________
`
`
`
`
`
`Graphics
`
`Controller
`
`
`
`
`
`Video Port Data [02:15]
`
`Video Port Control
`
`
`
`
`Serial to
`
`Parallel
`Convener
`
`
`...............
`
`
`X‘
`
`..--....--....-..
`
`aI .
`
`
`FIG. 6
`
`Ex. 1011, Page 15
`
`Ex. 1011, Page 15
`
`

`

`
`
`US. Patent
`
`
`
`Feb. 5, 2002
`
`
`
`
`Sheet 7 0f 57
`
`
`
`US 6,345,330 B2
`
`
`
`EoEEoo25.0“.East".0.:Bmammx
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`Ex. 1011, Page 16
`
`
`
`
`
`
`
`Ex. 1011, Page 16
`
`
`
`
`
`

`

`
`
`US. Patent
`
`
`
`Feb. 5, 2002
`
`
`
`
`Sheet 8 0f 57
`
`
`
`US 6,345,330 B2
`
`
`8:035;gg25.8SE:0.:o.25%
`
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`Ex. 1011, Page 17
`
`Ex. 1011, Page 17
`
`
`
`

`

`
`US. Patent
`
`
`
`Feb. 5, 2002
`
`
`
`
`Sheet 9 0f 57
`
`
`
`US 6,345,330 B2
`
`
`
`Primary PCI Bus
`
`
`NW
`
` CIB Ef
`
`
`
`
`
`IRPYQW ‘
`TRDY#
`
`DSEL#
`
`STOW
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`
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`
`
`Cable
`Delay
`
`
`
`
`
`
`
`
`
`
`
`
`
`Ex. 1011, Page 18
`
`Ex. 1011, Page 18
`
`

`

`
`US. Patent
`
`
`
`Feb. 5, 2002
`
`
`
`
`Sheet 10 0f 57
`
`
`
`US 6,345,330 B2
`
`
`
`Primary PCIBus
`
`‘
`
`
`WWW
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`
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`
`
`
`
`
`
`
`
`
`ii
`
`5
`
`
`
`Ex. 1011, Page 19
`
`Ex. 1011, Page 19
`
`€
`

`

`
`US. Patent
`
`
`
`Feb. 5, 2002
`
`
`
`
`Sheet 11 0f 57
`
`
`
`US 6,345,330 B2
`
`
`
`1101
`
`1160
`
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`PC! CLK
`
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`
`
`
`
`
`A 1130
`1135
`Reset Cnll
`
`
`
`
`_ Latch/Driver RESE'W
`
`......................
`
`
`
`Video Part Data [0::15]
`
`
`
`
`
`
`Parallel
`VFD
`
`
`to Serial
`
`
`
`
`
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`Video Part Control
`
`
`
`
`
`
`
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`
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`Convener
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`
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`0|
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`
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`Data Path
`
`
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`PCI Bus
`
`Control
`
`
`
`Encoder &
`
`
`
`Merge
`
`
`Data Path
`
`
`
`
`
`
`
`
`
`
`CPU CNTL
`
`8. GPIO
`
`
`South
`Brid .e
`
`Video
`Capture
`CifCUii
`
`Vldeo
`Clock
`
`
`
`
`
`
`
`Ex. 1011, Page 20
`
`Ex. 1011, Page 20
`
`

`

`
`
`US. Patent
`
`
`
`Feb. 5, 2002
`
`
`
`
`Sheet12 0f57
`
`
`
`US 6,345,330 B2
`
`
`
`
`
`
`
`
`
`
`
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`Ex. 1011, Page 21
`
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`
`Ex. 1011, Page 21
`
`
`
`

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`US. Patent
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`Feb.5,2002
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`Sheet13 0f57
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`US 6,345,330 B2
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`Ex. 1011, Page 22
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`US. Patent
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`Feb. 5, 2002
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`Sheet 14 0f 57
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`1400
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`Ex. 1011, Page 23
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`Ex. 1011, Page 23
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`

`

`
`US. Patent
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`
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`Feb. 5, 2002
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`Sheet 15 0f 57
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`US 6,345,330 B2
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`1550
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`Ex. 1011, Page 24
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`Ex. 1011, Page 24
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`

`

`
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`US. Patent
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`Feb. 5, 2002
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`Sheet 16 0f 57
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`US 6,345,330 B2
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`1605
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`1610
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`FIG. 16
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`Ex. 1011, Page 25
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`Ex. 1011, Page 25
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`

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`
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`US. Patent
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`Feb. 5, 2002
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`Sheet 17 0f 57
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`US 6,345,330 B2
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`Ex. 1011, Page 26
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`Ex. 1011, Page 26
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`US. Patent
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`Feb. 5, 2002
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`Sheet 18 0f 57
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`US 6,345,330 B2
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`Ex. 1011, Page 27
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`Ex. 1011, Page 27
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`US. Patent
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`Feb. 5, 2002
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`Sheet 19 0f 57
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`US 6,345,330 B2
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`Ex. 1011, Page 28
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`Ex. 1011, Page 28
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`

`

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`US. Patent
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`Feb. 5, 2002
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`Sheet 20 0f 57
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`US 6,345,330 B2
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`FIG. 20
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`Ex. 1011, Page 29
`
`Ex. 1011, Page 29
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`

`

`
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`US. Patent
`
`
`b.eF
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`025,
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`Ex. 1011, Page 30
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`Ex. 1011, Page 30
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`

`

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`US. Patent
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`Feb. 5, 2002
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`Sheet 22 0f 57
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`US 6,345,330 B2
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`:20
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`Ex. 1011, Page 31
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`Ex. 1011, Page 31
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`
`

`

`
`USJhwm
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`Ex. 1011, Page 32
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`Ex. 1011, Page 32
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`

`

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`US. Patent
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`Feb. 5, 2002
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`Sheet 24 0f 57
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`US 6,345,330 B2
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`Primary PCI Bus
`
`
`
`Host
`
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`
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`Ex. 1011, Page 33
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`Ex. 1011, Page 33
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`

`

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`US. Patent
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`Feb. 5, 2002
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`Sheet 25 0f 57
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`US 6,345,330 B2
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`Flash Memory
`BIOS!
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`Configuration
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`Ex. 1011, Page 34
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`Ex. 1011, Page 34
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`

`

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`US. Patent
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`Feb. 5, 2002
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`Sheet 26 0f 57
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`US 6,345,330 B2
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`2601
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`Ex. 1011, Page 35
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`Ex. 1011, Page 35
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`

`

`
`US. Patent
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`
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`Feb. 5, 2002
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`Sheet 27 0f 57
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`US 6,345,330 B2
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`2710
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`FIG. 27
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`Ex. 1011, Page 36
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`Ex. 1011, Page 36
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`Ex. 1011, Page 37
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`

`

`
`
`US. Patent
`
`
`
`Feb. 5, 2002
`
`
`
`
`Sheet 29 0f 57
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`US 6,345,330 B2
`
`
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`

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`
`
`US. Patent
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`
`
`Feb. 5, 2002
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`Sheet 30 0f 57
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`US 6,345,330 B2
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`Ex. 1011, Page 39
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`Ex. 1011, Page 39
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`

`

`
`
`US. Patent
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`
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`Feb. 5, 2002
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`Sheet 31 0f 57
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`US 6,345,330 B2
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`Ex. 1011, Page 40
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`Ex. 1011, Page 40
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`

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`
`US. Patent
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`Feb. 5, 2002
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`Sheet 32 0f 57
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`US 6,345,330 B2
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`PCK
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`Ex. 1011, Page 41
`
`Ex. 1011, Page 41
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`

`

`
`
`US. Patent
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`Ex. 1011, Page 42
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`

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`
`
`US. Patent
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`
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`Feb. 5, 2002
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`Sheet 34 0f 57
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`US 6,345,330 B2
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`Ex. 1011, Page 43
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`

`

`
`US. Patent
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`Feb. 5, 2002
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`Sheet 35 0f 57
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`US 6,345,330 B2
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`Ex. 1011, Page 44
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`

`

`
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`US. Patent
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`Feb. 5, 2002
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`Sheet 36 0f 57
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`US 6,345,330 B2
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`Ex. 1011, Page 45
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`Ex. 1011, Page 45
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`

`

`
`
`US. Patent
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`
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`Feb. 5, 2002
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`Sheet 37 0f 57
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`US 6,345,330 B2
`
`
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