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`Intel Corporation v. ACQIS LLC
`Intel Corp.'s Exhibit 1012
`Ex. 1012, Page 1
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`

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`Attorney Docket No. ACQI-001/05US 310578-2057
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`Control No. 90/010,816
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`IN THE DRAWINGS
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`Attachment: New Sheets corresponding to FIG. 13 and FIG. 14
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`Ex. 1012, Page 2
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`Ex. 1012, Page 2
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`Attorney Docket No. ACQl-OO1/05US 310578-2057
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`Control No. 90/010,816
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`IN THE SPECIFICATION
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`Please add the following new paragraphs immediately after the paragraphs previously added beginning at col.
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`3, line 40:
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`FIG. 13 is a partial block diagram of a computer system in which the north and south bridges are
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`integrated with the host and peripheral interface controllers, respectively.
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`FIG. 14 is a schematic diagram of the signal lines PCK, PDO to PD3, and PCN.
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`Please add the following new paragraphs immediately after the paragraphs previously added beginning at col.
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`17, line 30:
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`In yet another embodiment, such as that shown in FIG. 13, the HIC and PIC are integrated with the
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`north and south bridges, respectively, such that integrated HIC and north bridge unit 1305 includes an HIC and
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`a north bridge, while integrated PIC and south bridge unit 1310 includes a PIC and a south bridge.
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`FIG. 14 is a schematic diagram of lines PCK, PDO to PD3, and PCN. These lines are unidirectional
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`LVDS lines for transmitting clock signals and bits from the HIC to the PIC. The bits on the PDO to PD3 and the
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`PCN lines are sent synchronously within eveyy clock cycle of the PCK. Another set of lines, namely PCKR,
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`PDRO to PDR3, and PCNR, are used to transmit clock signals and bits from the PIC to HIC. The lines used for
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`transmitting information from the PIC to the HIC have the same structure as those shown in FIG. 14, except
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`that they transmit data in a direction opposite to that in which the lines shown in FIG. 14 transmit data.
`In other
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`words they transmit information from the PIC to the HIC. The bits on the PDRO to PDR3 and the PCNR lines
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`are sent synchronously within evepy clock cycle of the PCKR. Some of the examples of control information that
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`may be sent in the reverse direction, i.e., on PCNR line, include a reguest to switch data bus direction because
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`of a pending operation (such as read data available), a control signal change in the target
`requiring
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`communication in the reverse direction, target busy, and transmission error detected.
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`The XPBus which includes lines PCK, PDO to PD3, PCN, PCKR, PDRO to PDR3, and PCNR, has two
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`sets of unidirectional
`lines transmitting clock signals and bits in opposite directions.
`The first set of
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`unidirectional lines includes PCK, PDO to PD3, and PCN. The second set of unidirectional
`lines includes
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`PCKR, PDRO to PDR3, and PCNR. Each of these unidirectional set of lines is a point-to-point bus with a fixed
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`transmitter and receiver, or in other words a fixed master and slave bus. For the first set of unidirectional lines,
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`the HIC is a fixed transmitter/master whereas the PIC is a fixed receiver/slave.
`For the second set of
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`3
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`Ex. 1012, Page 3
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`Ex. 1012, Page 3
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`Attorney Docket No. ACQl-001/O5US 310578-2057
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`Control No. 90/010,816
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`unidirectional lines the PIC is a fixed transmitter/master whereas the HIC is a fixed receiver/slave. The LVDS
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`lines of XPBus, a cable friendly and remote system l/O bus, transmit fixed length data packets within a clock
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`The XPBus lines, PDO to PD3, PCN, PDRO to PDR3 and PCNR, and the video data and clock lines,
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`VPD and VPCK, are not limited to being LVDS lines, as they may be other forms of bit based lines. For
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`example, in another embodiment, the XPBus lines may be IEEE 1394 lines.
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`It is to be noted that although each of the lines PCK, PDO to PD3, PCN, PCKR, PDRO to PDR3, PCNR,
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`VPCK, and VPD is referred to as a line, in the singular rather than plural, each such line may contain more than
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`one physical line. For example, in the embodiment shown in FIG. 14, each of lines PCK, PDO to PD3 and PCN
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`includes two physical
`lines between each driver and its corresponding receiver. The term line, when not
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`directly preceded by the terms physical or conductive,
`is herein used interchangeably with a signal or bit
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`channel which may consist of one or more physical lines for transmitting a signal.
`In the case of non-differential
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`signal lines, generally only one physical line is used to transmit one signal. However, in the case of differential
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`signal lines, a pair of physical lines is used to transmit one signal. For example, a bit line or bit channel in an
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`LVDS or lEEE 1394 interface consists of a pair of physical lines which together transmit a signal.
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`transmit bit
`A bit based line i.e. a bit line is a line for transmittin serial bits. Bit based lines t
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`packets and use a serial data packet protocol. Examples of bit lines include an LVDS line, an lEEE 1394 line,
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`and a Universal Serial Bus (USB) line.
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`icall
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`Ex. 1012, Page 4
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`Ex. 1012, Page 4
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`Attorney Docket No. ACQl-001/05US 310578—2057
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`Control No. 90/010,816
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`IN THE CLAIMS
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`1-48. (Cancelled)
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`49. New Adetachable com utin module for attachment toa eri heral console for formin afull o erational
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`personal computer system comprising:
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`an enclosure;
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`a CPU having a power supply connection point;
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`memoLy coupled to said CPU;
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`mass storage coupled to said CPU; and
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`interconnection circuitry coupled to said CPU, said interconnection circuitLy connectable to a peripheral
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`console, said interconnection circuitm configured to convey a low-voltage differential signaling (LVDS) bit
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`$19.61!;
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`wherein said power supply connection point of said CPU is uncoupled from any electrical power source
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`having sufficient energy to sustain execution of instructions by said CPU whenever said interconnection
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`circuitm is disconnected from a peripheral console,
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`wherein said interconnection circuitry comprises a LVDS channel comprising two sets of unidirectional,
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`multiple serial bit channels to transmit data in opposite directions,
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`wherein said LVDS channel is configured to convey encoded Peripheral Component lnterconnect bus
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`transaction data.
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`50. (New) The apparatus of claim 49 wherein said encoded Peripheral Component lnterconnect bus transaction
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`data comprises 10 bit packets.
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`51-55. (Cancelled)
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`56. New Adetachable com utin module for attachment toa eri heral console forformin afull o erational
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`personal computer system comprising:
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`a CPU;
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`memogy coupled to said CPU;
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`mass storage coupled to said CPU;
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`Ex. 1012, Page 5
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`Ex. 1012, Page 5
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`Attorney Docket No. ACQl-OOi/05US 310578-2057
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`Control No. 90/010,816
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`a communication channel coupled to said CPU and configured to convey a low-voltage differential
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`signaling (LVDS) bit stream;
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`interconnection circuitry coupled to said CPU, said interconnection circuitry connectable to a peripheral
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`console; and
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`power supply circuitry having a stored energy capaciy no greater than the energy required to power
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`said CPU, memory, and mass storage for 30 minutes of operation at the maximum rated speed of the CPU,
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`wherein said communication channel comprises a first unidirectional, serial bit channel and a second
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`unidirectional, serial bit channel, and said first unidirectional, serial bit channel and said second unidirectional,
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`serial bit channel are configured to transmit data in opposite directions,
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`wherein said communication channel comprises multiple pairs of unidirectional, serial bit channels to
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`transmit data in opposite directions,
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`wherein said communication channel is configured to convey an encoded serial bit stream of Peripheral
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`Component lnterconnect bus transaction.
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`57. New The a
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`"data bits.
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`aratus of claim 56 wherein said encoded serial bit stream com rises encoded address and
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`is cou led to said communication
`aratus of claim 56 wherein said interconnection circuit
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`channel to encode Peripheral Component lnterconnect bus transaction data as said encoded serial bit stream.
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`com rises said communication
`aratus of claim 56 wherein said interconnection circuit
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`channel to convey said encoded serial bit stream between said computing module and said peripheral console.
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`60-69. (Cancelled)
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`70. (New) A personal computer system wherein the core computing power and environment for a computer
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`user can be readily separated and transported from the remaining computer system components comprising:
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`(at a detachable computing module including
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`a CPU having a power supply connection point;
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`memory coupled to said CPU;
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`mass storage coupled to said CPU; and
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`Ex. 1012, Page 6
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`Ex. 1012, Page 6
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`b a eri heral console com risin a owersu
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`Attorney Docket No. ACQl-001/05US 310578-2057
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`Control No. 90/010,816
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`(c) interconnection circuitry coupled to said computing module and to said peripheral console for
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`conveying electrical power and signals between said computing module and said peripheral console;
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`wherein said power supply connection point of said CPU is uncoupled from any electrical power source
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`having sufficient energy to sustain execution of instructions by said CPU whenever said computing module is
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`disconnected from said peripheral console,
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`wherein said eri heral console further com rises a low-volta e differential si nalin
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`LVDS channel
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`comprising two sets of unidirectional, multiple serial bit channels to transmit encoded Peripheral Component
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`Interconnect bus transaction data in opposite directions.
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`71. (New) The apparatus of claim 70 wherein said encoded Peripheral Component Interconnect bus transaction
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`data comprises 10 bit packets.
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`72-74. (Cancelled)
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`75. (New) A personal computer system wherein the core computing power and environment for a computer
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`power supply circuitry having a stored energy capacity no greater than the energy reguired to
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`power said CPU, memory, and mass storage for 30 minutes of operation at the maximum rated speed of the
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`b a eri heral console com risin a owersu
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`interconnection circuitgr coupled to said computing module and to said peripheral console for
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`conveying electrical power and signals between said computing module and said peripheral console,
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`wherein said eri heral console further com rises a low-volta e differential si nalin
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`comprising multiple pairs of unidirectional, serial bit channels to transmit data in opposite directions,
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`wherein said LVDS channel is configured to communicate an encoded serial bit stream of Peripheral
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`Component Interconnect bus transaction.
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`Ex. 1012, Page 7
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`Ex. 1012, Page 7
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`Attorney Docket No. ACQi-001/05US 310578-2057
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`Control No. 90/010,816
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`76. (New) The apparatus of claim 75 wherein said interconnection circuitpy is coupled to said LVDS channel to
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`encode Peripheral Component Interconnect bus transaction data as said encoded serial bit stream.
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`77-85. (Cancelled)
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`aratus of claim 49 further com risin
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`86. New The a
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`an inte rated interface controller and north brid e unit
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`interconnect bus transaction data, said integrated
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`interface controller and north bridge unit is coupled to said CPU without any intervening Peripheral Component
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`interconnect bus, and said LVDS channel directly extends from said integrated interface controller and north
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`bridge unit to convey said encoded Peripheral Component Interconnect bus transaction data.
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`corres onds to a main memo
`aratus of claim 86 wherein said memo
`87. New The a
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`said CPU through said integrated interface controller and north bridge unit.
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`88. (New) The apparatus of claim 86 wherein said encoded Peripheral Component interconnect bus transaction
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`data comprises address and data bits of Peripheral Component interconnect bus transaction in serial form.
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`89.
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`(New) The apparatus of claim 88 wherein said integrated interface controller and north bridge unit
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`comprises a north bridge and an interface controller integrated with said north bridge, said interface controller is
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`interconnect bus, and said interface
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`controller is configured to output said address and data bits of Peripheral Component Interconnect bus
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`transaction in serial form that are conveyed over said LVDS channel.
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`90. New The a
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`aratus of claim 89 wherein said LVDS channel com rises a first
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`differential signal pairs to convey data in a first direction and a second plurality of unidirectional, differential
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`signal pairs to convey data in a second, opposite direction.
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`91. New The a
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`aratus of claim 57 further com risin
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`address and data bits of Peripheral Component interconnect bus transaction over said communication channel,
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`and said peripheral bridge is directly coupled to said CPU.
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`Ex. 1012, Page 8
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`Ex. 1012, Page 8
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`Attorney Docket No. ACQl-001/05US 310578-2057
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`Control No. 90/010,816
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`92. (New) The apparatus of claim 91 wherein said peripheral bridge is coupled to said CPU without any
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`intervening Peripheral Component interconnect bus, and said communication channel directly extends from
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`said peripheral bridge to convey said encoded address and data bits of Peripheral Component Interconnect bus
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`transaction.
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`93. (New) The apparatus of claim 92 wherein said peripheral bridge comprises a north bridge.
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`aratus of claim 93 wherein said eri heral brid e com rises an interface controller inte rated
`94. New The a
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`with said north bridge, said interface controller is coupled to said CPU without any intervening Peripheral
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`Component Interconnect bus, and said interface controller is configured to output said encoded address and
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`data bits of Peripheral Component Interconnect bus transaction in serial form that are conveyed over said
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`95. (New) The apparatus of claim 92 wherein said memory corresponds to a main memopy that is coupled to
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`said CPU through said peripheral bridge.
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`96. (New) The apparatus of claim 70 wherein said encoded Peripheral Component Interconnect bus transaction
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`data comprises information to permit decoding to create a Peripheral Component Interconnect bus transaction.
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`97. (New) The apparatus of claim 70 wherein said LVDS channel corresponds to a first LVDS channel, and said
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`a second LVDS channel comprising a first unidirectional, serial bit channel to transmit data in a first
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`direction and a second unidirectional, serial bit channel to transmit data in a second, opposite direction; and
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`a peripheral bridge coupled to said CPU without any intervening Peripheral Component Interconnect
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`bus, said peripheral bridge comprising an integrated interface controller to communicate, over said second
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`LVDS channel, encoded address and data bits of Peripheral Component Interconnect bus transaction in serial
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`form.
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`98. New The a
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`aratus of claim 97 wherein said inte rated interface controller is confi ured to communicate
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`said encoded address and data bits of Peripheral Component Interconnect bus transaction as 10 bit packets.
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`99. (New) The apparatus of claim 97 wherein said peripheral bridge comprises a north bridge.
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`Ex. 1012, Page 9
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`Ex. 1012, Page 9
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`Attorney Docket No. ACQi-001/05US 310578-2057
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`Control No. 90/010,816
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`100. New The a
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`without any intervening Peripheral Component Interconnect bus.
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`aratus of claim 97 wherein said inte rated interface controller is cou led to said CPU
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`101. New The a
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`aratus of claim 97 wherein said second LVDS channel directl extends from said inte rated
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`102. New The a
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`aratus of claim 97 wherein said memo
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`corres onds to a main memo
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`aratus of claim 75 wherein said LVDS channel corres onds to a first LVDS channel and
`103. New The a
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`said detachable computing module comprises:
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`an integrated interface controller and bridge unit to output encoded address and data bits of Peripheral
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`Component interconnect bus transaction in serial form, said integrated interface controller and bridge unit
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`directly coupled to said CPU; and
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`a second LVDS channel coupled to said integrated interface controller and bridge unit to convey said
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`encoded address and data bits of Peripheral Component interconnect bus transaction in serial form.
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`104. New The a
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`luralit of
`aratus of claim 103 wherein said second LVDS channel com rises a first
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`unidirectional, differential signalpairs to convey data in a first direction and a second plurality of unidirectional,
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`aratus of claim 103 wherein said inte rated interface controller and brid e unit com rises a
`105. New The a
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`north bridge and an interface controller integrated with said north bridge.
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`106. New The a' aratus of claim 103 wherein said inte rated interface controller and brid e unit is cou led to
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`107. {New} The apparatus of claim 106 wherein said second LVDS channel directly extends from said
`Integrated interface controller and bridge unit.
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`10
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`Ex. 1012, Page 10
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`Ex. 1012, Page 10
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`Attorney Docket No. ACQl-001/05US 310578-2057
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`Control No. 90/010,816
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`aratus of claim 107 wherein said memo
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`corres onds to a main memo
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`109. New The a
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`aratus of claim 103 wherein said first LVDS channel is confi ured to cou le to said second
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`LVDS channel.
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`110. New The a
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`aratus of claim 103 wherein said interconnection circuit
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`11
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`Ex. 1012, Page 11
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`Ex. 1012, Page 11
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`Attorney Docket No. ACQI-001/05US 310578-2057
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`Control No. 90/010,816
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`REMARKS
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`I.
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`INTRODUCTION:
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`Claims 49—50, 56-59, 70-71, and 75-76 of US. Patent No. 6,216,185 (the ““185 patent”) were previously
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`subject to reexamination, and currently stand rejected. Patent Owner respectfully traverses the rejections for
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`the reasons set forth below. Claims 49-50, 56—59, 70-71, and 75-76 are unamended by this paper. New claims
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`86-110 are added by this paper.
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`For the reasons set forth below, Patent Owner respectfully submits that claims 49-50, 56-59, 70-71, 75—
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`76, and 86-110 should be deemed patentable.
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`Il.
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`DRAWINGS AND SPECIFICATION:
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`The ‘185 patent incorporates by reference US. Application No. 09/149,882, now issued as US. Patent
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`No. 6,345,330 (the “‘330 patent”).1 By this paper, the ‘185 patent is amended to include additional incorporated
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`material from the ‘330 patent. Specifically, the ‘185 patent is amended to add new FIG. 13 and FIG. 14, as well
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`as accompanying text. The added drawings and text correspond to: (a) FIG. 4 and FIG. 23 of the ‘330 patent;
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`and (b) text of the “330 patent at col. 3, lines 51-53; col. 4, lines 35-36; col. 6, lines 30-35; and col. 15, line 10 to
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`col. 16, line 5. For purposes of consistency, FIG. 4 of the “330 patent and its accompanying reference numbers
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`having the format 4xx (e.g., integrated HIC and north bridge unit 405) are re—Iabeled as FIG. 13 and reference
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`numbers having the format 13xx (e.g., integrated HIC and north bridge unit 1305). Likewise, FIG. 23 of the ‘330
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`patent is re-Iabeled as FIG. 14. Otherwise, Patent Owner respectfully submits that the added drawings and text
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`correspond to the above-noted drawings and text of the ‘330 patent, and that no new matter is added.
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`III.
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`STATUS OF CLAIMS AND SUPPORT FOR CLAIM CHANGES:
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`In accordance with Patent Owner’s response filed on September 27, 2010, original claims 34, 36, 38,
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`40, and 42 were unamended, original claims 7, 14, and 21 were amended, original claims 1-6, 28-33, 35, 37,
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`39, and 41 were cancelled, and new claims 43-85 were added.
`In accordance with Patent Owner’s response
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`filed on May 3, 2011 and resubmission of Patent Owner’s response filed on June 2, 2011, previously added
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`claims 49, 56, 70, and 75 were amended, previously added claims 50, 57—59, 71, and 76 were unamended, and
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`claims 7-27, 34, 36, 38, 40, 42-48, 51-55, 60-69, 72-74, and 77—85 were cancelled.
`In accordance with this
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`1 See “185 patent at col. 1, lines 11-16 (“This application is being filed concurrently with the application of William W. Y. Chu for ‘A
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`Communication Channel and Interface Devices For Bridging Computer Interface Buses’, US. application No. 09/149,882 filed on
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`Sept. 8, 1998 and incorporates the material therein by reference”) and col. 5, line 66 to col. 6, line 4 (“The preferred ACM-to-PCON
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`Interconnection 300 is described in detail in a companion US. patent application, Ser. No. 09/149,882, entitled ‘A Communication
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`Ex. 1012, Page 12
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`Ex. 1012, Page 12
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`Attorney Docket No. ACQI-001/05US 310578-2057
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`Control No. 90/010,816
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`paper, previously added claims 49—50, 56-59, 70-71, and 75-76 are unamended, and new claims 86-110 are
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`added. Although previously added claims 49—50, 56-59, 70-71, and 75-76 are unamended, these claims are
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`designated as “New” to reflect changes vis-a-vis the ‘185 patent.
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`New claim 49 waspreviously amended to be in independent form in accordance with Patent Owner’s
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`response filed on May 3, 2011 and resubmission of Patent Owner’s response filed on June 2, 2011. Claim 49
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`is unamended by this paper.
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`New dependent claim 50 (dependent from claim 49) was previously added by Patent Owner’s response
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`filed on September 27, 2010, and support was set forth therein. Claim 50 is unamended by this paper.
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`New claim 56 was previously amended to be in independent form in accordance with Patent Owner’s
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`response filed on May 3, 2011 and resubmission of Patent Owner’s response filed on June 2, 2011. Claim 56
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`is unamended by this paper.
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`New dependent claims 57-59 (dependent from claim 56) were previously added by Patent Owner’s
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`response filed on September 27, 2010, and support was set forth therein. Claims 57-59 are unamended by this
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`New claim 70 was previously amended to be in independent form in accordance with Patent Owner’s
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`response filed on May 3, 2011 and resubmission of Patent Owner’s response filed on June 2, 2011. Claim 70
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`is unamended by this paper.
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`New dependent claim 71 (dependent from claim 70) was previously added by Patent Owner’s response
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`filed on September 27, 2010, and support was set forth therein. Claim 71 is unamended by this paper.
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`New claim 75 was previously amended to be in independent form in accordance with Patent Owner’s
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`response filed on May 3, 2011 and resubmission of Patent Owner’s response filed on June 2, 2011. Claim 75
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`is unamended by this paper.
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`New dependent claim 76 (dependent from claim 75) was previously added by Patent Owner’s response
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`filed on September 27, 2010, and support was set forth therein. Claim 76 is unamended by this paper.
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`New dependent claim 86 (dependent from claim 49) specifies “an integrated interface controller and
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`north bridge unit to communicate said encoded Peripheral Component Interconnect bus transaction data, said
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`integrated interface controller and north bridge unit is coupled to said CPU without any intervening Peripheral
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`Component Interconnect bus, and said LVDS channel directly extends from said integrated interface controller
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`and north bridge unit
`to convey said encoded Peripheral Component interconnect bus transaction data.”
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`Support for this claim can be found, for example, in the ‘185 patent at FIG. 4; col. 5, line 57 to col. 6, line 13;
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`Channel and Interface Devices for Bridging Computer interface Buses,’ by the same inventor, filed on the same day herewith, and
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`Ex. 1012, Page 13
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`Ex. 1012, Page 13
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`Attorney Docket No. ACQI-001/05US 310578-2057
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`Control No. 90/010,816
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`and col. 6, lines 31-40, as well as in the incorporated ‘330 patent at FIG. 4; FIG. 6; FIG. 23; col. 6, lines 30-35;
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`col. 7, line 28 to col. 10, line 18; and col. 15, line 10 to col. 16, line 5.
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`New dependent claim 87 (dependent from claim 86) specifies that “said memory corresponds to a main
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`memory that is coupled to said CPU through said integrated interface controller and north bridge unit.” Support
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`for this claim can be found, for example, in the ‘185 patent at FIG. 4 and col. 6, lines 31-44, as well as in the
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`incorporated ‘330 patent at FIG. 4 and col. 6, lines 30-35.
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`New dependent claim 88 (dependent
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`Component Interconnect bus transaction data comprises address and data bits of Peripheral Component
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`Interconnect bus transaction in serial form.” Support for this claim can be found, for example, in the ‘185 patent
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`at col. 5, line 57 to col. 6, line 13, as well as in the'incorporated ‘330 patent at col. 7, line 44 to col. 9