Intel Corporation v. ACQIS LLC
`Intel Corp.'s Exhibit 1026
`Ex. 1026, Page 1
`
`

`

`IEEE Standards documents are developed within the Technical Committees of the IEEE Societies and the Standards
`Coordinating Committees of the IEEE Standards Board. Members of the committees serve voluntarily and without
`compensation. They are not necessarily members of the Institute. The standards developed within IEEE represent a
`consensus of the broad expertise on the subject within the Institute as well as those activities outside of IEEE that have
`expressed an interest in participating in the development of the standard.
`
`Use of an IEEE Standard is wholly voluntary. The existence of an IEEE Standard does not imply that there are no other
`ways to produce, test, measure, purchase, market, or provide other goods and services related to the scope of the IEEE
`Standard. Furthermore, the viewpoint expressed at the time a standard is approved and issued is subject to change
`brought about through developments in the state of the art and comments received from users of the standard. Every
`IEEE Standard is subjected to review at least every five years for revision or reaffirmation. When a document is more
`than five years old and has not been reaffirmed, it is reasonable to conclude that its contents, although still of some
`value, do not wholly reflect the present state of the art. Users are cautioned to check to determine that they have the
`latest edition of any IEEE Standard.
`
`Comments for revision of IEEE Standards are welcome from any interested party, regardless of membership affiliation
`with IEEE. Suggestions for changes in documents should be in the form of a proposed change of text, together with
`appropriate supporting comments.
`
`Interpretations: Occasionally questions may arise regarding the meaning of portions of standards as they relate to
`specific applications. When the need for interpretations is brought to the attention of IEEE, the Institute will initiate
`action to prepare appropriate responses. Since IEEE Standards represent a consensus of all concerned interests, it is
`important to ensure that any interpretation has also received the concurrence of a balance of interests. For this reason
`IEEE and the members of its technical committees are not able to provide an instant response to interpretation requests
`except in those cases where the matter has previously received formal consideration.
`
`Comments on standards and requests for interpretations should be addressed to:
`
`Secretary, IEEE Standards Board
`445 Hoes Lane
`PO. Box 1331
`
`Piscataway, NJ 08855-1331
`USA
`
`NOTE — Attention is called to the possibility that implementation ofthis standard may require use of subject matter covered
`by patent rights. By publication of this standard, no position is taken with respect to the existence or validity of any
`patent rights in connection therewith. The IEEE shall not be responsible for identifying all patents for which a
`license may be required by an IEEE standard or for conducting inquiries into the legal validity or scope of those
`
`patents that are brought to its attention.
`
`Authorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute
`of Electrical and Electronics Engineers, Inc., provided that the appropriate fee is paid to Copyright Clearance Center.
`To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service, 222 Rosewood
`Drive, Danvers, MA 01923 USA; (508) 750-8400. Permission to photocopy portions of any individual standard for
`educational classroom use can also be obtained through the Copyright Clearance Center.
`
`ii
`
`Ex. 1026, Page 2
`Authorized licensed use limited to: Reprints Desk. Downloaded on April 28,2021 at 20:15:41 UTC from IEEE Xplore. Restrictions apply.
`
`Ex. 1026, Page 2
`
`

`

`Introduction
`
`[This introduction is not a part of IEEE Std 1596.3-1996, IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable
`Coherent Interface (SCI).]
`
`The demand for more processing power continues to increase, and apparently has no limit. One can usefully saturate
`the resources of any computer by merely specifying a finer mesh or higher resolution for the solution to a physical
`problem such as hydrodynamics or 3-D graphics. This demand leads engineers and scientists in a desperate search for
`more powerful and faster computers.
`
`To economically obtain this kind of computing power, it seems necessary to use a large number of processors
`cooperatively. This cooperation is provided by the Scalable Coherent Interface (SCI), a high-speed packet
`transmission protocol that efficiently provides the functionality of bus-like transactions (read, write, lock, etc.).
`However, the initial physical implementations are based on emitter coupled logic (ECL) signal levels, which consume
`more power than is practical in the low-cost workstation environment. The initial specification’s 1 Gbyte/s bandwidth
`(16-bit data path) may be overly expensive in the workstation environment. It may be more cost effective to use a
`narrower data path of sufficient bandwidth. The combination of a high-speed transmission environment and efficient
`protocols can provide the link for multiple processors to cooperate in a low-cost workstation environment.
`
`The initial developers of this standard came from the Working Group that developed the SCI protocol (IEEE Std
`1596-1992). The ECL signal levels defined for the SCI were effective in getting the standard implemented quickly
`and are practical for high-performance applications. They are less well suited, however, to using SCI in low-cost
`workstations. The obvious low-cost solution is to integrate the transceivers into the controller and implement both
`in CMOS. This integration will satisfy the space and power requirements of the workstation and personal
`computing market.
`
`Eventually, a lower voltage swing will be needed in order to get higher speeds than ECL signal levels can provide. This
`standard can provide the basis for increasing parallel signal switching frequency into the gigahertz range.
`
`Committee Membership
`
`The following is a list of participants in the IEEE Project 1596.3 Working Group. Voting members at the time of
`publication are marked with an asterisk (*).
`
`Romain Agostini
`Duane Anderson
`Andre Bogaerts
`Mike Chastain
`James R. (Bob) Davis
`Stein Gjessing
`James Goodman
`Emil N. Hahn
`
`Stephen Kempainen*, Chair
`David B. Gustavson*, Vice Chair
`
`Craig Hansen
`Mats Hedberg
`David V. James
`Ross Johnson
`Anatol Kaganovich
`Khan Kibria
`Tom Knight
`
`Michael J. Koster
`Ernst Kristiansen
`John Moussouris
`Gary Murdock
`Gurindar Sohi
`William Terrell
`Hans Wiggers
`Danny Yeung
`
`Ex. 1026, Page 3
`Authorized licensed use limited to: Reprints Desk. Downloaded on April 28,2021 at 20:15:41 UTC from IEEE Xplore. Restrictions apply.
`
`iii
`
`Ex. 1026, Page 3
`
`

`

`The following persons were on the balloting committee that approved this document for submission to the IEEE
`Standards Board:
`
`Robert E. Allen
`Knut Alnes
`
`Harry Andreas
`Keith D. Anthony
`Harrison A. Beasley
`Chris Bezirtzoglou
`Janos Biri
`Martin Blake
`
`Andre Bogaerts
`Charles Brill
`Alice Brown
`
`Haakon Ording Bugge
`Andrew M. Cofler
`
`Roger D. Edwards
`Wayne Fischer
`Gordon Force
`Willard Graves
`
`Willard Graves
`John Griffith
`David B. Gustavson
`David V. James
`Kenneth A. Jansen
`Ernst H. Kristianson
`Conrad Laurvick
`Gerald E. Laws
`Roland Marbot
`William C. McDonald
`Chris McFarland
`
`Thanos Mentzelopoulos
`Klaus-Dieter Mueller
`J. D. Nicoud
`Tadahiko Nishimukai
`
`Michael Orlovsky
`
`Granville Ott
`Elwood Parsons
`Mira Pauker
`Brian Ramelson
`
`William Ramsay
`Fred U. Rosenberger
`Frederick E. Sauer
`
`Vilaus G. Singer
`Manu Thapar
`Michael G. Thompson
`Robert C. Tripi
`Tom W. Vrankar
`
`Hans A. Wiggers
`David L. Wright
`Yoshio Yamaguchi
`Oren Yuen
`Janusz Zalewski
`
`When the IEEE Standards Board approved this standard on 21 March 1996, it had the following membership:
`
`Donald C. Loughry, Chair
`Richard J. Holleman, Vice Chair
`Andrew G. Salem, Secretary
`
`Ben C. Johnson
`E.G. “Al” Kiener
`
`Joseph L. Koepfinger*
`Lawrence V. McCall
`
`L. Bruce McClung
`Marco W. Migliaro
`Mary Lou Padgett
`John W. Pope
`Jose R. Ramos
`
`Arthur K. Reilly
`Ronald H. Reimer
`
`Gary S. Robinson
`Ingo Rfisch
`John S. Ryan
`Chee Kiow Tan
`
`Leonard L, Tripp
`Howard L. Wolfrnan
`
`Gilles A. Baril
`
`Clyde R. Camp
`Joseph A. Cannatelli
`Stephen L. Diamond
`Harold E. Epstein
`Donald C. Fleckenstein
`
`Jay Forster*
`Donald N. Heirman
`
`*Member Emeritus
`
`Also included are the following nonvoting IEEE Standards Board liaisons:
`
`Satish K, Aggarwal
`
`Alan H. Cookson
`
`Chester C. Taylor
`
`Paula M. Kelty
`IEEE Standards Project Editor
`
`iv
`
`Ex. 1026, Page 4
`Authorized licensed use limited to: Reprints Desk. Downloaded on April 28,2021 at 20:15:41 UTC from IEEE Xplore. Restrictions apply.
`
`Ex. 1026, Page 4
`
`

`

`CLAUSE
`
`PAGE
`
`1.
`
`Overview ............................................................................................................................................................. 1
`
`1.1 Scope .......................................................................................................................................................... 1
`1.2 Objectives ................................................................................................................................................... 1
`1.3 Strategies .................................................................................................................................................... 2
`1.4 Design models ............................................................................................................................................ 2
`
`2.
`
`Document notation .............................................................................................................................................. 3
`
`2.1 Conformance levels .................................................................................................................................... 3
`
`2.2 Technical glossary...................................................................................................................................... 4
`
`3.
`
`Electrical specifications ...................................................................................................................................... 5
`
`3.1 Description and configuration .................................................................................................................... 5
`3.2 Electrical specifications ............................................................................................................................. 6
`3.3 AC specifications ..................................................................................................................................... 17
`3.4 Skew specifications .................................................................................................................................. 18
`
`Annex A (informative) Bibliography ............................................................................................................................ 22
`
`Annex B (normative) SCI signal encoding ................................................................................................................... 23
`
`Annex C (informative) Driver and receiver models ..................................................................................................... 28
`
`Ex. 1026, Page 5
`Authorized licensed use limited to: Reprints Desk. Downloaded on April 28,2021 at 20:15:41 UTC from lEEE Xplore. Restrictions apply.
`
`v
`
`Ex. 1026, Page 5
`
`

`

`IEEE Standard for Low-Voltage
`Differential Signals (LVDS) for Scalable
`Coherent Interface (SCI)
`
`1. Overview
`
`1.1 Scope
`
`This standard specifies a process-technology—independent low-voltage (less than 1 V swing) point-to-point signal
`interface as optimized for IEEE Std 1596-1992 [B1],1 which uses a differential driver connected to a terminated
`receiver through a constant-impedance transmission line. The interface will be optimized for CMOS processes, while
`being compatible with other IC processes, including GaAs and BiCMOS. The specification should support a transfer
`rate of at least 200 mega-transfers/second.
`
`In addition, the specification will define encodings for transporting SCI packets over narrow and wide data paths
`(4-, 8-, 32-, 64-, and 128-bits, rather than the 16 bits defined by IEEE Std 1596-1992) using these signals.
`
`1.2 Objectives
`
`The primary goal of this standard is to create a physical layer specification for drivers and receivers and signal
`encoding suitable for use with the SCI as specified by IEEE Std 1596-1992 in low-cost workstation and personal
`computer applications. Other objectives include the following:
`— Technology independence. Specifications should allow designs to be implemented in a variety of integrated-
`circuit technologies.
`— CMOS compatible. Signal voltage levels and other specifications should be compatible with digital CMOS
`processes operating from 2 V through 5 V power supply levels.
`— Backplane and cable applications. Specifications should be optimized for connections between boards
`contained within one chassis and short (less than 5 m) chassis-to-chassis interconnects. Longer connections
`are not prohibited, provided they meet specified signal loss and ground shift criteria for proper receiver
`operation. Connector and cable specifications are beyond the scope of this standard.
`— Scalable. The original l6-bit-wide SCI data path should be supplemented by 4- and 8-bit-wide data paths to
`support a variety of cost/performance ratios. Support for 32-, 64-, and 128-bit—wide data paths will also be
`addressed.
`
`1 The numbers in brackets preceded by the letter B correspond to those of the bibliography in annex A.
`
`Copyright © 1996 IEEE All Rights Reserved
`
`1
`
`Ex. 1026, Page 6
`Authorized licensed use limited to: Reprints Desk. Downloaded on April 28,2021 at 20:15:41 UTC from IEEE Xplore. Restrictions apply.
`
`Ex. 1026, Page 6
`
`

`

`IEEE Std 1596.3-1996
`
`IEEE STANDARD FOR LOW-VOLTAGE
`
`1.3 Strategies
`
`The basic design strategies selected by this standard include the following:
`
`— Low-voltage swing. To minimize power dissipation and enable operation at very high-speed, low-swing
`(400 mV maximum) signals are specified.
`— DWerential signals. Small signal swings require differential signaling for adequate noise margin in practical
`systems.
`— Self-terminated. To minimize board real estate and costs, and to maximize clock rates, each receiver is
`assumed to provide its own termination resistors.
`— Uniform ground. The standard assumes that the ground potential difference between driver and receiver is
`kept small by the system design. The mechanism for constraining the ground potential difference is beyond
`the scope of this standard.
`
`The most controversial decision was to use differential signals, which at first appears to double the number of signal
`lines. The pin-count overhead is actually much less than this, since reliable single-ended schemes require many more
`ground signals (many high-speed chips and/or backplanes provide one ground for every two signal pins) and run
`significantly slower. Other design benefits associated with differential signals include the following:
`
`— Constant driver current. The transmitter consumes a (near) constant current when driving the links; the
`current remains the same, but is routed in the opposite direction when the signal value changes. This
`simplifies the design of power-distribution wiring.
`— Constant link current. The net signaling current in a differential link is (nearly) constant, which greatly
`simplifies system design. The links are unidirectional and transmitters always drive a differential signal per
`table 2—1 or table 2—2. Reversing or stopping links would cause the net common-mode signaling current to
`change, creating system noise.
`— Lowpower. A low signal current can be used, since much of the induced noise and ground-bounce appears as
`a common-mode signal.
`— Simple board design. Although differential signals must be carefully routed on adjacent matched tracks, they
`are usually less sensitive to imperfections in the transmission line environment.
`— Low EMI. Differential signals minimize the area between the signal and the return path. In addition, the equal
`and opposite currents create canceling electromagnetic fields. This dramatically reduces the electromagnetic
`emissions.
`
`— Low susceptibility to externally generated noise. Though these links generate little noise, other parts of the
`system may. Differential signals are relatively immune to this noise.
`
`1.4 Design models
`
`1.4.1 Source-synchronous data
`
`The SCI-LVDS link model assumes unidirectional operation (the driver always at one end of the link, the receiver at
`the other), and that a clock signal is sent along with the data as though it is just another data bit.
`
`Both edges of the clock are used to delimit data, so the maximum transition rate of the clock is the same as the
`maximum transition rate of the data signals. This clock flows through the link at the same velocity as the data, and is
`to be used as the time reference for sampling the data.
`
`In most applications, the received sampled data will need to be synchronized to the receiver’s local clock. If the
`transmitter’s clock and the receiver's clock are independent, and thus perhaps at slightly different frequencies,
`occasional symbols will need to be inserted or removed from time to time in an elasticity buffer in order to maintain
`synchronization.
`
`2
`
`Copyright © 1996 IEEE All Rights Reserved
`
`Ex. 1026, Page 7
`Authorized licensed use limited to: Reprints Desk. Downloaded on April 28,2021 at 20:15:41 UTC from IEEE Xplore. Restrictions apply.
`
`Ex. 1026, Page 7
`
`

`

`DIFFERENTIAL SIGNALS (LVDS) FOR SCALABLE COHERENT INTERFACE (SCI)
`
`IEEE Std 1596.3-1996
`
`The transmission system shall ensure that the setup and hold requirements of the receiving latches are met, in order to
`avoid incorrect data sampling and triggering metastable states. The receiver can observe the timing of the received
`clock relative to its own clock in order to choose an appropriate sampling time.
`
`By carefully adhering to these assumptions, the SCI signaling protocol becomes independent of distance or delay. The
`maximum distance is limited by signal skew, caused by slight differences in propagation velocity from one signal to
`another, and by attenuation and distortion of the signals.
`
`Because these signals are unidirectional, it is relatively easy to reshape and time-align them in order to transmit them
`greater distances. However, this may introduce timing jitter, which can make it impossible for the receiver to anticipate
`clock transitions with sufficient accuracy for reliable operation.
`
`1.4.2 Terminated transmission lines
`
`In addition to extending the signal encoding to parallel widths not included in IEEE Std 1596-1992, this standard
`specifies driver and receiver parameters only. However, a system must interconnect these components to be useful. The
`interconnect termination is specified in the receiver portion of this standard. The interconnect is beyond the scope of
`this standard because of the many options possible. The interconnect could include bond wires, packages and pins,
`printed circuit board, cables, connectors, multi—chip modules, wafer scale integration, or any combination of the
`previous options in one driver-to-receiver signal path. This signal path is important to the correct operation of a system
`implementing LVDS signals and is therefore discussed in general terms in this standard.
`
`At the high data rates this standard supports, it is important to consider the transmission line aspects of the signal path.
`The high-frequency components of the 300 ps transition times make the parasitic reactive signal path components
`important. Familiar concepts, such as the receiver input capacitance, are overshadowed by the parasitic inductance of
`signal path elements that shape the waveform. If the signal delay through a signal path section is greater than the
`allowed minimum transition time, 300 ps, that section must be analyzed as a transmission line with associated
`characteristic impedance and delay. Impedance discontinuities through connectors, pins, solder pads, and bond wires
`to the IC itself cause reflections that degrade the signal integrity.
`
`The receiver and its package input impedance need to match the signal transmission line impedance. This serves to
`minimize noise-causing reflections that create data errors. Given typical CMOS process tolerances, this generally
`implies the use of active devices to adjust the terminating resistance until it matches an external reference. Integrating
`the terminating impedance onto the receiver chip complicates the design and manufacturing, but the trade-off is
`simplified board layout and better signal integrity.
`
`2. Document notation
`
`2.1 Conformance levels
`
`Several key words are used to differentiate between different levels of requirements and options, as follows:
`
`2.1.1 expected: A key word used to describe the behavior of the hardware or software in the design models assumed
`by this specification. Other hardware and software design models may also be implemented.
`
`2.1.2 may: A key word that indicates flexibility of choice with no impliedpreference.
`
`2.1.3 shall: A key word indicating a mandatory requirement. Designers are required to implement all such mandatory
`requirements to ensure interoperability.
`
`2.1.4 should: A key word indicating flexibility of choice with a strongly preferred alternative. Equivalent to the phrase
`is recommended.
`
`Copyright © 1996 IEEE All Rights Reserved
`
`3
`
`Ex. 1026, Page 8
`Authorized licensed use limited to: Reprints Desk. Downloaded on April 28,2021 at 20:15:41 UTC from IEEE Xplore. Restrictions apply.
`
`Ex. 1026, Page 8
`
`

`

`IEEE Std 1596.3-1996
`
`IEEE STANDARD FOR LOW-VOLTAGE
`
`2.2 Technical glossary
`
`Many bus and interconnect-related technical terms are used in this document. These terms are defined below:
`
`2.2.1 backplane: A board that holds the connectors into which SCI modules can be plugged. In ring-based SCI
`systems, the backplane may contain wiring that connects the output link of one module to the input link of the next.
`Usually the backplane provides power connections, power status information, and physical position information to the
`module.
`
`2.2.2 board: The physical component that is inserted into one of the backplane slots. Note that a board may contain
`multiple nodes.
`
`2.2.3 byte: Eight bits of data. Syn: octet.
`
`2.2.4 differential voltage signal: The voltage difference between the true and complementary signals from a driver
`with two single-ended outputs whose signals always complement each other. Differential signals are also referred to as
`“balanced signals.”
`
`2.2.5 driver: An electrical circuit whose purpose is to signal a binary state for transmitting information. Also referred
`to as a “generator” in international standards.
`
`2.2.6 flag: A signal used to delimit packets in parallel-signal—transmission implementations.
`
`2.2.7 ground potential difference voltage: The voltage that results from current flow through the finite resistance and
`inductance between the receiver and driver circuit ground voltages.
`
`2.2.8 idle symbol: A symbol that is not inside a packet and is therefore not protected by a CRC. Idle symbols serve
`to keep links running and synchronized when no other data are being transmitted. The idle symbol also contains
`flow-control information.
`
`2.2.9 jitter: Refers to the time-uncertainty of a transitioning edge recurring in a repetitive signal. This uncertainty is
`only with respect to other edges in that signal. Jitter is commonly measured using random bit patterns and
`accumulating an eye pattern to show the worst-case difference in transitions.
`
`2.2.10 LVDS: An abbreviation for low-voltage differential signal.
`
`2.2.11 offset voltage: The driver offset voltage is the average dc voltage generated by the differential driver;
`Vos = (Voa + Vob) / 2-
`
`2.2.12 packet: A collection of symbols that contains addressing information and is protected by a CRC. A subaction
`consists of two packets: a send packet and an echo packet.
`
`2.2.13 physical interface: The circuitry that interfaces a module’s nodes to the input link, output link, and
`miscellaneous signals.
`
`2.2.14 receiver common-mode voltage: The combination of three components: 1) the driver-receiver ground
`potential difference (Vgpd); 2) the longitudinally coupled peak noise voltage measured between the receiver circuit
`ground and the signal transmission media with the driver end shorted to ground (Vnoise); 3) the driver offset voltage.
`
`2.2.15 receiver differential noise margin high: The tolerable signal voltage variation from any source that still
`results in the receiver producing a logic high output state when the driver is stimulated by a logic high input.
`Differential noise margin high is calculated by subtracting the receiver’s minimum differential high input voltage from
`the driver's minimum high differential output voltage; Vodh(min) — Vidh(min).
`
`2.2.16 receiver differential noise margin low: Tolerable voltage variation to guarantee that the receiver produces a
`logic low output when the driver is stimulated by a logic low input; Vidl(max) — V0d1(max).
`
`2.2.17 SCI: See:Scalable Coherent Interface
`
`2.2.18 Scalable Coherent Interface (SCI): An abbreviation for the Scalable Coherent Interface standard, IEEE Std
`1 596-1992 .
`
`4
`
`Copyright © 1996 IEEE All Rights Reserved
`
`Ex. 1026, Page 9
`Authorized licensed use limited to: Reprints Desk. Downloaded on April 28,2021 at 20:15:41 UTC from IEEE Xplore. Restrictions apply.
`
`Ex. 1026, Page 9
`
`

`

`DIFFERENTIAL SIGNALS (LVDS) FOR SCALABLE COHERENT INTERFACE (SCI)
`
`IEEE Std 1596.3-1996
`
`2.2.19 signal line: An electrical or optical information-carrying facility, such as a differential pair of wires or an
`optical fiber, with associated driver and receiver, carrying binary true/false logic values.
`
`2.2.20 skew: The difference in time that is unintentionally introduced between changing signal levels (incident edges)
`that occur on parallel signal lines. This difference results in an uncertain position with respect to time among parallel
`signals.
`
`2.2.21 symbol: Refers to data within an SCI packet. A 16-bit unit of data accompanied by flag information. The flag
`information may be explicitly present as a 17th bit, or implied by the context. Symbols are transmitted one after
`another to form SCI packets or idles. The particular physical layer used to transmit these symbols is not visible to the
`logical layer.
`
`2.2.22 sync packet: A special packet that is used heavily during initialization and occasionally during normal
`operation for the purpose of checking and adjusting receiver circuit timing.
`
`3. Electrical specifications
`
`3.1 Description and configuration
`
`A LVDS interface, (figure 3-1), has a low-voltage swing (400 mV single-ended maximum), is connected point-to-point,
`and achieves a very high data rate (500 Mbits per second per signal pair) and reduced power dissipation. Power is low
`because signal swings are small: aminimurn of2. 5 mA are sent through a 100 Q termination resistor. This sharply reduced
`power dissipation enables an important advance: integrating the line termination resistors, interface drivers and receivers,
`and the processing logic in the same integrated circuit.
`
`driver
`
`interconnect
`
`receiver
`
`
`
`Figure 3-1 —LVDS interface
`
`Switching speed is high because the driver load is an uncomplicated point-to-point 100 9 transmission line
`environment. Switching speed is also high because interface devices are all on the same piece of semiconductor
`material, reducing the skew due to process, temperature, and supply variations between signal pairs. Connected in
`serial or parallel pairs, the LVDS interface forms a link used to transfer packets between integrated circuits, such as
`SCI nodes. For example, figure 3-2 shows circuit boards with LVDS links connected in a ring. The ring is implemented
`on a printed circuit board (PCB) similar in mechanical function to a multidrop bus backplane. The difference is that
`fewer PCB layers are needed to make the point— to-point connections. The PCB is simplified by eliminating the
`multidrop bus lines, as there is no need to route around interlayer vias used to make mechanical and electrical
`connections.
`
`Copyright © 1996 IEEE All Rights Reserved
`
`5
`
`Ex. 1026, Page 10
`Authorized licensed use limited to: Reprints Desk. Downloaded on April 28,2021 at 20:15:41 UTC from IEEE Xplore. Restrictions apply.
`
`Ex. 1026, Page 10
`
`

`

`IEEE Std 1596.3-1996
`
`IEEE STANDARD FOR LOW-VOLTAGE
`
`SCI interface
`controller
`
`SCI interface
`controller
`
`SCI interface
`
`controller
`
`1, 4, 8, 16, 32, 64, or 128 bit data
`
`Figure 3-2 —Links in SCI application (ring connection)
`
`LVDS is independent of the physical layer transmission media. As long as the media deliver the signals to the receiver
`with adequate noise margin and within the skew tolerance range, the interface will be reliable. This is a great advantage
`when using cables to carry LVDS signals. Since all connections are point-to-point, physical links between nodes are
`independent of other node connections in the same system. This allows for freedom in developing a useful
`interconnect that fits the needs of the application.
`
`The data path can be serial or parallel with l-, 4-, 8-, 16-, 32—, 64-, or 128-bits, depending on the needs of the user
`(see annex A, Signal encoding, for all widths except 1 and 16, which are defined in IEEE Std 1596-1992, clause 6,
`Physical layer).
`
`Electrical specifications and skew specifications are optimized for 2—5 V supply voltages. The full range of
`semiconductor process technologies can be used to implement LVDS. It is intended that the specification be
`interoperable for all these technologies. The rapid trend toward reduced power supply voltage was considered in
`providing for signals that can be compatible with future system requirements.
`
`The physical environment of point-to-point connections between circuit boards is further divided into two categories.
`The first (a general purpose link) is for circuitboards thatneed to operate with tolerance for Vgpd (table 3 -1). This tolerance
`(approximately i 1 V for a 2.5V powered system) is for a general purpose system. The second (a reduced-range link)
`is for boards mounted on a PCB or similar environment that will guarantee less than 50 mV Vgpd (table 3-2). In this
`environment, the differential signal is reduced by reducing the driver current. This reduces the power at both driver and
`receiver. This is a special consideration for subsystem implementations such as IEEE Std 1596.4-1994 RamLink.
`
`The backplane environment implies short interconnects with controlled Vgpd. The use of cables implies that all the
`skew and signal quality requirements will be met by the cables, and the system designer will account for the worst-case
`Vgpd and provide appropriate safeguards. The scope ofthe electrical specification is the differential interface of drivers
`and receivers. The transmission media specification, whether cables or printed circuits, is beyond the scope of this
`standard.
`
`3.2 Electrical specifications
`
`The specification for driver and receiver parameters is given in table 3-1 and table 3-2. Descriptions of these
`parameters are contained in the following subclauses. These specifications shall be satisfied over the product’s stated
`power supply voltage and temperature operating range.
`
`6
`
`Copyright © 1996 IEEE All Rights Reserved
`
`Ex. 1026, Page 11
`Authorized licensed use limited to: Reprints Desk. Downloaded on April 28,2021 at 20:15:41 UTC from IEEE Xplore. Restrictions apply.
`
`Ex. 1026, Page 11
`
`

`

`DIFFERENTIAL SIGNALS (LVDS) FOR SCALABLE COHERENT INTERFACE (SCI)
`
`IEEE Std 1596.3-1996
`
`Table 3-1 —General purpose link
`
`Driver dc specifications:
`———-“I
`=
`0
`Output voltage high, V0a or Vob
`11:13};tolfggiirleiél-g’ - 1475
`Output voltage low, Voa or Vob
`R10“: 100 9 il% ---
`Outputdifferenfialvouage
`Rm: 1009:1% "m
`Rload=100 Q i1%
`1275
`1125
`Refer to figure 3_7
`Output offset voltage
`Vos
`140
`40
`ch=1.0 V and 1.4 V
`Output impedance, single ended
`Ro
`
`AR0
`R0 mismatch between A & B
`ch=1.0 V and 1.4 V
`10
`%
`
`Q
`
`mV
`
`
`
`|AVodI
`
`AV0s
`
`Ilsa,
`
`Change in |V0d| between “0” and “1”
`
`Rload = 100 9 i1%
`
`Change in V0s between “0” and “1”
`
`Output current
`
`Rload = 100 9 i1%
`Driver shorted to
`ground
`Drivers shorted
`
`_—---
`Receiver dc specifications (all voltages are given with respect to receiver circuit ground voltage):
`
`-——--—
`Receiver differential input
`
`
`Driver ac specifications:
`
`Units
`Max
`Min
`Conditions
`Parameter
`Symbol
`
`Clock
`Clock signal duty cycle
`250 MHz
`
`V0d fall time, 20—80%
`
`V0d rise time, 20—80%
`
`21cad = 100