United States Patent (19)
`Tien et al.
`
`54 PCI-PCI BRIDGE AND PCI-BUS AUDIO
`ACCELERATOR INTEGRATED CIRCUIT
`
`75 Inventors: Paul Tien, Fremont; Cheng-Yeuan
`Tsay, Pleasanton; Rsong-Hsiang Shiao,
`Fremont, all of Calif.
`73 Assignee: ESS Technology, Fremont, Calif.
`
`21 Appl. No.: 09/074,657
`22 Filed:
`May 6, 1998
`511 Int. Cl. ............................. GO6F13FOO GO6F 13/38
`51
`700;
`/
`52 U.S. Cl. ............................ 710/129, 710/127, 710/64;
`345/435; 84/604; 84/621; 84/622; 84/647
`58) Field of Search
`345/435: 710/127
`710129,6484/602,604 621 622 647.
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`References Cited
`U.S. PATENT DOCUMENTS
`5,689,080 11/1997 Gulick ....................................... 84/604
`5,909,559 6/1999 So ........................................... 710/127
`
`56)
`
`USOO6157976A
`Patent Number:
`11
`(45) Date of Patent:
`
`6,157,976
`Dec. 5, 2000
`
`OTHER PUBLICATIONS
`PCI System Architecture, Tom Shanley/Don Anderson,
`1995, pp. 381-382.
`
`Primary Examiner Ayaz R. Sheikh
`Assistant Examiner Rupal D. Dharia
`Attorney, Agent, or Firm-Gray Cary Ware & Freidenrich
`57
`ABSTRACT
`
`A semiconductor device with an embedded PCI 2.1 com
`pliant bridge provides expanded functionality as System
`level implementations of a PCI-to-PCI bridge, and enhances
`p
`9.
`the level of integration possible. The embedded PCI-to-PCI
`bridge allows the creation of multi-function, multimedia
`add-on cards Supporting multiple devices. Multi-function,
`multimedia Subsystems that provide audio, graphics, MPEG,
`etc., are mapped into a bridged-to PCI-bus that keeps Such
`traffic off the main PCI-bus. The advantage for the system or
`add-in card Vendor is that the various multimedia chips that
`are combined can come from different Sources, providing an
`optimized and highly customized combination of functions.
`
`1 Claim, 2 Drawing Sheets
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`1O
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`14
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`2
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`PC-bus
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`(10 max)
`2 loads each
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`22
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`PC I/O controllers
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`Intel Corporation v. ACQIS LLC
`Intel Corp.'s Exhibit 1040
`Ex. 1040, Page 1
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`U.S. Patent
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`Dec. 5, 2000
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`Ex. 1040, Page 3
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`Ex. 1040, Page 3
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`1
`PC-PCI BRIDGE AND PCI-BUS AUDIO
`ACCELERATOR INTEGRATED CIRCUIT
`
`FIELD OF THE INVENTION
`The present invention relates to digital electronic circuits,
`and more particularly to personal computer PCI-bus SyS
`temS.
`
`DESCRIPTION OF THE PRIOR ART
`The peripheral component interface (PCI) bus has become
`the interface bus of choice for high-Speed devices because it
`is well-equipped to handle newer, more demanding appli
`cations with its 32-bit data path, 33 MHz clock speed and a
`maximum data transfer rate of 132 MB/sec.
`However, PCI loading constraints limit the number of
`devices that can be Supported directly on a System mother
`board or through expansion slots, so PCI-to-PCI bridge
`chips have been developed by a number of major Suppliers
`to increase the number of available System expansion slots.
`Embedding a bridge in a Semiconductor device that also
`Supplies other functionality provides a higher degree of
`integration and enables the creation of multi-function, mul
`timedia expansion cards, where a single add-in card could
`Support audio, graphics acceleration and Video conferenc
`ing.
`The PCI bus is typically isolated from the CPU local bus
`by a PCI controller, a so-called “Northbridge”. The CPU can
`thereby write data to PCI peripherals and go on to its next
`operation rather than waiting for the transfer to complete.
`The PCI controller stores the data in its buffer, and sends it
`out later at the most efficient rate.
`The PCI-buS Supports intelligent-device bus mastering, So
`other masters can take control of the bus and do their jobs
`independent of the CPU. The CPU can run in parallel with
`the bus master peripheral because of the buffered design.
`The number of PCI peripheral devices that can be Sup
`ported by a single PCI-bus is based on the electrical loading
`constraints defined in the industry-standard “PCI 2.1 Speci
`fication'. A compliant PCI-bus is capable of Supporting a
`total of ten loads, and two loads are consumed by the basic
`PCI chipset associated with the CPU. PC-device controllers
`that are built into the motherboard present only a single load.
`A Single PCI-buS can therefore only Support four expan
`Sion slots without violating the Specification's loading
`constraints, e.g., one PCI device per expansion slot. High
`end System designers have recently begun to build Systems
`using PCI-to-PCI bridges to provide more expansion slots
`on the motherboard. The PCI bus specifications provide for
`an automatic configuration of any adapter or peripheral
`plugged into the bus to eliminate conflicts between boards in
`the System and the need for jumper headers on a board.
`
`SUMMARY OF THE INVENTION
`It is therefore an object of the present invention to provide
`a System for Supporting ISA-bus applications Software on a
`PCI-based hardware system.
`It is a further object of the present invention to provide a
`direct memory access controller that accepts ISA-bus inter
`rupt controller commands and accesses and that translates
`these into PCI-bus equivalent interrupt controller commands
`and accesses.
`It is a still further object of the present invention to
`emulate an ISA-bus interrupt controller that accepts and
`responds to direct memory acceSS controller commands and
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`accesses for execution by a PCI-bus interrupt controller
`mapped into a PCI-bus memory resource.
`Briefly, a circuit embodiment of the present invention
`comprises a PCI-PCI bridge core integrated on the same
`chip as a PCI-bus audio accelerator.
`An advantage of the present invention is that more
`functionality can be implemented on both PCI-bus add-in
`cards and motherboards.
`These and other objects and advantages of the present
`invention will no doubt become obvious to those of ordinary
`skill in the art after having read the following detailed
`description of the preferred embodiments which are illus
`trated in the various drawing figures.
`
`IN THE DRAWINGS
`FIG. 1 is a functional block diagram of a PC system
`embodiment of the present invention; and
`FIG. 2 is a function block diagram of an audio accelerator
`with an auxiliary integrated PCI-PCI bridge core.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`FIG. 1 illustrates a personal computer (PC) embodiment
`of the present invention, referred to herein by the general
`reference numeral 10. The PC 10 comprises a microproces
`sor (CPU) 12, a system controller (Northbridge “NB”) 14,
`and a peripheral component interconnect (PCI) bus 16. A
`peripheral-bus controller (Southbridge “SB') 18 provides a
`bridge to Several buses including an industry Standard archi
`tecture (ISA) bus 20. APCI-bus audio accelerator peripheral
`22 includes a PCI-bus resident audio accelerator 24 and a
`PCI-PCI bridge 26 both integrated as cores on the same
`integrated circuit (IC). The PCI-PCI bridge 26 provides
`more slots on a secondary PCI-bus 28 for a plurality of
`input-output (I/O) controllers 30.
`The PCI bus is the ideal medium for utilization as a
`multimedia interface due to its high bandwidth, Support for
`bus mastering, and low demands on CPU capacity. By using
`the PCI bus as a multimedia bridge, multimedia Subsystems
`can be designed on a adapter, e.g., PCI-bus expansion card,
`for different target markets. The high level of integration
`achieved by using embedded PCI-to-PCI technology is
`valuable where motherboard form factors decreased in size
`and yet the number of multimedia functions expand.
`In one embodiment, the System controller 14 comprises
`an Advanced Micro-Devices (Sunnyvale, Calif.) AMD-640
`system controller (“Northbridge") has a 64-bit Socket-7
`interface, integrated writeback cache controller, System
`memory controller, and PCI bus controller. Such Socket-7
`interface is optimized for the AMD-K6 processor, providing
`3-1-1-1-1-1-1-1 transfer timing for both read and write
`transactions from PBSRAM at 66 MHz. (The number
`sequence refers to the CPU clock “t” cycles for each
`operation, i.e., 3-1-1-1 means the first data will be available
`at the third “t” when issue the operation, then the conse
`quence data only need additional one “t cycle, and So on.)
`The AMD-640's internal memory controller has a data
`buffering design that uses four cache lines, e.g., Sixteen
`quadwords, of processor-to-DRAM or cache-to-DRAM
`write buffering with concurrent writeback capability to
`accelerate writeback and write-miss cycles. The integrated
`PCI bus controller does concurrent processor and PCI opera
`tion with a five-doubleword posted write buffer. PCI con
`currency with DRAM or cache memory is achieved through
`a 48-doubleword post write buffer and 26-doubleword
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`prefetch buffer. Byte-merging is used to optimize processor
`to-PCI throughput and reduce PCI bus traffic by converting
`consecutive processor addresses into burst PCI cycles. The
`AMD-640 system controller uses a variety of techniques to
`minimize PCI initiator read latency and DRAM access,
`including Snoop ahead, Snoop filtering, forwarding cache
`writebacks to the PCI initiator, and merging L1 writebacks
`into the PCI-posted write buffers to minimize PCI initiator
`read latency and DRAM utilization. To minimize Snoop
`overhead, the integrated PCI controller Supports enhanced
`PCI bus commands, Such as memory-read-line, memory
`read-multiple, and memory-write-invalidate. The combina
`tion allows a PCI initiator to achieve the full 133-Mbps burst
`transfer rate.
`In another embodiment, the peripheral-bus controller 18
`comprises an AMD-645 peripheral bus controller
`(“Southbridge”). The AMD-645 has an integrated ISA bus
`controller, enhanced master mode PCI EIDE controller with
`Ultra DMA/33 technology, an ACPI-compatible power man
`agement unit, a USB controller, a PS2-compatible keyboard/
`mouse controller, and a real-time clock (RTC) with extended
`256-byte CMOS RAM. The on-chip EIDE controller has a
`dual-channel DMA engine capable of interlaced dual
`channel commands. High-bandwidth PCI transfers are
`achieved by a sixteen double-word data FIFO with full
`scatter and gather capability. The integrated USB controller
`has a root hub with two ports having 18-level-deep data
`FIFOs and built-in physical layer transceivers.
`The AMD-645 peripheral bus controller is marketed as
`meeting Microsoft Windows(R 95 Plug-and-Play require
`ments with steerable PCI interrupts, ISA interrupts, and
`DMA channels. The integrated power management unit is
`compliant with ACPI and APM and provides dedicated input
`pins for external modem ring indication and power-on, five
`general-purpose I/O pins with option for I2C port, and
`Sixteen general-purpose pins that can be programmed as
`inputs or outputs. To manage power management events, the
`AMD-645 controller includes an ACPI power management
`timer, a GPO timer, a GP1 timer, a secondary event timer,
`and a conserve mode timer. Two types of Sleep States, e.g.,
`Soft-off and power-on Suspend, are Supported with hardware
`automatic wake-up. Additional functionality includes event
`monitoring, CPU clock throttling, hardware and Software
`based event handling, and multiple external SMI Sources.
`The PCI-bus audio accelerator peripheral 22 or PCI
`expansion card may comprise an ESS Technology (Fremont,
`Cailf.) PCI audio accelerator chip, e.g., marketed as
`MAESTRO-1TM. At a minimum, the PCI-bus audio accel
`erator peripheral 22 is preferably compliant with major
`industry Standards including the Audio Subsystem Specifi
`cation of PC97, Windows 95 DirectSoundTM, Windows
`Sound System, AC'97 CODEC Interface, and the PCI 2.1
`Bus Specification.
`The Maestro-1 is a dual audio-engine architecture that
`comprises of a 64-voice, pipelined, wavetable Synthesizer
`and a programmable audio signal processor that can Simul
`taneously handle multiple audio Streams of different data
`types, high-quality music Synthesis, and Voice compression
`and decompression. Wavetable technology uses algorithms
`to frequency Shift a stored digitized Sound Sample of the
`instrument playing to create the various notes, tones and
`octaves of a performance
`Market acceptance of early PC wavetable sound solutions
`was hampered by a lack of compatibility with Software
`developed for the SOUNDBLASTER standard and the high
`cost of the first implementations. Software compatibility has
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`now been resolved by vendors such as ESS Technology
`through hardware legacy Support. ESS Technology's
`solution, Transparent DMA, creates a virtual ISA bus that
`interfaces with the PCI bus. The expense of the first wavet
`able Synthesis devices has also now been driven down, in
`part through the use of techniques Such as downloadable
`Sound fonts that also enhance performance.
`The first wavetable synthesis PC audio solutions utilized
`ROM to Store the Sound Samples needed to generate Sound.
`The ROM was expensive and limited the number of sounds
`that a wavetable engine could produce. Also, because the
`audio Samples were loaded by the hardware device vendor,
`the software developer had no control over how their
`application would Sound with a given vendor's wavetable
`hardware accelerator.
`ESS Technology's PC audio solutions utilize the high
`bandwidth PCI bus and WaveCaches8 technology to store
`MIDI sound samples in a PC's main memory. The down
`loadable sound samples saves the cost of ROM and allows
`a Software developer to determine precisely how their title
`will sound on every system that utilizes downloadable sound
`fonts.
`FIG. 2 illustrates a PCI-bus audio accelerator peripheral
`50 that is similar to the audio accelerator peripheral 22 of
`FIG. 1. The PCI-bus audio accelerator peripheral 50 com
`prises a PCI-interface 52, a SOUNDBLASTER datapath 54,
`a wave processor 56, a 512x16 wave cache 58, an applica
`tion specific signal processor (ASSP) 60, a ring bus 62, a
`SIO-2 codec 64, a SIO-1 codec 66, and an IS serial
`interface 68. A high-performance game port (HPGP) 70
`provides an interface for a joystick, and a general purpose
`input-output port (GPI/0) 72 provides connections to mul
`tiplexed buses. A PCI-PCI bridge 74 serves to expand the
`number of PCI-bus peripheral cards that the PCI-CPU 12
`can address.
`The wave processor 56 is a dual-engine, Sixty-four
`channel, pipelined wave processor. The ASSP 60 is a pro
`grammable audio signal processor. Together these provide
`Simultaneous Support for multiple audio Streams of different
`types. Such architecture enables complex, three-dimension
`positional gaming Sound effects to be implemented while
`also Supporting voice communications over the Internet
`from multiple Sources. Embodiments of the present inven
`tion preferably Support Sixty-four independently program
`mable wave processor channels and provide for DIRECT
`SOUND(R) hardware acceleration with digital mixing of up
`to thirty-two wave Streams. Audio Streams of any frequency
`are converted to forty-eight kHz. Each of the sixty-four
`channels can be assigned its own parameters to control
`panning, tremolo, Vibrato, and tone-filtering. The channels
`also Support independently programmable Special effects,
`e.g., reverb, chorus, flange, echo, and three-dimension Spa
`tial enhancements to create positional Special effects. The
`high bandwidth PCI-bus is used to store MIDI-samples in
`main memory. Downloadable Sound Samples relieve need
`ing ROM-type memory to store sound fonts, a allow soft
`ware developers to control the Sound PCI-bus audio accel
`eratorS.
`A more obvious advantage that the PCI bus brings to
`audio applications is sheer bandwidth. At 133 MB/second,
`the PCI bus represents a much larger “pipe” than the 7
`MB/second ISA bus. In addition to being able to move large
`amounts of data quickly through the bus, PCI accelerators
`are able to transfer multiple data streams with different
`destinations during a Single bus master cycle. Because PCI
`audio accelerators can Support multiple data Streams of
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`different types, it can also reduce the latencies typically
`asSociated with Internet-based interactive audio, phone and
`conferencing applications.
`Although the present invention has been described in
`terms of the presently preferred embodiments, it is to be
`understood that the disclosure is not to be interpreted as
`limiting. Various alterations and modifications will no doubt
`become apparent to those skilled in the art after having read
`the above disclosure. Accordingly, it is intended that the
`appended claims be interpreted as covering all alterations
`and modifications as fall within the true Spirit and Scope of
`the invention.
`What is claimed is:
`1. An audio accelerator peripheral (50), comprising:
`a single integrated circuit (IC) having a PCI-interface (52)
`for providing a limited PCI-bus loading to a primary
`PCI-bus (16);
`a PCI-bus resident audio accelerator core (24) disposed in
`the IC that includes a SOUNDBLASTER-type datap
`ath (54) connected between said PCI-interface (52) and
`a wave processor (56) for creating a virtual ISA bus
`interfaced with said primary PCI-bus (16); and
`a PCI-PCI bridge core (26,74) disposed in the IC and
`providing an interface between said PCI-interface (52)
`and a secondary PCI-bus (28) for a plurality of expan
`sion input-output (I/O) controllers (30);
`wherein the PCI-bus resident audio accelerator core (24)
`includes a dual audio-engine architecture with a
`64-voice, pipelined, wavetable Synthesizer, and a pro
`grammable audio signal processor that can Simulta
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`neously handle multiple audio Streams of different data
`types, high-quality music Synthesis, and Voice com
`pression and decompression, wherein Said wavetable
`includes algorithms for frequency shifting Stored digi
`tized Sound Samples of an instrument playing to create
`a variety of notes, tones and octaves of a performance;
`wherein the PCI-bus resident audio accelerator core (24)
`further comprises:
`an application specific signal processor (ASSP) (60)
`implemented as a programmable audio-signal pro
`cessor that combines with said wave processor (56)
`for providing Simultaneous Support for multiple
`audio Streams of different types, and
`a wave cache (58) connected to both said ASSP (60)
`and said wave processor (56), and for providing
`temporary Storage of memory data downloaded from
`said primary PCI-bus (16) that is later provided
`on-demand to said wave processor (56); and
`wherein said wave processor (56) and ASSP (60) combine
`to enable complex, three-dimension positional gaming
`Sound-effects, and Support Sixty-four independently
`programmable wave processor channels for
`DIRECTSOUND-type hardware acceleration with
`digital mixing of up to thirty-two wave Streams, and
`wherein audio streams of any frequency are converted
`to forty-eight kHz, and each of Sixty-four channels can
`be assigned their own parameters to control panning,
`tremolo, Vibrato, and tone-filtering.
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