HyperTransport
`
` Technology Consortium
`
`HyperTransport™ I/O
`Link Specification
`
`Revision 1.03
`
`10/10/2001
`
`Copyright 2001 HyperTransport Technology Consortium
`
`Intel Corporation v. ACQIS LLC
`Intel Corp.'s Exhibit 1043
`Ex. 1043, Page 1
`
`

`

`HyperTransport
`
` Technology Consortium
`
`REVISION
`1.03
`
`REVISION HISTORY
`Initial release
`
`Date
`10/10/01
`
`The HyperTransport Technology Consortium disclaims all warranties and
`liability for the use of this document and the information contained
`herein and assumes no responsibility for any errors that may appear
`in this document, nor does the HyperTransport Technology
`Consortium make a commitment to update the information
`contained herein.
`
`DISCLAMER
`
`This specification is provided “AS IS” with no warranties
`whatsoever,
`including
`any warranty of merchantability,
`noninfrigment, fitness for any particular purpose, or any warranty
`otherwise arising out of any proposal, specification or sample.
`The HyperTransport Technology Consortium disclaims all
`liability for infringement of property rights, relating to use of
`information in this specification. No license, express or implied,
`by estoppel or otherwise, to any intellectual property rights is
`granted herein.
`
`Trademarks
`
`HyperTransport is a trademark of the HyperTransport Technology Consortium.
`
`AMD is a trademarks of Advanced Micro Devices, Inc.
`
`Other product names used in this publication are for identification purposes only and may be trademarks of their
`respective companies.
`
`Ex. 1043, Page 2
`
`

`

`HyperTransport
`
` Technology Consortium
`
`Revision 1.03
`
`Contents
`
`HyperTransport™ I/O Link Specification................................................................................i
`Revision 1.03 RC2......................................................................................................................i
`
`Contents ....................................................................................................................................3
`List of Figures ......................................................................................................................... 12
`
`List of Tables........................................................................................................................... 13
`Preface..................................................................................................................................... 17
`This Document..................................................................................................................... 17
`Organization......................................................................................................................... 17
`
`About HyperTransport™ Technology .................................................................................. 17
`HyperTransport™ Technology Consortium .......................................................................... 18
`Section 1 – Protocol ........................................................................................................... 19
`Overview.................................................................................................................................. 19
`1.1
`Terminology...................................................................................................... 20
`
`2
`
`3
`
`4
`
`1.2
`
`HyperTransport™ Technology in x86 Platforms ............................................... 21
`
`Signaling........................................................................................................................... 23
`
`Packet Definition.............................................................................................................. 25
`3.1
`Use of the CTL Signal....................................................................................... 25
`
`3.2
`3.2.1
`
`Packet Structure ................................................................................................ 26
`Control Packets ................................................................................................. 26
`
`3.2.2
`
`Data Packet....................................................................................................... 31
`
`Fabric Operation.............................................................................................................. 33
`4.1
`Topology........................................................................................................... 33
`4.1.1
`Double-Hosted Chains ...................................................................................... 35
`
`4.1.2
`4.2
`
`HyperTransport™ Technology Signals PWROK and RESET# ......................... 36
`Transactions and UnitID ................................................................................... 37
`
`4.3
`4.4
`
`Link Synchronization ........................................................................................ 37
`Requests............................................................................................................ 38
`
`4.4.1
`
`Sized Reads and Writes..................................................................................... 38
`
`Contents
`
`3
`
`Ex. 1043, Page 3
`
`

`

`Revision 1.03
`
`HyperTransport
`
` Technology Consortium
`
`4.4.2
`4.4.3
`
`4.4.4
`4.4.5
`
`4.5
`4.5.1
`
`4.5.2
`4.6
`
`4.7
`4.8
`
`Broadcast Message ............................................................................................41
`Flush .................................................................................................................41
`
`Fence.................................................................................................................42
`Atomic Read-Modify-Write...............................................................................43
`
`Responses..........................................................................................................44
`Read Response (RdResponse) ...........................................................................44
`
`Target Done (TgtDone) .....................................................................................45
`I/O Streams .......................................................................................................46
`
`Virtual Channels................................................................................................46
`Flow Control .....................................................................................................47
`
`4.9
`4.9.1
`
`Routing .............................................................................................................50
`Acceptance........................................................................................................50
`
`4.9.2
`4.9.3
`
`4.9.4
`4.9.5
`
`Forwarding........................................................................................................51
`Rejection ...........................................................................................................51
`
`Host Bridges......................................................................................................52
`Fairness and Forward Progress ..........................................................................53
`
`5
`
`6
`
`Interrupts..........................................................................................................................57
`5.1
`Interrupt Requests .............................................................................................57
`5.2
`End of Interrupt (EOI) .......................................................................................58
`
`I/O Ordering.....................................................................................................................61
`6.1
`Upstream I/O Ordering ......................................................................................61
`
`6.2
`6.2.1
`
`Host Ordering Requirements .............................................................................63
`Host Responses to Nonposted Requests.............................................................64
`
`6.3
`6.4
`
`Downstream I/O Ordering .................................................................................64
`Ordering in Sharing Double-Hosted Chains .......................................................65
`
`7 Configuration Accesses ....................................................................................................67
`7.1
`Configuration Cycle Types ................................................................................67
`
`7.2
`7.2.1
`
`Configuration Space Mapping ...........................................................................68
`Function and Register Numbering .....................................................................68
`
`7.2.2
`
`Device Numbering ............................................................................................68
`
`4
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`Ex. 1043, Page 4
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`

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`HyperTransport
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` Technology Consortium
`
`Revision 1.03
`
`7.2.3
`
`Bus Numbering ................................................................................................. 69
`
`7.3
`7.3.1
`
`HyperTransport™ Technology Device Header.................................................. 70
`Command Register: Offset 04h ......................................................................... 71
`
`7.3.2
`7.3.3
`
`7.3.4
`7.3.5
`
`7.3.6
`7.3.7
`
`7.3.8
`7.3.9
`
`Status Register: Offset 06h................................................................................ 71
`Cache Line Size Register: Offset 0Ch: R/O ....................................................... 72
`
`Latency Timer Register: Offset 0Dh: R/O ......................................................... 72
`Base Address Registers (BARs): Offsets 10-24h: R/W: Warm Reset................. 72
`
`CardBus CIS Pointer: Offset 28h: R/O .............................................................. 73
`Capabilities Pointer: Offset 34h: R/O ................................................................ 73
`
`Interrupt Line Register: Offset 3C: R/W: Warm Reset....................................... 73
`Interrupt Pin Register: Offset 3Dh: R/O............................................................ 73
`
`7.3.10 Min_Gnt, and Max_Lat Registers: Offsets 3E and 3Fh: R/O ............................. 73
`7.4
`HyperTransport™ Technology Bridge Headers................................................. 73
`
`7.4.1
`7.4.2
`
`7.4.3
`
`7.4.4
`7.4.5
`
`7.4.6
`
`7.4.7
`7.4.8
`
`Command Register: Offset 04h ......................................................................... 75
`Status, Cache Line Size, Primary Latency Timer, Base Address, Interrupt Pin, and
`Interrupt Line Registers..................................................................................... 75
`Secondary Latency Timer Register: Offset 1Bh: R/O ........................................ 75
`
`Secondary Status Register: Offset 1Eh .............................................................. 75
`Memory and Prefetchable Memory Base and Limit Registers: Offsets 20-2Ch:
`R/W: Warm Reset ............................................................................................. 76
`I/O Base and Limit Registers: Offsets 1C, 1D, 30, and 32h: R/W: Warm Reset. 77
`
`Capabilities Pointer Register: Offset 34h: R/O .................................................. 77
`Bridge Control Register: Offset 3Eh.................................................................. 77
`
`7.5
`7.5.1
`
`Capability Registers .......................................................................................... 79
`Capability ID: Offset 00h: R/O.......................................................................... 81
`
`7.5.2
`7.5.3
`
`7.5.4
`7.5.5
`
`7.5.6
`7.5.7
`
`Capabilities Pointer: Offset 01h: R/O ................................................................ 81
`Command Register: Offset 02h ......................................................................... 81
`
`Link Control Register: Offsets 04h and 08h....................................................... 85
`Link Configuration Register: Offsets 06h and 0Ah ............................................ 88
`
`Revision ID Register: Offset 08h or 0Ch: R/O................................................... 91
`Link Frequency Register: Offsets 09h or 0Dh and 11h (Bits 3:0): R/W: Cold Reset
`
`Contents
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`5
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`Ex. 1043, Page 5
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`Revision 1.03
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`
` Technology Consortium
`
`to 0....................................................................................................................91
`Link Error Register: Offsets 09h or 0Dh and 11h (Bits 7:4) ...............................93
`
`Link Frequency Capability Register: Offsets 0Ah or 0Eh and 12h: R/O.............93
`Feature Capability Register: Offset 0Ch or 10h: R/O .........................................94
`
`Enumeration Scratchpad Register: Offset 10h or 14h: R/W: Cold Reset to 0......95
`Error Handling Register: Offset 12h or 16h .......................................................95
`
`7.5.8
`
`7.5.9
`7.5.10
`
`7.5.11
`7.5.12
`
`7.5.13 Memory Base Upper 8 Bits: Offset 14h or 18h: R/W: Warm Reset to 0 ...............97
`7.5.14 Memory Limit Upper 8 Bits: Offset 15h or 19h: R/W: Warm Reset to 0 ..............98
`
`7.6
`7.6.1
`
`7.6.2
`7.7
`
`7.7.1
`7.7.2
`
`7.7.3
`7.7.4
`
`Interrupt Discovery and Configuration Capability Block ...................................98
`Last Interrupt: Index 01h: R/O...........................................................................98
`
`Interrupt Definition Registers: Index 10h and Higher: Warm Reset ...................99
`Address Remapping Capability Block .............................................................100
`
`Capability Header............................................................................................100
`Secondary Bus Window Base Registers: R/W, Warm Reset to 0 .....................101
`
`DMA Primary Base Register: R/W: Warm Reset to 0......................................101
`DMA Secondary Base and Limit Registers: R/W: Warm Reset to 0.................101
`
`8
`
`System Management ......................................................................................................103
`8.1
`Command Mapping .........................................................................................103
`8.2
`Special Cycles .................................................................................................105
`
`8.3
`
`Disconnecting and Reconnecting HyperTransport™ Links ..............................105
`
`9 Address Map ..................................................................................................................109
`
`10 Error Handling...............................................................................................................111
`10.1
`Error Conditions..............................................................................................111
`
`10.1.1
`10.1.2
`
`10.1.3
`10.1.4
`
`10.1.5
`10.1.6
`
`10.1.7
`
`Transmission Errors: 8-Bit, 16-Bit, and 32-Bit Links.......................................111
`Transmission Errors: 2-Bit and 4-Bit Links......................................................113
`
`Protocol Errors ................................................................................................114
`Receive Buffer Overflow Errors ......................................................................114
`
`End of Chain Errors.........................................................................................114
`Chain Down Errors..........................................................................................115
`
`Response Errors ..............................................................................................115
`
`6
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`Ex. 1043, Page 6
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`HyperTransport
`
` Technology Consortium
`
`Revision 1.03
`
`10.2
`
`Error Reporting ............................................................................................... 116
`
`10.2.1
`10.2.2
`
`10.2.3
`10.2.4
`
`Error Responses .............................................................................................. 116
`Error Interrupts ............................................................................................... 116
`
`Sync Flooding ................................................................................................. 117
`Error Routing CSRs ........................................................................................ 118
`
`11 Clocking.......................................................................................................................... 119
`11.1
`Clocking Mode Definitions ............................................................................. 119
`
`11.2
`11.3
`
`11.4
`
`Receive FIFO.................................................................................................. 120
`Async Mode Implementation Example............................................................ 121
`
`Link Frequency Initialization and Selection..................................................... 121
`
`12 Reset and Initialization .................................................................................................. 123
`12.1
`Definition of Reset .......................................................................................... 123
`12.2
`System Powerup, Reset, and Low-Level Link Initialization............................. 123
`
`12.3
`12.3.1
`
`I/O Fabric Initialization ................................................................................... 127
`Finding the Firmware ROM ............................................................................ 129
`
`12.4
`12.5
`
`Link Width Initialization ................................................................................. 130
`Link Frequency Initialization .......................................................................... 130
`
`Protocol Appendices ............................................................................................................. 131
`A Address Remapping Capability..................................................................................... 131
`A.1
`I/O Space Aliasing .......................................................................................... 131
`A.2
`Memory Space Mapping ................................................................................. 132
`
`A.3
`
`DMA Window Remapping.............................................................................. 132
`
`B Ordering Rules of Supported I/O Protocols.................................................................. 135
`B.1
`PCI ................................................................................................................. 135
`B.2
`AGP................................................................................................................ 136
`
`B.2.1
`B.2.2
`
`HP AGP Ordering Rules ................................................................................. 136
`LP AGP Ordering Rules.................................................................................. 136
`
`C Mapping of Other Protocol Ordering Rules ................................................................. 137
`C.1
`Processor ........................................................................................................ 137
`
`C.2
`
`PCI ................................................................................................................. 137
`
`Contents
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`7
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`Ex. 1043, Page 7
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`Revision 1.03
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`
` Technology Consortium
`
`C.3
`
`AGP ................................................................................................................138
`
`D Considerations for Isochronous Traffic ........................................................................141
`D.1
`Isochronous Flow Control Mode (Optional).....................................................141
`D.2
`Normal Flow Control Mode.............................................................................142
`
`E Southbridges and Compatibility Buses .........................................................................143
`E.1
`ISA/LPC Deadlock Case .................................................................................143
`
`E.2
`E.3
`
`ISA/LPC Write Post Flushing..........................................................................144
`Subtractive Decoding ......................................................................................144
`
`E.3.1
`E.3.2
`
`E.3.3
`E.3.4
`
`Subtractive Decode in the General Case ..........................................................144
`Subtractive Decode in x86 Legacy Systems.....................................................145
`
`Subtractive Decode in the Simplest Case .........................................................145
`Subtractive Decode Behind a PCI Bridge.........................................................145
`
`E.4
`
`VGA Palette Snooping ....................................................................................146
`
`F Required Behavior in x86 Platforms .............................................................................147
`F.1
`Interrupts.........................................................................................................147
`F.1.1
`Standard EOI...................................................................................................150
`F.1.2
`Legacy PIC (8259) Interrupt Request, Acknowledge, and EOI ........................151
`
`F.1.3
`F.2
`
`Alternate Interrupt Discovery and Configuration Mechanism ..........................151
`System Management .......................................................................................153
`
`F.2.1
`F.2.2
`
`F.2.3
`F.2.4
`
`F.2.5
`F.2.6
`
`F.3
`F.4
`
`F.5
`
`Command Encoding ........................................................................................155
`VID/FID Changes............................................................................................158
`
`Throttling ........................................................................................................158
`C3 System State Transitions and LDTREQ#....................................................159
`
`SMI and STPCLK ...........................................................................................159
`Default State of Virtual Wires..........................................................................160
`
`Initialization Issues..........................................................................................160
`AGP Bridge Issues ..........................................................................................160
`
`Configuration Space Access Mechanism .........................................................162
`
`G CRC Testing Mode.........................................................................................................163
`
`H Doubleword-Based Data Buffer Flow Control..............................................................165
`
`8
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`Ex. 1043, Page 8
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`

`

`HyperTransport
`
` Technology Consortium
`
`Revision 1.03
`
`I Quick Reference for x86 Systems .................................................................................. 167
`Section 2 – Electrical Interface .................................................................................... 168
`13 HyperTransport™ Link Overview................................................................................ 168
`14 Electrical Overview........................................................................................................ 171
`
`15 Supply Characteristics................................................................................................... 172
`16 Power Requirements...................................................................................................... 173
`
`17 Input/Output DC Voltage Characteristics .................................................................... 174
`17.1
`Impedance Requirements ................................................................................ 174
`
`17.2
`17.2.1
`
`DC Output Voltage Requirements ................................................................... 175
`ATE Test Environment ................................................................................... 175
`
`17.2.2
`17.2.3
`
`Reference System Load................................................................................... 175
`Output Voltage Parameter Descriptions........................................................... 176
`
`17.3
`17.3.1
`
`17.3.2
`17.4
`
`17.5
`17.6
`
`17.7
`17.8
`
`DC Input Requirements................................................................................... 176
`ATE Test Environment ................................................................................... 176
`
`Input Parameter Descriptions .......................................................................... 177
`Differential Signal DC Specifications.............................................................. 178
`
`Single-Ended Signal AC/DC Specifications .................................................... 179
`Input/Output AC Voltage Characteristics ........................................................ 180
`
`Impedance Requirements ................................................................................ 180
`AC Output Requirements ................................................................................ 181
`
`17.8.1
`17.8.2
`
`ATE Test Environment ................................................................................... 181
`Reference System Load................................................................................... 182
`
`17.8.3
`17.9
`
`Output Parameter Descriptions........................................................................ 183
`AC Input Requirements................................................................................... 184
`
`17.9.1
`17.9.2
`
`ATE Test Environment ................................................................................... 184
`Input Parameter Descriptions .......................................................................... 184
`
`17.10
`
`Differential Signal AC Specifications.............................................................. 185
`
`18 Link Transfer Timing Characteristics .......................................................................... 186
`18.1
`Signal Groups ................................................................................................. 186
`18.2
`Device Output Timing Characteristics............................................................. 187
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`Ex. 1043, Page 9
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`18.2.1
`18.2.2
`
`18.3
`18.3.1
`
`18.3.2
`18.4
`
`18.4.1
`18.5
`
`Differential Output Skew.................................................................................187
`TCADV (TCADValid)..............................................................................................188
`Device Input Timing Characteristics................................................................189
`Input Differential Skew ...................................................................................189
`TSU and THD.....................................................................................................190
`Interconnect Timing Characteristics.................................................................191
`TCADVRS/RH.......................................................................................................191
`Transfer Timing Characteristics.......................................................................192
`
`18.6
`
`Reconciling Transfer Timing and Link Frequency ...........................................194
`
`19 Phase Recovery Timing Characteristics........................................................................196
`19.1
`Receiver Modes of Operation ..........................................................................196
`19.1.1
`Synchronous Operation ...................................................................................196
`
`19.1.2
`19.1.3
`
`Pseudo Synchronous Operation .......................................................................196
`Asynchronous Operation .................................................................................197
`
`19.2
`19.2.1
`19.2.2
`
`Phase Recovery Timing Variations..................................................................197
`Uncertainty When Initializing the Pointers ......................................................198
`Other Factors Affecting FIFO Size and Read Pointer Separation .....................198
`
`Phase Recovery Timing Characteristics ...........................................................199
`19.3
`Reconciling Phase Recovery Timing to Receiver FIFO Depth and Read Pointer
`19.4
`Initialization .......................................................................................................................201
`19.4.1
`Read Pointer Initialization ...............................................................................201
`
`19.4.2 Minimum FIFO Depth.....................................................................................201
`
`Electrical Interface Appendices............................................................................................202
`
`J DC and AC Characteristics and Relationships .............................................................202
`J.1
`DC Parameters ................................................................................................202
`
`J.2
`J.3
`
`Relationships Between AC and DC Parameters ...............................................203
`Relationships Between Output and Input Parameters .......................................203
`
`K Detailed Transfer Timing Budget..................................................................................204
`K.1
`HyperTransport™ Link Transmitter ................................................................204
`
`K.2
`K.3
`
`10
`
`Differential Skew ............................................................................................205
`Transmitter Clock Uncertainties ......................................................................206
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`HyperTransport
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`Revision 1.03
`
`K.4
`
`K.5
`K.6
`
`K.7
`K.8
`
`K.9
`
`Transmitter PHY Uncertainties ....................................................................... 207
`
`Transmitter Package Skew .............................................................................. 208
`Receiver Package Skew................................................................................... 208
`
`PCB Skew....................................................................................................... 209
`Receiver Setup and Hold times........................................................................ 209
`
`Transfer Timing Example................................................................................ 210
`
`L Detailed Phase Recovery Timing Budget ...................................................................... 211
`L.1
`System Reference Clock Uncertainties ............................................................ 211
`L.2
`Transmitter CLKOUT Uncertainties................................................................ 212
`
`L.2.1
`L.2.2
`
`L.2.3
`L.3
`
`L.3.1
`L.3.2
`
`Transmitter PLL Variations............................................................................. 212
`Transmitter and Link Transfer Variations........................................................ 213
`
`Transmitter Cross Byte Lane Variations .......................................................... 214
`Receiver CLKIN Uncertainties........................................................................ 215
`
`Receiver PLL Variations ................................................................................. 215
`Receiver Transfer Variations........................................................................... 215
`
`L.4
`
`CADIN/CTLIN Sampling Error ...................................................................... 216
`
`M Combining Voltage and Transfer Characteristics........................................................ 217
`
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`Ex. 1043, Page 11
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`HyperTransport
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` Technology Consortium
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`Revision 1.03
`
`List of Figures
`
`Figure 1.
`
`Figure 2.
`Figure 3.
`
`Figure 4.
`Figure 5.
`
`Figure 6.
`Figure 7.
`
`Figure 8.
`Figure 9.
`
`Figure 10.
`Figure 11.
`
`Figure 12.
`Figure 13.
`Figure 14.
`
`Figure 15.
`Figure 16.
`
`Figure 17.
`Figure 18.
`
`Figure 19.
`Figure 20.
`
`Figure 21.
`Figure 22.
`
`Figure 23.
`Figure 24.
`
`Figure 25.
`Figure 26.
`
`Figure 27.
`
`HyperTransport™ I/O Link .................................................................................19
`
`Example Device Configurations ..........................................................................34
`Example Topologies............................................................................................34
`
`Example Data Buffer Sizing Calculation .............................................................49
`Receive FIFO ....................................................................................................120
`
`Sync Sequence Ti