(12) United States Patent
`Helms et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,146.510 B1
`Dec. 5, 2006
`
`USOO714651OB1
`
`(54) USE OF A SIGNAL LINE TO ADJUST WIDTH
`AND/OR FREQUENCY OF A
`COMMUNICATION LINK DURING SYSTEM
`OPERATION
`
`(75) Inventors: Frank P. Helms, Round Rock, TX
`(US); Derrick R. Meyer, Austin, TX
`(US); Larry D. Hewitt, Austin, TX
`(US); Dale E. Gulick, Austin, TX (US);
`William A. Hughes, Burlingame, CA
`(US); Scott E. Swanstrom, San Jose,
`CA (US)
`(73) Assignee: Advanced Micro Devices, Inc.,
`Sunnyvale, CA (US)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 533 days.
`Appl. No.: 10/198,637
`
`(21)
`(22)
`
`Filed:
`
`Jul. 18, 2002
`
`Related U.S. Application Data
`(63) Continuation-in-part of application No. 10/185.195,
`filed on Jun. 28, 2002, now Pat. No. 7,051.218.
`Provisional application No. 60/306,361, filed on Jul.
`18, 2001.
`
`(60)
`
`(51)
`
`(52)
`(58)
`
`(56)
`
`Int. C.
`(2006.01)
`G06F I/26
`(2006.01)
`G06F I/32
`U.S. Cl. ....................................... 713/300; 713/320
`Field of Classification Search ................ 713/300,
`713/322, 400, 320
`See application file for complete search history.
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,710,922 A 12, 1987 Scott
`4,958,344 A
`9, 1990 Scott
`5,255,374. A 10/1993 Aldereguia et al.
`5,280,598 A *
`1/1994 Osaki et al. ................ T10/310
`5,349,693. A
`9, 1994 Matsushita
`
`(Continued)
`FOREIGN PATENT DOCUMENTS
`
`EP
`
`1146429
`
`10, 2001
`
`OTHER PUBLICATIONS
`“HyperTransportTM I/O Link Specification.” HyperTransport Tech
`nology Consortium, Revision 1.03, Oct. 10, 2001, pp. 1-217.
`(Continued)
`Primary Examiner Thomas Lee
`Assistant Examiner Ji H. Bae
`(74) Attorney, Agent, or Firm—Zagorin O'Brien Graham
`LLP
`
`(57)
`
`ABSTRACT
`
`An integrated circuit is coupled to a communication link and
`to a separate signal line and includes programmable registers
`specifying communication link width and frequency. The
`integrated circuit responds to a change in the value of the
`signal line by changing the width and/or frequency of at least
`a portion of the communication link to the programmed
`value in response to a change in a logical value of the signal
`line, without the integrated circuit entering a reset state. The
`width and/or frequency may be changed during a POST
`routine or during system operation as part of a power
`management or other system function while maintaining its
`operational state.
`
`4,633,437 A * 12/1986 Mothersole et al. .......... 71 Of74
`
`16 Claims, 8 Drawing Sheets
`
`
`
`CTL
`
`304
`
`306
`
`PROCESSOR
`2O a
`
`PROCESSOR
`2O1b
`
`CAD (n:O
`
`312
`
`Intel Corporation v. ACQIS LLC
`Intel Corp.'s Exhibit 1044
`Ex. 1044, Page 1
`
`

`

`US 7,146.510 B1
`Page 2
`
`U.S. PATENT DOCUMENTS
`Kobayashi et al.
`Shah et al.
`Kishigami .................. 710,307
`Carmean et al. ............ T13/601
`Titus et al.
`Weiss et al. ................ T13,501
`Hu et al. .......
`... 713,320
`Gupta et al. ...
`... 713,322
`Bacigalupo et al. ........ TO9,208
`Zeller et al.
`Edwards et al. ............ T13/400
`Enns et al.
`Totsuka et al. ............. T13,323
`Shoobe et al.
`Cohen et al.
`
`2, 1995
`10, 1995
`3, 1997
`5, 1997
`6, 1998
`6, 1998
`11, 1999
`11, 1999
`2, 2000
`8, 2001
`T/2003
`12, 2003
`3, 2004
`4, 2004
`5, 2004
`
`5,394,528
`5,461,723
`5,613,078
`5,630, 107
`5,761.456
`5,774,703
`5,987,617
`5.996,083
`6,032,178
`6,282,662
`6,591.369
`6,658,010
`6,715,090
`6,725,310
`6,738,068
`
`
`
`2003/0088799 A1
`2006,0041704 A1
`
`5/2003 Bodas ........................ T13,320
`2, 2006 Choi
`
`OTHER PUBLICATIONS
`“HyperTransportTM Technology I/O Link.” Advanced Micro
`Devices, Inc., Jul. 20, 2001, pp. 1-25.
`U.S. Appl. No. 10/185,171, filed Jun. 28, 2002, entitled “Message
`Based Power Management in a Multi-Processor System” by Frank
`P. Helms, et al.
`U.S. Appl. No. 10/185.195, filed Jun. 28, 2002, entitled “Message
`Based Power Management” by Dale E. Gulick, et al.
`U.S. Appl. No. 10/647,397, filed Aug. 25, 2003 entitled “Config
`uring a Communication Link Interface,” naming inventors Larry D.
`Hewitt and Dale E. Gulick, (109 pages).
`* cited by examiner
`
`Ex. 1044, Page 2
`
`

`

`U.S. Patent
`
`Dec. 5, 2006
`
`Sheet 1 of 8
`
`US 7,146.510 B1
`
`103
`
`PROCESSOR
`
`DDR
`DIMMs
`
`101(a) -1
`
`I/O LINK
`
`TUNNEL WITH
`AGP INTERFACE
`
`102
`
`AGP
`
`I/O LINK
`101(b) -1
`I/O HUB
`
`
`
`AGP
`CARD FOR DESKTOPS
`MOTHERBOARD DEVICE
`FOR MOBILES
`
`o IDE
`a USB
`o MAC
`o AC97
`o SMBUS
`
`LPC
`
`LPC
`SUPER I/O
`
`CARDBUS
`MOBILE ONLY
`
`PCBUS 1
`(BUS OFOR
`MOBILE)
`
`104.
`
`F.G. 1
`
`Ex. 1044, Page 3
`
`

`

`U.S. Patent
`
`Dec. 5, 2006
`
`Sheet 2 of 8
`
`US 7,146.510 B1
`
`2O2C
`DDR
`DIMMs
`
`201c / 205c - 201d
`DDR, PROCESSOR
`PROCESSORDDR. DDR
`DIMMS
`1205c
`
`202d
`
`205b -
`201a
`29- 205a
`202b
`DDR
`DDR, PROCESSOR
`PROCESSORDDR, DDR
`DIMMs
`DIMMs
`(COHERENT PROTOCOLFABRIC)
`(I/O PROTOCOLFABRIC)
`N-206
`PCI-X (BUS 3)
`
`PCI-X (BUS 2)
`
`2O7
`
`REQ#
`
`STOPH
`
`204
`
`202a
`
`TUNNEL WITH
`PCI-X BRIDGES
`1 208
`
`LPC
`SUPERI/O
`
`LPC
`
`PC (BUS 1)
`
`
`
`I/O HUB
`
`IDE
`USB
`MAC
`AC97
`SMBUS
`
`FIG. 2
`
`Ex. 1044, Page 4
`
`

`

`U.S. Patent
`
`Dec. 5, 2006
`
`Sheet 3 of 8
`
`US 7,146.510 B1
`
`
`
`PROCESSOR
`20 a
`
`PROCESSOR
`201b.
`
`I/O HUB
`204
`
`TUNNEL
`2O7
`
`FIG. 4
`
`Ex. 1044, Page 5
`
`

`

`U.S. Patent
`
`Dec. 5, 2006
`
`Sheet 4 of 8
`
`US 7,146.510 B1
`
`/09
`
`
`
`
`
`
`
`
`
`
`
`HOSSEO08d
`
`Ex. 1044, Page 6
`
`

`

`U.S. Patent
`
`Dec. 5, 2006
`
`Sheet 5 of 8
`
`US 7,146.510 B1
`
`Nkwothout LNWOHN MLNWDHOUT MAXLINKWDTHIN
`
`FIG. 6A
`
`
`
`
`
`
`
`LINK WIDTH2O)
`
`001
`
`010
`
`011
`
`100
`
`111
`
`
`
`
`
`
`
`
`
`
`
`WDTH
`
`RESERVED
`
`32 BITS
`
`2 BITS
`
`4. BITS
`
`RESERVED
`
`
`
`LINK NOT PHYSICALLY
`
`CONNECTED
`
`FIG. 6B
`
`Ex. 1044, Page 7
`
`

`

`U.S. Patent
`
`Dec. 5, 2006
`
`Sheet 6 of 8
`
`US 7,146.510 B1
`
`
`
`LINKFREQUENCY ENCODING
`
`TRANSMITTER CLOCKFREQUENCY (MHZ)
`
`0000
`
`0001
`
`OO 10
`
`200 (DEFAULT)
`
`300
`
`400
`
`O 111 TO 1110
`
`1111
`
`RESERVED
`
`WENDOR-SPECIFIC
`
`FIG. 6C
`
`Ex. 1044, Page 8
`
`

`

`U.S. Patent
`
`Dec. 5, 2006
`
`Sheet 7 of 8
`
`US 7,146.510 B1
`
`1.
`
`7s ke
`
`
`
`| 6 || 5
`
`SeqId3:2)
`SeqId1:0
`Count1:0
`
`4
`
`2
`
`Cmd5:0)
`UnitID4:0
`Reserved
`
`1
`
`o
`
`RSV
`SysMgtCmd7:0
`Addr23:20
`
`Count3:2)
`
`RSV
`
`Addr31:24
`Addr39:32)
`
`FIG. 7A
`
`IE
`
`1.
`
`SeqId3:2)
`PaSSPW
`
`| 5 |
`
`|
`
`|
`
`| | |
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIG. 7B
`
`Ex. 1044, Page 9
`
`

`

`U.S. Patent
`
`Dec. 5, 2006
`
`Sheet 8 of 8
`
`US 7,146.510 B1
`
`I/O HUB
`
`HOST BRIDGE
`
`PROCESSORS
`
`801
`
`CONDITION
`DETECTED
`
`803
`
`YES
`
`SEND STPCLKMSG 1
`TO HOSTBRIDGE
`
`807
`
`
`
`
`
`NO
`
`809
`
`813
`
`
`
`BROADCAST SYSTEM
`STPCLK MGT MSG TO
`PROCESSOR(S)
`
`RESPONSE
`RECEIVED FROMALL
`PROCESSORSP
`
`YES
`
`
`
`BROADCAST STPCLK
`MSGTOI/O LINKS
`
`
`
`
`
`
`
`
`
`RECEIVE
`SYSTEMMGT
`STOPGRANT
`MSG
`
`835
`
`ASSERT
`STOPH:
`
`
`
`NO
`
`BROADCAST STOPGRANT
`SYSTEMMGT MSG TO
`PROCESSOR(S)
`
`a
`
`
`
`e
`
`827
`
`
`
`
`
`RESPONSE
`FROMALL
`PROCESSORS
`
`Y-------
`
`
`
`
`
`BROADCAST
`STOPGRAN SYSTEM
`MGTMSGTOI/O LINK
`
`ENTER
`STOPGRANT
`STATE
`
`
`
`SEND STOPGRANT
`MSG TO
`HOSTBRIDGE
`
`STOPGRANT
`SYSTEM MGT
`MSG RECEIVED?
`
`FIG. 8
`
`Ex. 1044, Page 10
`
`

`

`1.
`USE OF A SIGNAL LINE TO ADJUST WIDTH
`AND/OR FREQUENCY OF A
`COMMUNICATION LINK DURING SYSTEM
`OPERATION
`
`CROSS-REFERENCE TO RELATED
`APPLICATION(S)
`
`This application is a continuation-in-part of U.S. patent
`application Ser. No. 10/185,195, filed Jun. 28, 2002 now
`U.S. Pat. No. 7,051,218, entitled “Message Based Power
`Management, listing Dale E. Gulick et al. as inventors,
`which claims the benefit under 35 U.S.C. S 119(e) of
`provisional application 60/306,361, filed Jul. 18, 2001. This
`application also claims the benefit under 35 U.S.C. S 119(e)
`of provisional application 60/306,361, filed Jul. 18, 2001.
`
`15
`
`BACKGROUND
`
`25
`
`30
`
`40
`
`45
`
`1. Field of the Invention
`The invention relates to computer systems and more
`particularly to controlling the width and/or frequency of
`communication links used in computer systems.
`2. Description of the Related Art
`Power consumption and associated performance and ther
`mal issues are considerations for every computer system
`design. Many power saving techniques have been intro
`duced to save power and mitigate the impact of thermal and
`battery power constraints. The frequency of operation (clock
`frequency) of the processor and its operating Voltage can in
`large part determine its power consumption. Since power
`consumption and therefore heat generation are roughly
`35
`proportional to the processors frequency of operation, Scal
`ing down the processors frequency has been a common
`method of staying within appropriate power limitations.
`Microprocessors utilized in mobile applications, i.e., those
`used in battery powered systems, are particularly sensitive to
`power considerations. That is in part due to the Small,
`densely packed system construction that limits the ability of
`the mobile computer system to dissipate the heat generated
`by computer operation.
`While power consumption issues are particularly impor
`tant for portable computers, power consumption issues are
`important for all types of computers. For example, while
`battery life may not be a consideration for desktop comput
`ers, thermal considerations are still an important criteria. In
`particular, for desktop computers, the hotter they run, the
`more likely fans are turned on to try and cool the processor,
`which results in fan noise or frequent cycling of the fans,
`which may be objectionable to the computer user. In addi
`tion, saving power can have real economic benefits in terms
`of reduced electricity costs. Further, reduced power con
`Sumption and lower operating temperatures can improve
`system reliability. Reduced power consumption and lower
`operating temperatures can also allow for higher density
`server farms.
`It would be advantageous to be able to control the width
`and frequency of communication links in a computer system
`both to provide power management capability as well as to
`provide flexibility in System design and configuration. It
`would be further desirable to be able to adjust width and
`frequency of communication links while the system remains
`in an operational state.
`
`50
`
`55
`
`60
`
`65
`
`US 7,146,510 B1
`
`2
`SUMMARY
`
`Accordingly, in one embodiment, the invention provides
`a method for a device coupled to a communication link and
`coupled to a signal line. The method includes changing a
`width of at least a portion of the communication link to a
`desired width in response to a change in a logical value of
`the signal line without the device entering a reset state. The
`width may be changed during a POST routine or as part of
`a power management function. The method may further
`include changing a frequency of operation of at least a
`portion of the communication link to a desired frequency in
`response to the change in the logical value of the signal line
`without the device entering a reset state.
`In another embodiment, the invention provides a com
`puter system that includes a first integrated circuit coupled
`to a communication link. A control signal is coupled to the
`integrated circuit, which includes a first programmable reg
`ister specifying a width of a data portion of the communi
`cation link. The first integrated circuit is responsive to a
`change in logic levels assertion of the control signal to adjust
`the width of the data portion of the communication link
`according to a value of the first programmable register. The
`first integrated circuit adjusts the width of the data portion
`while maintaining its operational state.
`The first integrated circuit may include a second program
`mable storage location specifying a frequency of operation
`of the communication link. The integrated circuit responds
`to a change in the logical value of the control signal to adjust
`the frequency of the communication link according to a
`value of the second programmable storage location. The first
`integrated circuit adjusts the frequency of the data portion
`while maintaining its operational state.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention may be better understood, and its
`numerous objects, features, and advantages made apparent
`to those skilled in the art by referencing the accompanying
`drawings.
`FIG. 1 illustrates a single processor System configuration
`capable of utilizing one or more embodiments of the present
`invention.
`FIG. 2 illustrates a multi-processor system configuration
`capable of utilizing one or more embodiments of the present
`invention.
`FIG. 3 illustrates details of an exemplary coherent link
`shown in FIG. 2.
`FIG. 4 illustrates details of an exemplary non-coherent or
`I/O link shown in FIG. 2.
`FIG. 5A illustrates a host bridge incorporated into the
`processor integrated circuit to Support memory coupled
`directly to the processor.
`FIG. 5B illustrates use of an external host bridge to
`Support memory coupled to a chipset integrated circuit.
`FIG. 6A illustrates a link configuration register having
`fields specifying the width of the link.
`FIG. 6B illustrates the encoding for width fields in the link
`configuration register.
`FIG. 6C illustrates the encoding for 4 bit frequency
`register that controls the frequency utilized by the transmit
`clock.
`FIG. 7A shows a format of an exemplary system man
`agement message sent by the I/O hub upstream to the
`hostbridge.
`FIG. 7B illustrates a format of an exemplary system
`management message sent by the hostbridge downstream.
`
`Ex. 1044, Page 11
`
`

`

`US 7,146,510 B1
`
`3
`FIG. 8 illustrates a flow diagram of operation of the stop
`clock/stop grant protocol according to an embodiment of the
`invention used to cause system power state changes.
`The use of the same reference symbols in different draw
`ings indicates similar or identical items.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT(S)
`
`4
`The input output (I/O) hub 104 provides much of the
`functionality provided in prior art systems by the south
`bridge component of the chipset Supporting processor opera
`tions. For example, the I/O hub provides access to devices
`of Such exemplary interfaces and/or buses as Intelligent
`Drive Electronics (IDE), Universal Serial Bus (USB), Media
`Access Control Controller (MAC), AC97, SMBus, Low Pin
`Count (LPC) bus, and PCI bus. Additional interfaces, in
`addition to or instead of those shown may of course be
`utilized. Thus, typical I/O functions may be accessed by the
`processors through the I/O hub 104. Note that a south bridge
`can be utilized to support embodiments of the invention
`described herein. As shown in FIG. 1, the communication
`links 101a and 101b may be part of a daisy chained point to
`point interconnection where one device passes on anything
`not intended for that device either upstream (towards the
`hostbridge) or downstream (away from the hostbridge).
`FIG. 2 shows a block diagram of a multi-processor system
`that can advantageously utilize the link configuration capa
`bilities described herein. The multi-processor system
`includes respective processors 201a–201d coupled to
`respective memories 202a-202d. Each of the processors is
`connected by a communication link 205a–205d to other
`processors. The communication links coupling the processor
`Support the ability to maintain appropriate coherency
`between the various memories 202a-202d and the cache
`memories of processor 201a through 201d in a multi
`processor environment. In addition, processor 201a is
`coupled to the tunnel integrated circuit 207 through I/O link
`206. Thus the processors access I/O devices (and vice versa)
`through the processor integrated circuit 201a. The I/O Hub
`204 is coupled to the tunnel chip 207 through an I/O link
`208. Note that the I/O links are generally assumed to not be
`a part of the coherent fabric.
`Details of an exemplary embodiment of the link formed
`by links 205a–205d and the link formed by links 206 and
`208 are shown respectively in FIGS. 3 and 4. FIG.3, a block
`diagram with processors 201a and 201b, illustrates one
`embodiment of the coherent link in more detail. Other
`embodiments are possible and contemplated. In the embodi
`ment of FIG. 3, the coherent link is shown to include two
`sets of unidirectional lines. Clock line 302, a control line
`304, and a control/address/data bus 306 are the first set of
`unidirectional lines coupled between the processors. Simi
`larly, the other unidirectional portion of the link includes
`clock line 308, a control line 310, and control/address/data
`(CAD) bus 312.
`The clock line of the coherent link may transmit a clock
`signal that indicates a sample point for the control line and
`the CAD bus. In one particular embodiment, data/control
`bits may be transmitted on each edge (i.e. rising edge and
`falling edge) of the clock signal. Accordingly, two data bits
`per line may be transmitted per clock cycle. The amount of
`time employed to transmit one bit per line is referred to
`herein as a “bit time'. The above-mentioned embodiment
`includes two bit times per clock cycle. A coherent packet
`may be transmitted across two or more bit times. Multiple
`clock lines may be used depending upon the width of the
`control/address/data bus. For example, four clock lines may
`be used for a 32 bit control/address/data bus, one for each
`eight bit portion.
`The control line may indicate whether or not the data
`transmitted upon the control/address/data bus is either a bit
`time of a coherent control packet or a bit time of a coherent
`data packet. The control line, in one embodiment, may be
`asserted to indicate a coherent control packet, and deasserted
`
`15
`
`25
`
`10
`In accordance with the present invention, the width and/or
`frequency of one or more communication links of a com
`puter system is adjustable. During a power-on sequence or
`after a reset operation, a width and/or frequency is initially
`set for each of the communication links that have Such
`capability. In addition, in order to provide enhanced flex
`ibility, that can be utilized, for example by power manage
`ment, or for fault tolerance, the width and/or frequency can
`also be adjusted during system operation.
`During the power-up sequence or after a system reset
`resulting from a power-on sequence or other system event
`resulting in a reset condition, the microprocessor(s) in the
`computer system execute initialization code that is typically
`stored in an external Read-Only Memory (ROM). That code
`is referred to as Basic Input Output System (BIOS) code.
`The BIOS is responsible for system level operations such as
`initializing and testing the system hardware Such as the
`microprocessor(s), memory, and other hardware compo
`nents. That portion of BIOS code is known as Power On Self
`Test (POST).
`30
`One task that can be accomplished during the POST
`routine as part of the hardware initialization configuration is
`to configure the various communication links in the system
`(that can be configured) for width and/or frequency. During
`system operation, and during the POST routine, using a
`mechanism other than a reset to adjust width and/or fre
`quency allows the width/frequency change to occur without
`the computer system entering a reset state during the recon
`figuration to the new width and/or frequency. If a reset was
`required in order to establish the width or frequency of a
`communication link during the POST routine, that could
`cause the POST routine to execute again from the beginning,
`resulting in extra time spent to complete the POST routine.
`In addition, if a reset were required in order to accomplish
`a change in link width or frequency after the POST routine,
`that is during normal system operation, Such changes during
`system operation would be complicated and time consum
`ing, requiring, e.g., Saving System state prior to adjusting
`width and frequency. Use of a control signal separate from
`a reset signal to effect changes in link width and/or link
`frequency as described herein allows the configuration to
`occur without entering a reset state.
`The link width/frequency configuration capabilities dis
`cussed herein are applicable to uni-processor (1P) or multi
`processor (MP) systems as well other electronic systems
`utilizing a communication link capable of configuration with
`respect to width and/or frequency. FIG. 1 provides a block
`diagram of an exemplary uni-processor system suitable for
`exploiting the link configuration capabilities described
`herein. The input/output (I/O) links 101a and 101b couple
`processor 103 through tunnel integrated circuit 102 to the
`I/O hub integrated circuit 104 and thus to input/output
`devices. In the illustrated embodiment, the tunnel integrated
`circuit 102 provides an Accelerated Graphics Port (AGP)
`interface to AGP functionality that may be implemented as
`a separate graphics card in a desktop system or may be
`implemented as a motherboard device in a mobile system.
`
`50
`
`35
`
`40
`
`45
`
`55
`
`60
`
`65
`
`Ex. 1044, Page 12
`
`

`

`US 7,146,510 B1
`
`10
`
`15
`
`25
`
`30
`
`35
`
`5
`to indicate a coherent data packet. Certain coherent control
`packets may indicate that a coherent data packet follows.
`The coherent data packet may immediately follow the
`corresponding coherent control packet. In one embodiment,
`other coherent control packets may interrupt the transmis
`sion of a coherent data packet. Such an interruption may be
`performed by asserting the control line for a number of bit
`times during transmission of the coherent data packet and
`transmitting the bit times of the coherent control packet
`while the control line is asserted. Coherent control packets
`which interrupt a coherent data packet may not indicate that
`a coherent data packet will be following.
`The control/address/data bus comprises a set of lines for
`transmitting data/control bits. In one embodiment, the con
`trol/address/data bus may comprise different width of e.g., 8,
`16, or 32 lines. Each coherent link may employ any one of
`the Supported numbers of lines according to design choice.
`Other embodiments may support other sizes of control/
`address/data bus as desired.
`According to one embodiment, the command/address/
`data bus lines and the clock line carry inverted data (i.e. a
`logical one is represented as a low Voltage on the line, and
`a logical Zero is represented as a high voltage). Alternatively,
`lines may carry non-inverted data (in which a logical one is
`represented as a high voltage on the line, and logical Zero is
`represented as a low Voltage). Note the lines may also be
`implemented as differential rather than single ended signals.
`Turning next to FIG. 4, a block diagram with I/O Hub
`processing node 204 and tunnel 207 is shown to illustrate
`one embodiment of the non-coherent link in more detail.
`Other embodiments are possible and contemplated. In the
`embodiment of FIG. 4, the I/O link is similar to the coherent
`link and includes two sets of unidirectional lines. Clock line
`440, a control line 442, and a control/address/data bus 444
`are the first set of unidirectional lines coupled between the
`nodes. Similarly, the other unidirectional portion of the link
`includes clock line 446, a control line 448, and a control/
`address/data bus 449.
`Similar to the coherent link, the clock line in the non
`coherent link between a node and an I/O bridge may transmit
`40
`a clock signal that indicates a sample point for the control
`line and the control/address/data bus. In one particular
`embodiment, data/control bits may be transmitted on each
`edge (i.e. rising edge and falling edge) of the clock signal.
`Accordingly, two data bits per line may be transmitted per
`clock cycle in the non-coherent link. The amount of time
`employed to transmit one bit per line is referred to herein as
`a “bit time'. The above-mentioned embodiment may include
`two bit times per clock cycle. A non-coherent packet may be
`transmitted across two or more bit times. Multiple clock
`lines may be used depending upon the width of the control/
`address/data bus. For example, four clock lines may be used
`for a 32 bit control/address/data bus, one for each eight bit
`portion.
`The control line may indicate whether or not the data
`transmitted upon the control/address/data (CAD) bus is
`either a bit time of a non-coherent control packet or a bit
`time of a non-coherent data packet. The control line, in one
`embodiment, may be asserted to indicate a non-coherent
`control packet, and deasserted to indicate a non-coherent
`data packet. Certain non-coherent control packets may indi
`cate that a non-coherent data packet follows. The non
`coherent data packet may immediately follow the corre
`sponding non-coherent control packet. In one embodiment,
`other non-coherent control packets may interrupt the trans
`mission of a non-coherent data packet. Such an interruption
`may be performed by asserting the control line for a number
`
`50
`
`45
`
`55
`
`60
`
`65
`
`6
`of bit times during transmission of the non-coherent data
`packet and transmitting the bit times of the non-coherent
`control packet while the control line is asserted. Non
`coherent control packets which interrupt a non-coherent data
`packet may not indicate that a non-coherent data packet will
`be following.
`The control/address/data bus comprises a set of lines for
`transmitting the data/control bits. In one embodiment, the
`control/address/data bus may comprise 8, 16, or 32 lines.
`Each non-coherent link may employ any one of the Sup
`ported numbers of lines according to design choice. Other
`embodiments may support other sizes of control/address/
`data bus as desired. In addition, as described herein, the size
`of the link may be changed.
`According to one embodiment, the command/address/
`data bus lines and the clock line may carry inverted data (i.e.
`a logical one is represented as a low voltage on the line, and
`a logical Zero is represented as a high voltage). Alternatively,
`lines may carry non-inverted data (in which a logical one is
`represented as a high Voltage on the line, and logical Zero is
`represented as a low Voltage). Note the lines may also be
`implemented as differential rather than single ended signals.
`As described further herein, messages may be passed over
`the communication links described above to accomplish
`power management functions. Those power management
`messages may be utilized in adjusting the link width and/or
`frequency as described further herein. Exemplary power
`management mechanisms in Such a system include reducing
`the processor's power consumption to nearly static levels
`during Halt and Stop Grant states. Performance state man
`agement is accomplished by changing a processor register
`(VID/FID) specifying the voltage ID (VID) and frequency
`ID (FID) used by the processor as described further herein.
`Processor performance states are combinations of processor
`core Voltage and core frequency that can be dynamically
`changed during the processor working state. Exemplary
`power savings mechanisms also include providing bus
`power management such as the capability to dynamically
`stop and start the communication links during C3, S1,
`thermal throttling, and device power management during the
`C3 and S1 states. In addition, power management may
`provide software controlled reduced power device states
`(D-states and performance states) as well as hardware auto
`mated device power reduction.
`In addition to the communication link signals described
`above, systems may utilize, where appropriate, additional
`signals to facilitate power management and link width/
`frequency configuration activities. One such control signal
`can be utilized to facilitate link width and/or frequency
`adjustments. In one embodiment, one such signal is a
`LDTSTOPit signal (the # indicating an active low signal).
`The LDTSTOPit signal may be supplied as an output of the
`I/O Hub or south bridge (see FIG. 2) and an input to other
`devices coupled to the communication links. The LDT
`STOPit signal may be used for re-sizing the communication
`link width, and changing the link frequency without having
`to reset the entire system, and for power management
`functions such as stopping and tri-stating the communication
`link drivers in low power state, and changing the processor's
`core Voltage and frequency during the working state. In
`addition, the LDTSTOPit signal can be used to prevent
`probe activity while throttling the processor for thermal
`reasons. That use may be constrained by Stop Grant exit
`latency and the throttling period. In addition the LDTSTOPil
`signal can be used in controlling the processor power
`management and processor clock grids) for the I/O com
`
`Ex. 1044, Page 13
`
`

`

`US 7,146,510 B1
`
`5
`
`10
`
`15
`
`7
`munication link I/F (part of the host bridge) and the memory
`controller power management.
`A second signal that may be used in addition to the
`communication link signals described above is a request
`(REQ#) signal, which is an input to the I/O Hub and an
`optional open drain output of devices on the communication
`link except for the processor(s). A device asserts the REQi
`signal whenever it has a transaction outstanding in the
`communication link fabric, or when it needs to initiate a new
`transaction into the communication link fabric. The REQi
`signal provides the functionality of enabling bus masters to
`bring the processor out of the C3 state. AGP masters may
`assert REQi for any access which would cause the processor
`caches to be probed. For notebooks, integrated graphics/
`northbridge/memory controllers should not assert REQi for
`accesses to memory which are non-cached, like accesses to
`the frame buffer for display refresh assuming the frame
`buffer is local, not remote across a link.
`Thus, in one embodiment when REQi is asserted, the I/O
`Hub sets the bus master status (BM STS) bit in the industry
`standard ACPI PM1 Status register. In addition, the I/O hub
`de-asserts the LDTSTOPH signal if it was asserted for the
`ACPI C3 state. The I/O Hub brings the processor out of the
`C3 state if currently in C3 and the BM RLD bit in the ACPI
`PM1 control register, which determines if the Cx power state
`is exited upon a request from a bus master, is set in response
`to the REQi signal being asserted by one of the devices.
`Referring again to FIG. 2, processor 201(a) includes a
`host bridge function that bridges between the coherent
`communication link protocol used by the processor(s) on
`links 205a–205d and the I/O protocol in the communication
`link connecting the rest of the devices in the system. In one
`possible configuration, shown in FIG. 5A, the host bridge
`501 is located on the processor 503 and interfaces to the I/O
`communication link. That configuration may be used, e.g., in
`a system where system memory 507 is connected to pro
`cessor. Note that the embodiments discussed herein gener
`ally assume the host bridge is located in the processor
`coupled to the I/O link. However, the concepts discussed are
`valid for an external host bridge located in an integrated
`circuit Such as the north bridge component of a chipset as
`shown in FIG. 5B to allow for chipset control of system
`memory.
`In one embodiment, a link configuration register exists for
`each link present on a device. As explained further herein,
`software updates may be utilized to adjust the width of the
`link. Those updates take effect after a warm reset sequence
`described further herein and, depending on the field, also
`after an LDTSTOPit disconnect sequence described further
`herein. In one embodiment, the system utilizes a cold and a
`warm reset. During a cold reset, all configuration and control
`bits take their appropriate predetermined values. During a
`warm reset, certain configuration/control bits may be
`defined to be persistent and not be affected during a warm
`reset. However, the machine state is changed during a warm
`reset.
`The link configuration register includes, as shown in FIG.
`6A, a 3 bit field (Link WidthOut) specifying the width of the
`of the CAD lines transmitted by the device and a 3 bit field
`(Link Width In) that specifies the width of the CAD lines
`received by the device. In addition, the configuration register
`specifies a maximum link width (MaxLink WidthOut) for
`transmitted CAD lines and a maximum link width (Max
`Link Width In) for received CAD lines, both three bit fields.
`The exemplary maximum link width field can encode up to
`eight widths. FIG. 6B shows for one embodiment, the
`
`8
`encoding for the maximum and programmable link width
`fields shown in FIG. 6A for both incoming and outgoing
`CAD lines.
`The maximum link width field specifies the physical
`width of the link as implemented by the device. Note th