intel® 82559 Fast Ethernet* Multifunction PCI/
`
`Cardbus Controller
`Networking Silicon
`
`Preview Datasheet
`
`Product Features
`
`111 Optimum Integration for Lowest Cost
`Solution
`-
`Integrated IEEE 802.3 lOBASE-T and
`lOOBASE-TX compatible PHY
`-Glueless 32-bit PCI master interface
`-Glueless CardBus master interface
`- Modem interface for combination
`solutions in CardBus designs
`-128 Kbyte Flash interface
`-
`Integrated power management functions
`- Thin BGA 15mm2 package
`111 Wired for Management and Reduced Total
`Cost of Ownership
`- Wired for Management support
`-System Management Bus support for
`Total Cost of Ownership support
`- Power management capabilities
`-ACPI and PCI Power Management
`standards compliance
`- Wake on "interesting" packets and link
`status change support
`- Magic Packet* support
`- Remote power up support
`
`-
`
`111 High Performance Networking Functions
`-Chained memory structure similar to the
`82558, 82557, and 82596
`Improved dynamic transmit chaining
`with multiple priorities transmit queues
`- Backward compatible software to the
`82558 and 82557
`- Full Duplex support at both 10 and 100
`Mbps
`-IEEE 802.3u Auto-Negotiation support
`-3 Kbyte transmit and 3 Kbyte receive
`FIFOs
`-Fast back-to-back transmission support
`with minimum interframe spacing
`-IEEE 802.3x lOOBASE-TX Flow
`Control support
`-Adaptive Technology
`-TCP/UDP checksum offload capabilities
`111 Low Power Features
`-Low power 3.3 V device
`- Efficient dynamic standby mode
`- Deep power down support
`-Clockrun protocol support
`
`Notice: This document contains information on products in the design phase of development. Do
`not finalize a design with this information. Revised information will be published when the product
`is available. Verify with your local Intel sales office that you have the latest datasheet before finaliz(cid:173)
`ing a design.
`
`Document Number:
`Revision 1 .0
`January 1999
`
`Intel Corporation v. ACQIS LLC
`Intel Corp.'s Exhibit 1047
`Ex. 1047, Page 1
`
`

`

`82559 - Networking Silicon
`
`Revision History
`
`Revision
`Date
`
`Revision
`
`Description
`
`Jan. 1999
`
`1.0
`
`First release.
`
`Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
`property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
`whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
`fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
`intended for use in medical, life saving, or life sustaining applications.
`
`Intel may make changes to specifications and product descriptions at any time, without notice.
`
`Desif;ni:::r·s must not reiy on t~1e absence or characteristics of any features ot· instruct:ons marked ''reserved'' or "uncjef:ned." intel reserves these ior
`future definiiion and shaii have no respons:t)ii:ty wha:tsoever for c:onfi:cts or· incornpat:b:i:ties ari2;:n·J frorn future ,::J1anfws to H1ern.
`
`The 825.'.:lf.J may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
`characterized errata are avai!abie on request.
`
`Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
`
`Copyright@ Intel Corporation, 1999
`
`* Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.
`
`** Third-party brands and names are the property of their respective owners.
`
`ii
`
`Preview Datasheet
`
`Ex. 1047 Page 2
`
`

`

`Networking Silicon - 82559
`
`Contents
`
`1.0
`
`2.0
`
`INTRODUCTION ............................................................................................................................. 1
`1 .1
`82559 Overview .................................................................................................................. 1
`1.2 Features, Enhancements, and Changes to the 82559 from the 82558 .............................. 1
`
`82559 ARCHITECTURAL OVERVIEW .......................................................................................... 3
`2.1
`Parallel Subsystem Overview ............................................................................................. 3
`2.2 FIFO Subsystem Overview ................................................................................................. 4
`2.3
`10/100 Mbps Serial CS MA/CD Unit Overview .................................................................... 5
`2.4
`10/100 Mbps Physical Layer Unit ....................................................................................... 5
`
`3.0 SIGNAL DESCRIPTIONS ............................................................................................................... 7
`3.1
`Signal Type Definitions ....................................................................................................... 7
`3.2 PCI Bus and CardBus Interface Signals ............................................................................. 7
`3.2.1
`Address and Data Signals .................................................................................. 7
`3.2.2
`Interface Control Signals .................................................................................... 8
`3.2.3 System and Power Management Signals ........................................................... 9
`Local Memory Interface Signals ......................................................................................... 9
`3.3
`3.4 System Management Bus (SMB) Interface Signals .......................................................... 11
`3.5 Testability Port Signals ..................................................................................................... 11
`3.6 PHY Signals ..................................................................................................................... 11
`
`4.0 PCI AND CARDBUS INTERFACE ............................................................................................... 13
`4.1
`82559 Bus Operations ...................................................................................................... 13
`4.1 .1
`82559 Bus Slave Operation ............................................................................. 13
`4.1 .2
`82559 Bus Master Operation ........................................................................... 18
`4.1.3 PCI Mode Pin ................................................................................................... 21
`4.1 .4 Clockrun Signal ................................................................................................ 21
`4.1.5 Power Management Event and Card Status Change Signals .......................... 22
`4.2 PCI Power Management .................................................................................................. 22
`4.2.1
`Power States .................................................................................................... 22
`4.2.2 Wake-up Events ............................................................................................... 26
`4.3 CardBus Power Management .......................................................................................... 27
`4.4 Wake on LAN (Preboot Wake-up) .................................................................................... 27
`4.5 Parallel Flash/Modem Interface ........................................................................................ 27
`4.6 Serial EEPROM Interface ................................................................................................. 28
`4.7
`10/100 Mbps CSMA/CD Unit.. .......................................................................................... 28
`4.7.1
`Full Duplex ....................................................................................................... 28
`4.7.2
`Flow Control ..................................................................................................... 28
`4.7.3 Address Filtering Modifications ......................................................................... 29
`4.7.4 VLAN Support .................................................................................................. 29
`4.8 Media Independent Interface (MIi) Management lnterface ............................................... 29
`
`5.0
`
`82559 MODEM FUNCTIONALITY ................................................................................................ 31
`5.1
`PCI Address Mapping to the Modem ................................................................................ 31
`
`6.0
`
`82559 TCO FUNCTIONALITY ...................................................................................................... 33
`
`7.0 ELECTRICAL AND TIMING SPECIFICATIONS .......................................................................... 35
`7.1
`Absolute Maximum Ratings .............................................................................................. 35
`7.2 DC Specifications ............................................................................................................ 35
`7.3 AC Specifications ............................................................................................................. 39
`
`Datasheet
`
`iii
`
`Ex. 1047 Page 3
`
`

`

`82559 - Networking Silicon
`Contents
`
`infel.
`
`7.4 Timing Specifications ........................................................................................................ 40
`7.4.1
`PC I/Card Bus Clock Specifications ................................................................... 40
`7.4.2
`X1 Clock Specifications .................................................................................... 40
`7.4.3 Timing Parameters ........................................................................................... 41
`
`8.0 PACKAGE AND PINOUT INFORMATION ................................................................................... 49
`8.1
`Package lnformation ......................................................................................................... 49
`8.2 Pinout Information ............................................................................................................ 50
`8.2.1
`82559 Pin Assignments ................................................................................... 50
`8.2.2
`82559 Ball Grid Array Diagram ....................................................................... 52
`
`iv
`
`Product Datasheet
`
`Ex. 1047 Page 4
`
`

`

`i ntel@
`
`1.0
`
`Introduction
`
`1.1
`
`82559 Overview
`
`Networking Slllcon - 82559
`
`The 82559 is Intel's second generation fully integrated lOBASE-T/lOOBASE-TX LAN solution.
`The 82559 consists of both the Media Access Controller (MAC) and the physical layer (PHY)
`interface combined into a single component solution. The 82559 builds on the basic functionality
`of the 82558 and contains several new features and enhancements:
`
`• host-side CardBus interface
`
`• enhanced power management implementation
`
`• enhanced Total Cost of Ownership (TCO) support
`
`• optimized support for Flash device or modem interface
`
`The 32-bit PCI/CardBus controller provides enhanced scatter-gather bus mastering capabilities and
`enables the 82559 to perform high speed data transfers over the PCI bus and CardBus. Its bus
`mastering capabilities enable the component to process high level commands and perform multiple
`operations, which lowers CPU utilization by off-loading communication tasks from the CPU. Two
`large transmit and receive FIFOs of 3 Kbyte each help prevent data underruns and overruns while
`waiting for bus accesses. This enables the 82559 to transmit data with minimum interframe spacing
`(IFS).
`
`The 82559 can operate in either full duplex or half duplex mode. In full duplex mode the 82559
`adheres with the IEEE 802.3x Flow Control specification. Half duplex performance is enhanced by
`a proprietary collision reduction mechanism.
`
`The 82559 includes a simple PHY interface to the wire transformer at rates of lOBASE-T and
`lOOBASE-TX. This enables reduction in cost, real estate and design complexity. Its Auto(cid:173)
`Negotiation capability for speed, duplex, and flow control mode reduces cost, real estate, and
`design complexity.
`
`The 82559 also includes an interface to a serial (4-pin) EEPROM and a parallel interface to a 128
`Kbyte Flash memory. The EEPROM provides power-on initialization for hardware and software
`configuration parameters. The parallel port can be used as either a Flash memory interface or an
`ISA-like interface for modem.
`
`Combined with a Total Cost of Ownership (TCO) controller, the 82559 can help reduce the total
`cost of ownership in network environments. The device includes a System Management Bus
`(SMB) interface enabling the TCO controller to communicate with a management agent on the
`network.
`
`1.2
`
`Features, Enhancements, and Changes to the 82559 from
`the 82558
`
`• Glueless 32-bit PCI bus master interface
`
`• Support for latchless Flash interface with up to 128 Kbyte of Flash addressing
`
`• Glueless CardBus master interface
`
`• Modem interface for combination solution (LAN and modem) in CardBus designs
`
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`

`82559 - Networking Silicon
`
`infel.
`
`• Low power consumption for Modem/LAN combination designs to meet CardBus power
`requirements
`
`• Compliance with Advanced Configuration and Power Interface and PCI Power Management
`standards
`
`• Support for wake-up on interesting packets and link status change
`
`• Support for remote power-up using Wake on LAN* (WOL) technology
`
`• Deep power-down mode support
`
`• Support of Total Cost of Ownership (TCO) management interface and Wired for Management
`(WfM)
`
`• Backward compatible software with 82558 and 82557
`
`• TCP/UDP checksum offload capabilities
`
`• Support for Intel's Adaptive Technology
`
`The following is a list of changes that were made from the 82558 B-step Fast Ethernet Controller to
`the 82559 Fast Ethernet Controller.
`
`• The 82559 uses a 3.3 V power supply.
`
`• Individual Address, Multicast Address, and ARP wake-up events were merged into extended
`programmable wake-up packet command and removed from the CSMA command.
`
`• Receive collision bit in the RFD status word is replaced with a TCO indication bit.
`
`• The 82559 implements an SMB port to support TCO management interface.
`
`• The PHY identifier in MII register 3 was changed.
`
`• External PHY support removed.
`
`• PHY based flow control removed (802.3x flow control was not removed).
`
`2
`
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`

`i ntel@
`
`Networking Slllcon - 82559
`
`2.0
`
`82559 Architectural Overview
`
`Figure 1 is a high level block diagram of the 82559. It is divided into five main subsystems: a
`parallel subsystem, a FIFO subsystem, the Total Cost of Ownership (TCO) subsystem, the 10/100
`Mbps Carrier-Sense Multiple Access with Collision Detect (CSMA/CD) unit, and the 10/100 Mbps
`physical layer (PHY) unit.
`
`Local Memory/
`Modem Interface
`
`t
`
`PCI Target and
`Flash/Modem/EEPROM
`Interface
`
`SMB
`Interface
`
`t
`
`SMB
`Interface
`
`3 Kbyte
`Tx FIFO
`
`Four Channel
`Addressing Unit -
`DMA
`
`PCI/
`Card Bus
`Interface
`
`.------.
`
`PCI Bus
`Interface Unit
`(BIU)
`
`Micro-
`machine
`
`FIFO Control
`
`10/100 Mbps
`CSMA/CD
`
`1 OOBASE-TX/
`10BASE-T
`PHY
`
`~ TPE
`Interface
`
`Data Interface Un it
`(DIU)
`
`Dual
`Ported
`FIFO
`
`3 Kbyte
`Rx FIFO
`
`Figure 1. 82559 Block Diagram
`
`2.1
`
`Parallel Subsystem Overview
`
`The parallel subsystem is broken down into several functional blocks: a PCI bus master interface, a
`micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/
`Flash/EEPROM/Modem interface. The parallel subsystem also interfaces to the FIFO subsystem,
`passing data (such as transmit, receive, and configuration data) and command and status
`parameters between these two blocks.
`
`The dual function modem and PCI bus master interface provides a complete glueless interface to a
`PCI bus and is compliant with the PCI Bus Specification, Revision 2.1. The 82559 provides 32 bits
`of addressing and data, as well as the complete control interface to operate on a PCI bus. As a PCI
`target, it follows the PCI configuration format which allows all accesses to the 82559 to be
`automatically mapped into free memory and I/0 space upon initialization of a PCI system. For
`processing of transmit and receive frames, the 82559 operates as a master on the PCI bus, initiating
`zero wait state transfers for accessing these data parameters.
`
`The 82559 Control/Status Register Block is part of the PCI target element. The Control/Status
`Register block consists of the following 82559 internal control registers: System Control Block
`(SCB), PORT, Flash Control, EEPROM Control, Modem Control and Management Data Interface
`(MDI) Control.
`
`The micromachine is an embedded processing unit contained in the 82559 that enables Adaptive
`Technology. The micromachine accesses the 82559 microcode ROM working its way through the
`opcodes (or instructions) contained in the ROM to perform its functions. Parameters accessed from
`memory such as pointers to data buffers are also used by the micromachine during the processing
`of transmit or receive frames by the 82559. A typical micromachine function is to transfer a data
`
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`

`82559 - Networking Silicon
`
`infel.
`
`buffer pointer field to the 82559 DMA unit for direct access to the data buffer. The micromachine is
`divided into two units, Receive Unit and Command Unit which includes transmit functions. These
`two units operate independently and concurrently. Control is switched between the two units
`according to the microcode instruction flow. The independence of the Receive and Command units
`in the micromachine allows the 82559 to execute commands and receive incoming frames
`simultaneously, with no real-time CPU intervention.
`
`The 82559 contains an interface to an external Flash memory, an external serial EEPROM, and
`modem. These three interfaces are multiplexed. The Flash interface, which could also be used to
`connect to any standard 8-bit device, provides up to 128 Kbyte of addressing to the Flash. Both
`read and write accesses are supported. The Flash may be used for remote boot functions, network
`statistical and diagnostics functions, and management functions. The Flash is mapped into host
`system memory (anywhere within the 32-bit memory address space) for software accesses. It is
`also mapped into an available boot expansion ROM location during boot time of the system. More
`information on the Flash interface is detailed in Section 4.5, "Parallel Flash/Modern Interface" on
`page 27. The EEPROM is used to store relevant information for a LAN connection such as node
`address, as well as board manufacturing and configuration information. Both read and write
`accesses to the EEPROM are supported by the 82559. Information on the EEPROM interface is
`detailed in Section 4.6, ''Serial EEPROM Interface'' on page 28. The modem interface uses an ISA(cid:173)
`like signal and is described in more detail in Section 5.0, "82559 Modem Functionality" on
`page 31.
`
`2.2
`
`FIFO Subsystem Overview
`
`The 82559 FIFO subsystem consists of a 3 Kbyte transmit FIFO and 3 Kbyte receive FIFO. Each
`FIFO is unidirectional and independent of the other. The FIFO subsystem serves as the interface
`between the 82559 parallel side and the serial CSMA/CD unit. It provides a temporary buffer
`storage area for frames as they are either being received or transmitted by the 82559, which
`improves performance:
`
`• Transmit frames can be queued within the transmit FIFO, allowing back-to-back transmission
`within the minimum Interframe Spacing (IFS).
`
`• The storage area in the FIFO allows the 82559 to withstand long PCI bus latencies without
`losing incoming data or corrupting outgoing data.
`
`• The 82559 transmit FIFO threshold allows the transmit start threshold to be tuned to eliminate
`underruns while concurrent transmits are being performed.
`
`• The FIFO subsection allows extended PCI zero wait state burst accesses to or from the 82559
`for both transmit and receive frames since the transfer is to the FIFO storage area rather than
`directly to the serial link.
`
`• Transmissions resulting in errors (collision detection or data underrun) are retransmitted
`directly from the 82559 FIFO, increasing performance and eliminating the need to re-access
`this data from the host system.
`
`• Incoming runt receive frames (in other words, frames that are less than the legal minimum
`frame size) can be discarded automatically by the 82559 without transferring this faulty data to
`the host system.
`
`4
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`

`i ntel@
`
`Networking Slllcon - 82559
`
`2.3
`
`10/100 Mbps Serial CSMA/CD Unit Overview
`
`The CSMA/CD unit of the 82559 allows it to be connected to either a 10 or 100 Mbps Ethernet
`network. The CSMA/CD unit performs all of the functions of the 802.3 protocol such as frame
`formatting, frame stripping, collision handling, deferral to link traffic, etc. The CSMA/CD unit can
`also be placed in a full duplex mode which allows simultaneous transmission and reception of
`frames.
`
`2.4
`
`10/100 Mbps Physical Layer Unit
`
`The Physical Layer (PHY) unit of the 82559 allows connection to either a 10 or 100 Mbps Ethernet
`network. The PHY unit supports Auto-Negotiation for lOOBASE-TX Full Duplex, lOOBASE-TX
`Half Duplex, lOBASE-T Full Duplex, and lOBASE-T Half Duplex. It also supports three LED pins
`to indicate link status, network activity, and speed.
`
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`Ex. 1047 Page 9
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`

`

`82559 - Networking Silicon
`
`infel.
`
`6
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`Ex. 1047 Page 10
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`

`

`Networking Silicon - 82559
`
`3.0
`
`Signal Descriptions
`
`3.1
`
`Signal Type Definitions
`
`Type
`
`Name
`
`Description
`
`IN
`
`Input
`
`The input pin is a standard input only signal.
`
`OUT
`
`Output
`
`The output pin is a Totem Pole Output pin and is a standard
`active driver.
`
`T/S
`
`Tri-State
`
`The tri-state pin is a bidirectional, input/output pin.
`
`S/T/S
`
`Sustained Tri-State
`
`The sustained tri-state pin is an active low tri-state signal owned
`and driven by one agent at a time. The agent asserting the S/T/
`S pin low must drive it high at least one clock cycle before
`floating the pin. A new agent can only assert an S/T/S signal low
`one clock cycle after it has been tri-stated by the previous
`owner.
`
`0/D
`
`Open Drain
`
`The open drain pin allows multiple devices to share this signal
`as a wired-OR.
`
`A/I
`
`A/0
`
`B
`
`Analog Input
`
`The analog input pin is used for analog input signals.
`
`Analog Output
`
`The analog output pin is used for analog output signals.
`
`Bias
`
`The bias pin is an input bias.
`
`3.2
`
`PCI Bus and CardBus Interface Signals
`
`3.2.1
`
`Address and Data Signals
`
`Symbol
`
`Type
`
`Name and Function
`
`AD[31 :OJ
`
`T/S
`
`C/BE[3:0J#
`
`T/S
`
`PAR
`
`T/S
`
`Address and Data. The address and data lines are multiplexed on the
`same PCI pins. A bus transaction consists of an address phase
`followed by one or more data phases. During the address phase, the
`address and data lines contain the 32-bit physical address. For 1/0,
`this is a byte address; for configuration and memory, it is a Dword
`address. The 82559 uses little-endian byte ordering (in other words,
`AD[31 :24J contain the most significant byte and AD[7:0J contain the
`least significant byte). During the data phases, the address and data
`lines contain data.
`
`Command and Byte Enable. The bus command and byte enable
`signals are multiplexed on the same PCI pins. During the address
`phase, the C/BE# lines define the bus command. During the data
`phase, the C/BE# lines are used as Byte Enables. The Byte Enables
`are valid for the entire data phase and determine which byte lanes
`carry meaningful data.
`
`Parity. Parity is even across AD[31 :OJ and C/BE[3:0J# lines. It is stable
`and valid one clock after the address phase. For data phases, PAR is
`stable and valid one clock after either IRDY# is asserted on a write
`transaction or TROY# is asserted on a read transaction.Once PAR is
`valid, it remains valid until one clock after the completion of the current
`data phase. The master drives PAR for address and write data
`phases; and the target, for read data phases.
`
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`7
`
`Ex. 1047 Page 11
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`

`

`82559 - Networking Silicon
`
`3.2.2
`
`Interface Control Signals
`
`infel.
`
`Symbol
`
`Type
`
`Name and Function
`
`FRAME#
`
`S/T/S
`
`IROY#
`
`S/T/S
`
`TROY#
`
`S/T/S
`
`STOP#
`
`S/T/S
`
`IOSEL
`
`IN
`
`OEVSEL#
`
`S/T/S
`
`REQ#
`
`T/S
`
`GNT#
`
`IN
`
`Cycle Frame. The cycle frame signal is driven by the current master
`to indicate the beginning and duration of a transaction. FRAME# is
`asserted to indicate the start of a transaction and de-asserted during
`the final data phase.
`
`Initiator Ready. The initiator ready signal indicates the bus master's
`ability to complete the current data phase and is used in conjunction
`with the target ready (TROY#) signal. A data phase is completed on
`any clock cycle where both I ROY# and TROY# are sampled asserted
`(low) simultaneously.
`
`Target Ready. The target ready signal indicates the selected device's
`ability to complete the current data phase and is used in conjunction
`with the initiator ready (IROY#) signal. A data phase is completed on
`any clock cycle where both IROY# and TROY# are sampled asserted
`(low) simultaneously.
`
`Stop. The stop signal is driven by the target to indicate to the initiator
`that it wishes to stop the current transaction. As a bus slave, STOP# is
`driven by the 82559 to inform the bus master to stop the current
`transaction. As a bus master, STOP# is received by the 82559 to stop
`the current transaction.
`
`Initialization Device Select. The initialization device select signal is
`used by the 82559 as a chip select during PCI configuration read and
`write transactions. This signal is provided by the host in PCI systems.
`In a Card Bus system, this pin should not be connected.
`
`Device Select. The device select signal is asserted by the target once
`it has detected its address. As a bus master, the OEVSEL# is an input
`signal to the 82559 indicating whether any device on the bus has been
`selected. As a bus slave, the 82559 asserts OEVSEL# to indicate that
`it has decoded its address as the target of the current transaction.
`
`Request. The request signal indicates to the bus arbiter that the
`82559 desires use of the bus. This is a point-to-point signal and every
`bus master has its own REQ#.
`
`Grant. The grant signal is asserted by the bus arbiter and indicates to
`the 82559 that access to the bus has been granted. This is a point-to-
`point signal and every master has its own GNT#.
`
`INTA#
`
`0/0
`
`Interrupt A. The interrupt A signal is used to request an interrupt by
`the 82559. This is an active low, level triggered interrupt signal.
`
`SERR#
`
`0/0
`
`PERR#
`
`S/T/S
`
`System Error. The system error signal is used to report address
`parity errors. When an error is detected, SERR# is driven low for a
`single PCI clock.
`
`Parity Error. The parity error signal is used to report data parity errors
`during all PCI transactions except a Special Cycle. The parity error pin
`is asserted two clock cycles after the error was detected by the device
`receiving data. The minimum duration of PERR# is one clock for each
`data phase where an error is detected. A device cannot report a parity
`error until it has claimed the access by asserting OEVSEL# and
`completed a data phase.
`
`8
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`Ex. 1047 Page 12
`
`

`

`3.2.3
`
`System and Power Management Signals
`
`Networking Silicon - 82559
`
`Symbol
`
`Type
`
`Name and Function
`
`CLK
`
`IN
`
`Clock. The Clock signal provides the timing for all PCI transactions
`and is an input signal to every PCI device. The 82559 requires a PCI
`Clock signal (frequency greater than or equal to 16 MHz) for nominal
`operation. The 82559 supports Clock signal suspension using the
`Clockrun protocol.
`
`CLKRUN#
`
`Clockrun. The Clockrun signal is used by the system to pause or slow
`IN/OUT down the PCI Clock signal. It is used by the 82559 to enable or disable
`suspension of the PCI Clock signal or restart of the PCI clock. When
`0/D
`the Clockrun signal is not used, this pin should be connected to an
`external pull-down resistor.
`
`RST#
`
`IN
`
`PME#
`(PCI)
`
`CSTSCHG
`(Card Bus)/
`WOL(PCI)
`
`0/D
`
`OUT
`
`ISOLATE#
`
`IN
`
`ALTRST#
`
`VIO
`
`IN
`
`B
`IN
`
`Reset. The PCI Reset signal is used to place PCI registers,
`sequencers, and signals into a consistent state. When RST# is
`asserted, all PCI output signals will be tri-stated.
`
`Power Management Event. The Power Management Event signal
`indicates that a power management event has occurred in a PCI bus
`system.
`
`Card Status Change/Wake on LAN. This pin is multiplexed to
`provide Card Status Change or Wake on LAN signals. In a CardBus
`system, it is used as the Card Status Change output signal and is an
`asynchronous signal to the Clock signal. It indicates that a power
`management event has occurred in a CardBus system. In a PCI
`system, it is used as the WOL pin and provides a positive pulse of
`approximately 52 ms upon detection of an incoming Magic Packet*.
`
`Isolate. The Isolate signal is used to isolate the 82559 from the PCI
`bus. When Isolate is active (low), the 82559 does not drive its PCI
`outputs (except PME# and CSTSCHG) or sample its PCI inputs
`(including CLK and RST#). If the 82559 is not powered by an auxiliary
`power source, The ISOLATE# pin should not be connected.
`
`Alternate Reset. The Alternate Reset signal is used to reset the
`82559 on power-up. In systems that support an auxiliary power supply,
`ALTRST# should be connected to a power-up detection circuit.
`Otherwise, ALTRST# should be tied to Vee·
`
`Voltage Input/Output. The VIO pin is a voltage bias pin and should
`be 5 V ± 5% in a PCI bus system and Vee in a Card Bus system.
`
`3.3
`
`local Memory Interface Signals
`
`Symbol
`
`Type
`
`Name and Function
`
`FLD[7:0]
`
`T/S
`
`Flash/Modem Data Input/Output. These pins are used for Flash/
`Modem data interface.
`
`FLA[16]/
`CLK25
`
`OUT
`
`FLA[15]/
`EESK
`
`OUT
`
`Flash Address[16]/25 MHz Clock. This multiplexed pin is controlled
`by the status of the Flash Address[?] (FLA[?]) pin. If FLA[?] is left
`floating, this pin is used as FLA[16]; otherwise, if FLA[?] is connected
`to a pull-up resistor, this pin is used as a 25 MHz clock.
`
`Flash Address[15]/EEPROM Data Output. During Flash accesses,
`this multiplexed pin acts as the Flash Address [15] output signal.
`During EEPROM accesses, it acts as the serial shift clock output to
`the EEPROM.
`
`Preview Datasheet
`
`9
`
`Ex. 1047 Page 13
`
`

`

`82559 - Networking Silicon
`
`infel.
`
`Symbol
`
`Type
`
`Name and Function
`
`FLA[14]/
`EEDO
`
`IN/OUT
`
`Flash Address[14]/EEPROM Data Output. During Flash accesses,
`this multiplexed pin acts as the Flash Address [14] output signal.
`During EEPROM accesses, it acts as serial input data to the EEPROM
`Data Output signal.
`
`FLA[13]/
`EEDI
`
`OUT
`
`FLA[12]/
`MCNTSM#
`
`OUT
`0/D
`
`Flash Address[13]/EEPROM Data Input. During Flash accesses,
`this multiplexed pin acts as the Flash Address [13] output signal.
`During EEPROM accesses, it acts as serial output data to the
`EE PROM Data Input signal.
`
`Flash Address[12]/Modem Central Site Mode. This multiplexed pin
`acts as the Flash Address[12] output signal in a non-modem card. If
`modem is enabled, it is used as an output signal to the modem. It is
`either floated by default or driven low by the Modem System Control
`Registers.
`
`FLA[11 ]/
`MINT
`
`FLA[10]/
`MRING#
`
`FLA[9]/
`MRST
`
`IN/OUT
`
`Flash Address[11]/Modem Interrupt. This multiplexed pin acts as
`the Flash Address[11] output signal in a non-modem card. If modem is
`enabled, it is used as the Modem Interrupt input signal.
`
`Flash Address[10]/Modem Ring. This multiplexed pin acts as the
`IN/OUT Flash Address[1 OJ output signal in a non-modem card. If modem is
`enabled, it is used as the Modem Ring input signal.
`
`OUT
`
`Flash Address[9]/Modem Reset. This multiplexed pin acts as the
`Flash Address[9] output signal in a non-modem card. If modem is
`enabled, it acts as the Modem Reset signal with an active high output.
`
`FLA[8]/
`IOCHRDY
`
`IN/OUT
`
`Flash Address[S]/ISA Input/Output Channel Ready. This
`multiplexed pin acts as the Flash Address[8] output signal in a non-
`modem card. If modem is enabled, it is used as the ISA IOCHRDY
`input signal.
`
`FLA[?]/
`CLKEN
`
`T/S
`
`FLA[6:2]
`
`OUT
`
`FLA[1]/
`AUXPWR
`
`T/S
`
`FLA[O]/