`

`Revision History
`
`Revision
`
`ReVISIOflDate Descriptlon
`
`June 1998
`1.0
`First release.
`
`Initial Public Release - removed references to AP-393
`
`.
`
`1.2
`
`July 1998
`
`November
`1998
`
`Defgg‘sber
`
`£3;ng
`
`Added Section 8.0, "Signal Descriptions" on page 12, Section 9.0, "Package
`and Pinout Information“ on page 18, and Section 10.0, "Bill of Materials" on
`page 22.
`
`Incorporated new schematics.
`
`Final B5—Step Schematics Added
`
` - removed references to AP-393
`
`Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or othenlvise, to any intellectual
`property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
`whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
`fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
`intended for use in medical, life saving, or life sustaining applications.
`Intel may make changes to specifications and product descriptions at any time, without notice.
`Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined." Intel reserves these for
`future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
`The 82559 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
`characterized errata are available on request.
`Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
`Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
`Intel Corporation
`PO. Box 7641
`Mt. Prospect IL 60056-7641
`or call 1-800-879-4683.
`
`Many documents are available for download from Intel’s website at http://www.intel.com.
`
`Copyright © Intel Corporation, 1997
`*Third-party brands and names are the property of their respective owners.
`
`ii
`
`Application Note (AP-392)
`
`Ex. 1048, Page 2
`
`
`
`Ex. 1048, Page 2
`
`

`

`

`

`9.0
`
`PACKAGE AND PINOUT INFORMATION ........................................................................................... 18
`9.1 Package Information ..................................................................................................... 18
`9.2 Pinout Information ......................................................................................................... 19
`9.2.1
`82559 Pin Assignments ................................................................................... 19
`9.2.2
`82559 Ball Grid Array Diagram ....................................................................... 21
`
`10.0
`
`BILL OF MATERIALS ..................................................................................................................... 22
`
`11.0
`
`APPENDIX A: 82559/PIIX4 LOM DESIGNS ................................................................................... 23
`
`iv
`
`Application Note (AP-392)
`
`Ex. 1048, Page 4
`
`

`

`infel.
`
`1.0
`
`Introduction
`
`The 82559 provides: a higher level of integration, enhanced features set, reduced power
`consumption, and small footprint (15 mm by 15 mm). The 82559 has been optimized to accelerate
`the integration of LAN into desktop, server, PC cards, docking stations (port replicators), and
`mobile platforms.
`
`1.1
`
`Scope
`
`This application note covers the design of the 82559 into a platform based on Intel's PCI to ISA/
`IDE Xcelerator 4 (PIIX4). The 82559 will reduce cost, power, and real estate in existing LAN On
`Motherboard (LOM) designs. Platform designs for other chipsets are available from your Intel
`representative.
`
`1.2
`
`Reference Documents
`
`This application note assumes that the designer has a working knowledge of high-speed design and
`layout issues. A knowledge of the Advanced Configuration and Power Interface (ACPI)
`Specification and power management industry initiatives is valuable prior to beginning the
`integration of the 82559 into any platform. The following reference list provides sufficient
`background material.
`
`• PCI Specification, PCI Special Interest Group.
`
`• Network Device Class Reference, Revision 1.0, Intel Corporation, Microsoft Corporation, and
`Toshiba.
`
`• Advanced Configuration and Power Interface (ACPI) Specification, Intel Corporation,
`Microsoft Corporation, Toshiba.
`
`• Advanced Power Management (APM) Specification, Intel Corporation and Microsoft
`Corporation.
`
`• 82559 Fast Ethernet Multifunction PCI/CardBus Controller Datasheet, Intel Corporation.
`
`• LAN On Motherboard (LOM) Design Guide Application Note (AP-391), Intel Corporation.
`
`• WOL Header Recommendations, Intel Corporation.
`
`Application Note (AP-392)
`
`Ex. 1048, Page 5
`
`

`

`82559 LOM Design Guide
`
`2.0
`
`PCI Interface
`
`The 82559 provides a direct (glueless) 32-bit interface to the PCI bus. Prior to configuration, the
`82559 operates as a simple slave device. After the device has been configured all data transactions
`with the device are through memory structures in system memory. The PCI interface must be
`enabled for bus mastering for normal operation. Address, data, and control signals are as defined in
`the PCI Specification. Additional clarification of the PCIMODE, CLKRUN#, RST#, PME#, WOL,
`ISOLATE#, ALTRST#, and VIO pins are provided in the following sections.
`
`2.1
`
`PCIMode
`
`Flash Address[O] (FLAO) doubles as the bus mode select pin during PCI reset. The PCIMODE#
`input signal (sampled during PCI RST#) determines whether the 82559 operates as a PCI or
`CardBus device. If this signal is sampled low when the RST# is active, the 82559 will operate as a
`PCI device; if sampled high, then a CardBus device. In a LOM design the pin is either left open
`(internal pull-down), pulled low (through a resistor), or connected to a Flash device. It should be
`pulled high only in a CardBus design.
`
`2.2
`
`Clockrun Operations
`
`The CLKRUN# signal is used by the system to pause or slow down the PCI Clock signal and by the
`82559 to enable and disable PCI Clock signal suspension or to request a restart of the PCI clock. If
`clockrun is not used, this pin should be pulled low through a resistor (the reference design provided
`in Section 11.0, "Appendix A: 82559/PIIX4 LOM Designs" on page 23 uses a value of 62 KQ).
`Pull-down resistor values were selected based on the requirements of Intel's Nand-tree test
`equipment. If the Nand-tree test capabilities of the 82559 are not used then any reasonable value
`will be adequate, i.e. 1- l O KQ.
`
`2.3
`
`Reset Considerations
`
`The 82559 can maintain a virtual connection to the network regardless of the power state of the
`system. Therefore, the state of the PCI bus signals can be undefined when the 82559 is operating
`from auxiliary power. The 82559 response to a reset event varies based on operational mode. The
`82559 provides three signals that enable the device to operate correctly in these environments.
`Connections to these signals vary based on system implementation.
`
`2.3.1
`
`PCI Reset
`
`The PCI Reset (RST#) signal is used to put PCI registers, sequencers, and signals in a consistent
`state. When the RST# signal is asserted, all PCI output signals are tri-stated. In LOM designs the
`82559's RST# pin would normally be connected to the PCI Reset pin.
`
`Note: In designs where an signal to drive the ISOLATE# pin on the 82559 is not available, the PCI
`reset signal may be routed to the ISOLATE# pin. In these designs the RST# pin on the 82559
`would be pulled-up to the 82559's power rail through a 3.3 KQ resistor.
`
`2
`
`Application Note (AP-392)
`
`Ex. 1048, Page 6
`
`

`

`

`

`82559 LOM Design Guide
`
`3.0
`
`Wake-up Events
`
`The 82559 provides two output signals to alert the system of a wake-up event, PME# and
`CSTSCHG (WOL). In ACPI compliant designs, the PME# pin alerts the system of any incoming
`event; and CSTSCHG, in CardBus systems. The WOL pin acts as an active high Wake on LAN
`(WOL) signal when used in PCI systems. This alleviates the need for external circuitry to create the
`WOL signal in Advanced Power Management (APM) designs. The WOL header requirements
`document is available from the wired for management website at http://developer.intel.com/ial/
`WfM/index.htm.
`
`3.1
`
`ACPI Designs
`
`The Power Management Event signal is an active low, open drain signal that indicates an event in
`ACPI compliant systems. It is usually connected to the General Purpose Input/Output 1 (GPI01)
`signal of the PIIX. In an ACPI compliant system, the Power Management Event signal is common
`to all PCI devices. Since the signal is driven from open drain sources, a single pull-up resistor to the
`3.3 VAUX must be provided. If configured, the 82559 will assert PME# anytime the system needs to
`be woken up.
`
`The 82559 was designed to be fully ACPI Specification compliant. The ACPI specification
`requires that PCI devices implement a power management event signal. The 82559 implements this
`through its PME# pin. For the 82559 to function properly in an ACPI context, the PME# signal
`should be connected to a pin on the PIIX4 device that resides in the resume well and is capable of
`generating a System Control Interrupt (SCI). In a PIIX4 design, which is intended to be both APM
`and ACPI compliant, it is recommended that the PME# signal is connected to the General Purpose
`Input 1 (GPII) PIIX4 pin. The GPII signal is capable of generating both a SCI and System
`Management Interrupt (SMI) making it the ideal pin to use.
`
`Note: As per the ACPI specification, the 82559 will not generate a follow-on wake-up indication
`until the device is re-armed. The re-arming is accomplished by clearing the PME bit
`
`3.2
`
`Advanced Power Management Designs
`
`The Wake on LAN pin provides the active high signal that wakes the system in APM designs. This
`signal is distributed via a 3-pin header in network interface card (adapter) implementations. The
`WOL signal is not necessary in LOM designs because it provides the same indication as the PME#
`signal (albeit active high). However, in adapter designs it can be used to build a card that provides
`both signal levels. If APM support is desired, then the PME# or WOL pin must be routed to a pin
`on the chipset capable of generating a SMI while the chipset is powered only from an auxiliary
`power source.
`
`It is recommended that the incoming signal from the WOL header is routed to a separate input on
`the PIIX4. The use of separate inputs provides the ability to interrogate the PIIX4 device once the
`system has powered up and discern the source of the wake event. The LID input of the PIIX4 is
`recommended since it resides in the resume well and is capable of generating a SMI or SCI.
`
`4
`
`Application Note (AP-392)
`
`Ex. 1048, Page 8
`
`

`

`82559 LOM Design Guide
`
`4.0
`
`Local Memory Ports
`
`The 82559 supports both a serial EEPROM for configuration information and a parallel Flash for
`user data. In most designs, the Flash interface is used for expansion ROM, such as Preboot
`Execution Environment (PXE) code.
`
`4.1
`
`Serial EEPROM
`
`The serial EEPROM of the 82559 provides storage for initialization, the heartbeat packet in
`managed designs, and the Card Information Structure (CIS) in CardBus designs. The EEPROM
`interface consists of the following signals:
`
`• EEPROM Data Input (EEDO)
`The EEDO pin is multiplexed with the Flash Address[l4] pin and acts as the serial input data
`pin to the EEPROM Data Output signal.
`
`• EEPROM Data Output (EEDI)
`The EEDI pin is multiplexed with the Flash Address[13] pin and acts as the serial output data
`pin to the EEPROM Data Input signal.
`
`• EEPROM Serial Clock (EESK)
`The EESK pin is a multiplexed with the Flash Address[l5] pin and acts as the serial clock
`output to the EEPROM.
`
`• EEPROM Chip Select (EECS)
`The EECS pin is used to assert chip select to the serial EEPROM.
`
`In unmanaged (TCO controllerless) PCI designs (such as the reference design provided in Section
`11.0, "Appendix A: 82559/PIIX4 LOM Designs" on page 23), a 64-word device is required. The
`EEPROM must be 3.3 V powered in order to operate with the 82559.
`
`4.2
`
`Flash Interface
`
`The 82559 support a glueless interface to an 8-bit wide (128 Kbyte), 3.3 V parallel memory device.
`This port can be used for a 128 Kbyte Flash or any other parallel 8-bit device which meets the
`82559's AC timing. The reference design provided in Section 11.0, ''Appendix A: 82559/PIIX4
`LOM Designs" on page 23 depicts a Flash socket, which may not be required if there is no
`requirement for the system to boot from the LAN or if the PXE code will be stored in main flash.
`
`The 82559 uses a number of the Flash address pins for auxiliary functions based on the
`configuration or the state of the device reset. The 82559 Datasheet contains additional details
`regarding these secondary pin functions.
`
`Application Note (AP-392)
`
`5
`
`Ex. 1048, Page 9
`
`

`

`82559 LOM Design Guide
`
`5.0
`
`Test Port
`
`The 82559 uses an internal NAND tree configuration for test purposes. The Test Port is not
`normally accessed in LOM designs. The Test pin (pin A13) must be pulled low through a 4.7 Kn
`resistor to place the device in normal operational mode.
`
`6
`
`Application Note (AP-392)
`
`Ex. 1048, Page 10
`
`

`

`

`

`

`

`

`

`82559 LOM Design Guide
`
`6.6.2
`
`Distance B: PHY to Magnetics (Priority 2)
`
`Distance B from Figure 2 should also be designed to extend less than one inch between devices.
`The high speed nature of the signals propagating through these traces requires that the distance
`between these components are closely observed. In general, any section of traces that is intended
`for use with high speed signals should observe proper termination practices.
`
`Proper termination of signals can reduce reflections caused by impedance mismatches between
`devices and traces. The reflections of a signal may have a high frequency component that may
`contribute more EMI than the original signal itself. For this reason, these traces should be designed
`to a 100 Q differential value.
`
`10
`
`Application Note (AP-392)
`
`Ex. 1048, Page 14
`
`

`

`82559 LOM Design Guide
`
`7.0
`
`Power Supply Requirements
`
`WOL designs require a segmented power supply. The auxiliary power supply (+3.3VSB) is used to
`provide the trickle power necessary to keep key components operational in WOL mode.
`
`7.1
`
`+3.3VSB Power Requirement
`
`In designs that utilize 3.3VSB, the 82559 will operate from this supply in all operational states.
`Therefore, the+ 3.3VSB must be capable of supplying 175 mA ofcurrent (worst case requirements
`for the 82559).
`
`7.2
`
`+3.3VSB Power Recommendation
`
`Ideally the power supply will provide an AUX_ GOOD signal. The AUX_ GOOD signal indicates
`that the auxiliary power supply is ready to provide stable power and is similar to the PWR _ GOOD
`signal on many of today's common power supplies.
`
`Note: The AUX_GOOD signal from the power supply is the same as the ALTRST# signal of the 82559.
`
`Application Note (AP-392)
`
`11
`
`Ex. 1048, Page 15
`
`

`

`

`

`

`

`

`

`

`

`

`

`

`

`

`

`

`

`

`

`

`

`

`

`82559 LOM Design Guide
`
`11.0
`
`Appendix A: 82559/PIIX4 LOM Designs
`
`The Intel 82559 is fully compatible with the Intel PCI to ISNIDE Xcelerator 4 (PIIX4). The
`following pages provide a complete reference design for a 82559/PIIX4 solution. Schematic notes
`are also provided below.
`
`Schematic Notes
`
`• GPil of the PIIX4 is used for the PME# input from the 82559. It should also be used for PME#
`inputs from PCI slots. GPil can cause SMI, SCI, and Resume events allowing it to operate in
`Advanced Configuration and Power Interface (ACPI) and Advanced Power Management
`(APM) applications.
`
`• The PWR _ GOOD signal feeds into the Power Good (PWROK) input pin of the PIIX4 as well
`as discrete logic for the ISOLATE# signal
`
`• LAN_ WAKE is a 50 ms pulse used in APM WOL cases to wake the system. It is connected to
`the LID input of the PIIX4 which allows for resume events (no SMI and no SCI).
`
`Information on the PIIX4 can be obtained from the Intel 82371AB PCI-to-ISNIDE Xcelerator
`(PIIX4) Datasheet.
`
`Application Note (AP-392)
`
`23
`
`Ex. 1048, Page 27
`
`

`

`82559 LOM Design Guide
`
`24
`
`Application Note (AP-392)
`
`Ex. 1048, Page 28
`
`

`

`
`Revisions
`
`hate
`neeenenee
`REVISION 0.5
`m
`a. 29/9»
`hurls) u see? Saharan: Release
`m
`07 m9»
`hurls) “tee Saharan: Release
`«9
`area 9
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`
`
`
`
`
`Copyright © Intel Corporation 1998.
`*Third— party brands and names are the property of their
`respective owners.
`
`
`
`
`
`Physical Interface 3
`
`
`
`** PLEASE NOTE THESE SCHEMATICS ARE SUBJECT TO CHANGE
`THESE SCHEMATICS ARE PROVIDED AS IS WITH NO WARRANTIES
`WHATSOEVER,
`INCLUDING ANY WARRANTY OF MERCHANTABILITY,
`FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY
`OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR
`SAMPLES.
`Information in this document is provided in connection
`with Intel products. No license, express or implied, by
`estoppel or otherwise,
`to any intellectual property
`rights is granted by this document. Except as provided
`in Intel‘s Terms and Conditions of Sale for such
`products, Intel assumes no liability whatsoever, and
`Intel disclaims any express or implied warranty,
`relating to sale and/ or use of Intel products including
`liability or warranties relating to fitness for a
`particular purpose, merchantability, or infringement of
`any patent, copyright or other intellectual property
`right. Intel products are not
`intended for use in
`medical, life saving, or life sustaining applications.
`Intel may make changes to specifications and product
`Descriptions at any time, without notice.
`The Intel
`82559 10/100Mbit LAN may contain design defects or
`errors known as errata, which may cause the product to
`deviate from published specifications. Current
`characterized errata are available on request.
`
`
`
`
`
`
`Cover Sheet
`
`82559
`
`1
`
`2
`
`
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`
`Mel
`
`1
`
`Ex. 1048, Page 29
`
`Ex. 1048, Page 29
`
`

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`.
`requnements.
`other
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`TCO features of the
`= »
`.
`is recommended that
`R8
`52559-
`CGmECE the
`E
`resistors be used other
`62K SMECLK and 5mm pins to
`that hard strapping the
`the systems we
`.
`up to the 3.3 volt rail
`plus
`All V55 Pins are connected together on the board
`controller, or pull them
`
`level.
`The power on the symbol ls broken down
`”Rough 100K mum)”
`between Core power
`(Vss) , Local Bus Power
`(Vsspl) ,
`is not “53¢ The”
`
`Transmit Power
`(Vest) , and PCI power
`(Vsspp)
`just
`signals should not be
`K‘s
`v
`-
`-
`connected m embedded
`
`52559 Re'mnfl Dam"
`designs‘
`for clarlty.
`See enclosed table for a listing of
`Vss plns.
`ize
`Dncu mam Number
`av
`
`a
`‘°°°’
`°5
`DPME” n
`
`3
`a!
`2
`Sheet
`Tuesday December 22 1995
`sis:
`
`| s | c | o e
`
`
`6‘9
`
`02
`22p;
`
`<7
`
`'
`
`
`
`
`22“,
`
`
`
`
`
`
`
`
`
`
`
`Ex. 1048, Page 30
`
`Ex. 1048, Page 30
`
`

`

`‘ This Caplcltor is not normally installed, but a
`m
`
`‘ placement location can be provided.
`It may
`‘
`‘ need to be placed based on the results of FCC
`conformance testing,
`If it is required, values
`CA
`‘
`‘
`in the pico farad range would be used.
`large
`l
`i capicitance values installed in this location
`i
`‘ will have a negative effect on lung cahle
`71
`Performance, m care must be taken Ln
`‘
`‘
`selecting values used.
`‘
`me
`xx;
`'
`*
`Tm
`TX»
`
`“ TD»
`Rx+
`"
`Rm cm
`
`my mas Lzmm-l mom MAGNETICS TO RJ-45 CONNECX‘OR mm 1 INCH.
`
`J‘
`R145
`1
`2
`a
`4
`
`
`
`
`
`a.
`
`S
`G
`
`5
`5
`
`7a
`
`,
`
`RDC
`RX»
`RD’ “0 -
`m MAGNETICS
`
`R10
`75
`
`R11
`75
`
`Riz
`75
`
`‘
`
`‘
`7
`i
`TERHPLME
`‘
`‘
`mop;
`PLANE um ecs a sum sos minimum
`To uses mm
`CREATE TERMINATION PLANE IN PWBr
`THIS
`OPTIONAL CAP
`‘
`\
`an me some so was as
`
`she seems SHOULD mos HAVE my nmacl'
`consosnlmcs
`‘
`L mom
`|
`
`cs
`
`
`
`CHASSIS GROUND
`use sums m
`nus emu».
`
`,
`
`0“";
`C7
`
`7
`
`
`
`mp
`
`use cinemas. 100
`TRACKS FUR sss/ssu
`use memes
`Ann Tap/mu
`
`R9
`We
`ma
`
`TDN
`
`
`xsss nu. semen-mums asses As sesame
`RESISTOR: As CLOSE m
`
`
`
`‘
`
`
`
`
`
`M!
`32559 Relevance Design
`
`ize
`Dncumam Number
`av
`a
`(not)
`05
`
`
`
`ale:
`Tuesday DacemherZZ 199a
`Sheet
`3
`a!
`3
`A | a | c | D E
`
`
`
`
`
`
`
`
`
`avsa
`
`
`
`ca
`c9
`cm
`on
`at
`cm
`on
`(:15
`cm
`on
`ma
`
`we:
`flAuF
`am:
`flAuF
`a“:
`flAuF
`flAuF
`our
`flAuF
`uh:
`uh:
`
`
`cm
`flAuF
`
`slace decoupling capaciticre as close to the 32559 as
`possible
`If cmponen: placements are utilized on the
`bottom side of the hoard than place decoupling under
`the asses.
`
`Ex. 1048, Page 31
`
`Ex. 1048, Page 31
`
`