DIGITAL DESIGN
`PRINCIPLES AND ACTICES
`JOHN E WAKERLY
`
`PRENTICE HALL SERIES IN COMPUTER ENGINEERING
`EDWARDJ. McCLUSKEY, SERIES EDITOR
`
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`Digital Design
`Principles and Practices
`
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`JOHN F. WAKERLY
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`Stanford University
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`PRENTICE HALL, Englewood Cliffs, NewJersey07632
`
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`L1brary of Congress Cata log ing-1n-Publicat
`
`ion Data
`
`waker ly, John F.
`pr inc iples and pract ices / John F. Waker ly
`Digital design
`(Prent ice Hall ser1es in computer engineer ing)
`Cn.
`--
`p.
`Includes bibliographical references.
`ISBN 0-13-212838-1
`1. Dig1tal
`integrated
`circu1ts--Des ign and construct
`I. Title.
`II. Series.
`des 1gn.
`1990
`TK7874.H335
`621.39'5--dc20
`
`ion.
`
`2.
`
`Logic
`
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`
`89-26498
`CIP
`
`Editorial/production supervision: Kathleen Schiaparelli
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`Cover painting: Casey Burley
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`
`© 1990 by Prentice-Hall, Inc.
`A Division ofSimon &Schuster
`Englewood Cliffs, New Jersey 07632
`
`All rightsreserved. No part of this book may
`be reproduced, in any form or by any means,
`without permission in writing from the publisher.
`
`Printed in the United States of America
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`ISBN -13-212838-1
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`524
`
`SEQUENTIAL LOGIC DESIGN PRACTICES
`
`CH. 6
`
`ure
`
`forms binary multiplication using the shift-and-add algorithm, or binarydivision
`using the shift-and-subtract algorithm. To perform an n-bit operation, theseal.
`gorithms require an initialization step, n computation steps, and possible cleanup
`steps. The main machine for such an algorithm contains states for initialization,
`generic
`computation, and cleanup steps, and a modulo-n
`counter can be used
`as a submachine to control
`the number of generic
`computation steps executed.
`In Section 6.9.2, we'll show the design of a monolithic state machine for8-bit
`shift-and-add multiplication, while the design of a corresponding decomposed
`machine for n-bit multiplication is left as an exercise (6.59).
`
`synchronous design
`methodology
`fully synchronous
`circuit
`
`6.9 SYNCHRONOUS DESIGN METHODOLOGY
`The basic rule of synchronous design mnethodology is that all of a circuit's flip-
`flops should be clocked by the same clock, and that preset and clear inputs
`should not be used, except for system initialization.
`In such fully synchronous
`circuits,
`races and hazards are not a problem,
`for
`two reasons. First,
`the only
`fundamental-mode circuits that might be subject
`to races or essential hazardsare
`predesigned elements (e.g., discrete flip-flops or ASIC cells), guaranteed bythe
`manufacturer to work properly. Second, even though the combinational circuits
`that drive flip-flop control
`inputs may contain static or dynamic or function
`hazards, these hazards have no effect since the control
`inputs are sampled only
`after the hazard-induced glitches have had a chance to settle out.
`The designer of a synchronous system or subsystem must perform justthree
`well-defined tasks to ensure reliable system operation:
`(1) Minimize and determine the amount of clock skew in the system, asdis-
`cussed in Section 6.9.3.
`(2) Ensure that flip-flops have positive setup- and hold-time margins, including
`an allowance for clock skew, as described in Section 6.1.4.
`Identify asynchronous inputs, synchronize them with the clock, andensure
`that
`the synchronizers have an adequately
`low probability
`of
`failure, as
`described in Sections 6.9.5 and 6.10.
`Before discussing some of these timing-related issues, we'll
`model
`for synchronous system structure and an example.
`
`look at a general
`
`(3)
`
`6.9.1 Synchronous System Structure
`The sequential-circuit design examples that we've given so far in this chapter
`are mostly state machines with a small number of states.
`If a sequential circuit
`has more than a few flip-flops,
`then it's not desirable (and often not possible)
`
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`SEC. 6.9
`
`Figure 6-82
`Synchronoussystem structure.
`
`CLOCK
`
`SYNCHRONOUS DESIGN METHODOLOGY
`
`525
`
`COMMAND
`JI
`
`CONTROL
`UNIT
`(state machine)
`
`DATA IN
`
`CONTROL
`
`INPUT
`
`CONTROL
`
`DATA UNIT
`
`CONTROL
`
`CONDITIONS
`
`OUTPUT
`JL
`DATA OUT
`
`state machine, because the number of
`
`totreat the circuit as a single, monolithic
`stateswould be too large to handle.
`Fortunately, most digital systems or subsystems can be partitioned into two
`ormoreparts. Whether
`the system processes numbers, digitized voice signals, or
`astreamof spark-plug pulses, a certain part of the system, which we'll call
`the
`dataunit, can be viewed as storing,
`routing,
`combining, and generally processing
`"data."Another part, which we'll call
`the control unit, can be viewed as starting
`andstopping actions in the data unit,
`testing conditions, and deciding what
`to do
`nextaccording to circumstances.
`In general, only the control unit
`is treated as a
`state machine.
`Figure 6-82 is a general block diagram of a system with a control unit and
`adataunit. We have also included
`explicit
`blocks for
`input and output, but we
`Couldhave just as easily absorbed these functions into the data unit
`itself. The
`Controlunit is a state machine whose inputs include command inputs that
`indicate
`howthe machine is to function, and condition inputs provided by the data unit.
`Ihecommand inputs may be supplied by another subsystem or by a user to set
`egeneraloperating mode of the control machine (RUN/HALT, NORMAL/TURBO,
`ec), while the condition inputs allow the control unit
`to change its behavior as
`Cquiredby circumstances in the data unit (ZERO DETECT, MEMORY FULL, etc.).
`A key characteristic of the structure in Figure 6-82 is that the control unit
`d thedata unit both use the same common clock. Figure 6-83 illustrates the
`Uperationsof both units during a typical clock cycle:
`(1 Shortly after the beginning of the clock period, the control-unit state and
`the data-unit
`register outputs are valid.
`
`data unit
`control unit
`
`command input
`condition input
`
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