(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2005/0251617 A1
`(43) Pub. Date:
`Nov. 10, 2005
`Sinclair et al.
`
`US 2005025 1617A1
`
`(54) HYBRID NON-VOLATILE MEMORY
`SYSTEM
`
`(76) Inventors: Alan Welsch Sinclair, Candie (GB);
`Sergey Anatolievich Gorobets,
`Edinburgh (GB); Kevin M. Conley,
`San Jose, CA (US); Carlos J.
`Gonzalez, Los Gatos, CA (US)
`Correspondence Address:
`PARSONS HSUE & DE RUNTZ, LLP
`595 MARKET STREET
`SUTE 1900
`SAN FRANCISCO, CA 94105 (US)
`(21) Appl. No.:
`10/841,379
`(22) Filed:
`May 7, 2004
`
`Publication Classification
`
`(51) Int. Cl. .................................................. G06F 12/00
`
`(52) U.S. Cl. ............................................ 711/103; 711/170
`(57)
`ABSTRACT
`The present invention presents a hybrid non-volatile System
`that uses non-volatile memories based on two or more
`different non-volatile memory technologies in order to
`exploit the relative advantages of each these technology with
`respect to the others. In an exemplary embodiment, the
`memory System includes a controller and a flash memory,
`where the controller has a non-volatile RAM based on an
`alternate technology such as FeRAM. The flash memory is
`used for the storage of user data and the non-volatile RAM
`in the controller is used for System control data used by the
`control to manage the Storage of host data in the flash
`memory. The use of an alternate non-volatile memory tech
`nology in the controller allows for a non-volatile copy of the
`most recent control data to be accessed more quickly as it
`can be updated on a bit by bit basis. In another exemplary
`embodiment, the alternate non-volatile memory is used as a
`cache where data can Safely be staged prior to its being
`written to the to the memory or read back to the host.
`
`
`
`
`
`
`
`
`
`controlls in
`
`
`
`
`
`
`
`UPDATE BLOCKMANAGER
`550
`Sequential Update
`552
`Chaotic Update
`554
`
`
`
`
`
`ERASE BLOCK MANAGER
`56O
`
`
`
`
`
`NVRAM 150
`Cache 3O2
`Group Address
`Tables (GAT) 210
`
`Chaotic Block
`indices (CBI)
`22O
`
`Micron Ex. 1017, p. 1
`Micron v. Vervain
`IPR2021-01548
`
`

`

`Patent Application Publication Nov. 10, 2005 Sheet 1 of 12
`
`US 2005/025 1617 A1
`
`HOST 10
`
`MEMORY SYSTEM 20
`
`Flash Memory
`200
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Controller 100
`
`Interface 11
`
`PrOCeSSOr 120
`Optional CoProcessor
`121
`
`ROM 122
`Optional
`Programmable
`Non-Volatile Memory
`124
`
`RAM 130
`
`FIG.1
`
`Micron Ex. 1017, p. 2
`Micron v. Vervain
`IPR2021-01548
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`

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`Patent Application Publication Nov. 10, 2005 Sheet 2 of 12
`
`US 2005/025 1617 A1
`
`
`
`
`
`FIG.2
`
`
`
`
`
`FIG. 3
`
`
`
`
`
`
`
`
`
`FIG.4
`
`
`
`
`
`
`
`
`
`
`
`Controller
`
`
`
`(Flash) Memory
`200
`
`
`
`141
`(Flash) Memory
`200
`
`Memory System 20
`
`Alternate NVM
`150
`
`Controller
`100
`
`Memory System 20
`
`
`
`Micron Ex. 1017, p. 3
`Micron v. Vervain
`IPR2021-01548
`
`

`

`Patent Application Publication Nov. 10, 2005 Sheet 3 of 12
`
`US 2005/025 1617 A1
`
`150 Ya
`
`
`
`Parameter Storage 151
`
`CPU Code Storage 153
`
`Logical Data Structure Cache 157
`
`Host Boot Sectors 159
`
`Single Sector Cache 161
`
`Multi-Segment Read/Write Cache 162
`
`Copy Buffers 163
`
`FIG.5
`
`Micron Ex. 1017, p. 4
`Micron v. Vervain
`IPR2021-01548
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`

`

`Patent Application Publication Nov. 10, 2005 Sheet 4 of 12
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`US 2005/025 1617 A1
`
`a
`
`as
`
`Logical Sectors
`
`CONTROLLER 100
`
`as a
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`LOGICAL TO PHYSICAL
`ADDRESSTRANSLATION
`
`
`
`UPDATE BLOCKMANAGER
`550
`Sequential Update
`552
`
`
`
`RAM 130
`(Volatile)
`Cache 302
`
`Allocation Block
`List (ABL) 304
`
`Cleared Block
`List (CBL) 306
`
`
`
`ERASE BLOCKMANAGER
`560
`
`r
`
`INITIALIZATION 590
`
`CONTROL DATA
`EXCHANGE 580
`
`
`
`Memory 200
`Group Address
`Tables (GAT) 210
`Chaotic Block
`Indices (CB) 220
`
`
`
`Erased Block
`ListS (EBL) 230
`)
`MAP240
`
`
`
`
`
`- - - - - - - - - - - - - - -
`
`Micron Ex. 1017, p. 5
`Micron v. Vervain
`IPR2021-01548
`
`

`

`Patent Application Publication Nov. 10, 2005 Sheet 5 of 12
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`US 2005/025 1617 A1
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`Data Update Management Operations
`
`Update
`ABL
`
`Update Chaotic
`Sector List
`
`RAM Data
`Structures
`
`Control Write Operation
`
`
`
`
`
`Update CBI
`Sector
`
`ReWrite CB
`Block
`
`Flash Data
`Structures
`
`RegaUggar
`
`Update GAT
`Sector
`
`Rewrite GAT
`Block
`
`Update EBM
`Sector
`
`Update MAP
`Sector
`
`ReWrite MAP
`Block
`
`Update MAPA
`Sector
`
`ReWrite MAPA
`Block
`
`Update Boot
`Sector
`
`ReWrite Boot
`Block
`
`Operations on Control Data Structures
`FIG.7
`
`Micron Ex. 1017, p. 6
`Micron v. Vervain
`IPR2021-01548
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`

`

`Patent Application Publication Nov. 10, 2005 Sheet 6 of 12
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`US 2005/025 1617 A1
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`controlleria
`
`
`
`HostiNTERFACE 110
`
`
`
`
`
`READ
`
`O
`
`LOGICAL TO PHYSICAL
`ADDRESS TRANSLATION -
`540
`WRITE
`UPDATE BLOCK MANAGER
`550
`Sequential Update
`552
`Chaotic Update
`554
`I
`
`
`
`ERASE BLOCK MANAGER
`560
`Closeout Block Manager
`562
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`NVRAM 150
`Cache 302
`Group Address
`Tables (GAT) 210
`
`Allocation Block
`List (ABL) 3O4
`
`
`
`
`
`
`
`
`
`
`
`
`
`Cleared Block
`List (CBL) 3O6
`
`Chaotic Block
`indices (CBI)
`220
`
`Memory 200
`
`- - - - - - - - - - - - - - -
`
`FIG 3
`
`Micron Ex. 1017, p. 7
`Micron v. Vervain
`IPR2021-01548
`
`

`

`Patent Application Publication Nov. 10, 2005 Sheet 7 of 12
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`US 2005/025 1617 A1
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`
`
`Micron Ex. 1017, p. 8
`Micron v. Vervain
`IPR2021-01548
`
`

`

`Patent Application Publication Nov. 10, 2005 Sheet 8 of 12
`
`US 2005/025 1617 A1
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`
`
`Micron Ex. 1017, p. 9
`Micron v. Vervain
`IPR2021-01548
`
`

`

`Patent Application Publication Nov. 10, 2005 Sheet 9 of 12
`
`US 2005/025 1617 A1
`
`
`
`ZZZZ?ZZZ
`
`Micron Ex. 1017, p. 10
`Micron v. Vervain
`IPR2021-01548
`
`

`

`Patent Application Publication
`
`Nov. 10, 2005 Sheet 10 of 12
`
`US 2005/025 1617 A1
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`Host System
`
`Memory System
`
`
`
`
`
`
`
`
`
`Controller Chip
`100
`
`FIG. 14A
`
`
`
`
`
`Controller Chip
`100
`
`Flash Chip
`200
`
`
`
`NVMChip
`150
`
`Flash Chip
`200
`
`FIG.14B
`
`
`
`FIG.14C
`
`
`
`FIG.14D
`
`
`
`FIG. 14E
`
`Controller Chip 100
`Controller
`100
`
`Controller Chip 100
`Controller
`100
`
`Memory Chip 100
`
`Controller
`100
`
`
`
`
`
`
`
`NVM
`150
`
`NVM
`150
`
`Flash
`200
`
`
`
`
`
`Micron Ex. 1017, p. 11
`Micron v. Vervain
`IPR2021-01548
`
`

`

`Patent Application Publication Nov. 10, 2005 Sheet 11 of 12
`
`US 2005/025 1617 A1
`
`O
`
`Flash
`200
`
`2OO
`
`200'
`
`Host System
`
`Memory System
`
`
`
`Memory Chip 100
`
`Host 10
`
`
`
`Controller
`100
`
`FIG.14F
`
`
`
`FIG. 14G
`
`
`
`
`
`FIG. 14.H
`
`
`
`
`
`FIG. 14
`
`FIG. 14J.
`
`
`
`
`
`Memory System Chip
`20
`
`Micron Ex. 1017, p. 12
`Micron v. Vervain
`IPR2021-01548
`
`

`

`Patent Application Publication Nov. 10, 2005 Sheet 12 of 12
`
`US 2005/025 1617 A1
`
`Host System
`
`Memory System
`
`Flash Chip
`200
`
`NVM Chip
`150
`
`Flash Chip
`200
`
`
`
`NVMChip
`150
`
`
`
`
`
`
`
`Memory Chip
`
`a
`
`150
`
`2OO
`
`2OO'
`
`Host 10
`
`Controller
`
`F.G. 14K
`
`
`
`
`
`
`
`
`
`Host 10
`
`Controller
`
`
`
`
`
`FIG. 14L
`
`
`
`F.G. 14M
`
`
`
`
`
`w
`
`FIG. 14N
`
`Micron Ex. 1017, p. 13
`Micron v. Vervain
`IPR2021-01548
`
`

`

`US 2005/025 1617 A1
`
`Nov. 10, 2005
`
`HYBRD NON-VOLATILE MEMORY SYSTEM
`0001. This application is related to the following U.S.
`patent applications Ser. Nos. 10/750,155, filed Dec. 30,
`2003; 10/749,189, filed Dec. 30, 2003 ; 10/750,157, filed
`Dec. 30, 2003; 10/796,575, filed Mar. 8, 2004; and a patent
`application entitled “Data Boundary Management” by Alan
`Sinclair, filed concurrently with the present application, all
`of which is hereby incorporated by reference.
`
`FIELD OF THE INVENTION
`0002 This invention relates generally to semiconductor
`non-volatile data Storage Systems, and more specifically, to
`a System incorporating multiple non-volatile memory tech
`nologies.
`
`BACKGROUND OF THE INVENTION
`0003) Nonvolatile memory devices such as flash memo
`ries are commonly used as mass data Storage Subsystems.
`Such nonvolatile memory devices are typically packaged in
`an enclosed card that is removably connected with a host
`System, and can also be packaged as the non-removable
`embedded Storage within a host System. In a typical imple
`mentation, the Subsystem includes one or more non-volatile
`memory devices and often a Subsystem controller.
`0004 Current commercial memory card formats include
`that of the Personal Computer Memory Card International
`Association (PCMCIA), CompactFlash (CF), MultiMedi
`aCard (MMC), Secure Digital (SD), SmartMedia, XD cards,
`Memory.Stick, and Memory.Stick-Pro. One supplier of these
`cards is SanDisk Corporation, assignee of this application.
`Host Systems with which Such cards are used include digital
`cameras, cellular phones, personal computers, notebook
`computers, hand held computing devices, audio reproducing
`devices, and the like.
`0005 The nonvolatile memory devices themselves are
`composed of one or more arrays of nonvolatile Storage
`elements. Each Storage element is capable of Storing one or
`more bits of data. One important characteristic of the non
`Volatile memory array is that it retains the data programmed
`therein, even when power is no longer applied to the
`memory array.
`0006. A number of nonvolatile memory technologies
`exist, have various advantages with respect to one another,
`and are at various Stages of maturity. Perhaps the most
`common technologies are currently those based on floating
`gate electrically erasable programmable read only memory
`(EEPROM) cells, such as the NAND and NOR flash
`memory technologies. Other technologies include: those
`based on ferroelectric random-access memory (FeRAM),
`such as the 1T-1C ferroelectric memory cell; Ovonics Uni
`fied Memory (OUM); magnetic RAM (MRAM), such as
`Giant Magneto-Resistive RAM (GMRAM) (Spin Valve and
`Pseudo-spin Valve Tunneling), and Magnetoresistive
`Memory (MJT); Polymer Ferroelectric RAM (PFRAM);
`Micro Mechanical Memories; Single Electron Memories;
`Capacitor-less SOI Memories; Nitride Storage Memories;
`and other technologies being developed.
`0007. There are many commercially successful non-vola
`tile Solid-State memory devices being used today. These
`memory devices may be flash EEPROM or may employ
`Some the other types of nonvolatile memory cells. Examples
`
`of flash memory and Systems and methods of manufacturing
`them are given in U.S. Pat. Nos. 5,070,032, 5,095,344,
`5,315,541, 5,343,063, and 5,661,053, 5,313,421 and 6,222,
`762. In particular, flash memory devices with NAND string
`structures are described in U.S. Pat. Nos. 5,570,315, 5,903,
`495, 6,046,935. Also, nonvolatile memory devices are also
`manufactured from memory cells with a dielectric layer for
`Storing charge. Instead of the conductive floating gate ele
`ments described earlier, a dielectric layer is used. Such
`memory devices utilizing dielectric Storage element have
`been described by Eitan et al., “NROM: A Novel Localized
`Trapping, 2-Bit Nonvolatile Memory Cell, IEEE Electron
`Device Letters, vol. 21, no. 11, November 2000, pp. 543
`545. An ONO dielectric layer extends across the channel
`between Source and drain diffusions. The charge for one data
`bit is localized in the dielectric layer adjacent to the drain,
`and the charge for the other data bit is localized in the
`dielectric layer adjacent to the Source. For example, U.S.
`Pat. Nos. 5,768,192 and 6,011,725 disclose a nonvolatile
`memory cell having a trapping dielectric Sandwiched
`between two Silicon dioxide layers. Multi-state data Storage
`is implemented by Separately reading the binary States of the
`Spatially Separated charge Storage regions within the dielec
`tric.
`0008. In flash memory systems, erase operation may take
`as much as an order of magnitude longer than read and
`program operations. Thus, it is desirable to have the erase
`block of Substantial size. In this way, the erase time is
`amortized over a large aggregate of memory cells.
`0009. The nature of flash memory predicates that data
`must be written to an erased memory location. If data of a
`certain logical address from a host is to be updated, one way
`is to rewrite the update data in the same physical memory
`location. That is, the logical to physical address mapping is
`unchanged. However, this will mean the entire erase block
`containing that physical location will have to be first erased
`and then rewritten with the updated data. This method of
`update is inefficient, as it requires an entire erase block to be
`erased and rewritten, especially if the data to be updated
`only occupies a Small portion of the erase block. It will also
`result in a higher frequency of erase recycling of the memory
`block, which is undesirable in view of the limited endurance
`of this type of memory device.
`0010 Flash memories are a relatively “mature” technol
`ogy in that it is well understood how to make large memories
`at a low cost. Flash memories are particularly Suited to the
`Storage of large amounts of logically continuous host data;
`however, as the memory needs to be erased before new data
`can be written into it, and erase is typically performed on
`large blocks of cells, this can result in requiring large
`amounts of overhead, both in data management Structures
`and in Some operation times, due to the use of large memory
`Structures that optimize flash memory operations. Some of
`the other memory technologies can overcome the shortcom
`ing of flash-type memories, but they often have their own
`relative disadvantages with respect to flash and other alter
`nate technologies.
`
`SUMMARY OF THE INVENTION
`0011. The various aspects of the present invention present
`a hybrid non-volatile System that uses non-volatile memo
`ries based on two or more different non-volatile memory
`
`Micron Ex. 1017, p. 14
`Micron v. Vervain
`IPR2021-01548
`
`

`

`US 2005/025 1617 A1
`
`Nov. 10, 2005
`
`technologies in order to exploit the relative advantages of
`each technology with respect to the others. In an exemplary
`embodiment, the memory System includes a controller and
`a flash memory, where the controller has a non-volatile
`RAM based on an alternate technology such as FeRAM. The
`flash memory is used for the Storage of user data and the
`non-volatile RAM in the controller is used for system
`control data used by the controller to manage the Storage of
`host data in the flash memory. The use of an alternate
`non-volatile memory technology in the controller allows for
`a non-volatile copy of the most recent control data to be
`accessed more quickly as it can be updated on a bit by bit
`basis. Examples of System control data that can be kept in a
`non-volatile RAM on the controller include meta-block
`linking information, Status information for the memory
`blocks, boot information, firmware code, and logical-to
`physical conversion data.
`0012. In another set of embodiments, the alternate non
`Volatile memory is used as Secure cache where host data can
`be staged prior to Storing in, or reading out, host data in the
`flash or other memory managed in large erase blocks. This
`allows for data to be received from the host in one order (as
`logically continuous Sectors) and written into the primary
`non-volatile memory in another order. Consequently, Several
`Semi-autonomous memory arrays can be programmed in
`parallel without the need to organize the memory into
`meta-blockS.
`0013 Additional aspects, features and advantages of the
`present invention are included in the following description
`of exemplary embodiments, which description should be
`read in conjunction with the accompanying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0.014
`FIG. 1 is a block diagram showing a memory
`System connected to a host.
`0015 FIGS. 2-4 show various topologies for a hybrid
`non-volatile memory System.
`0016 FIG. 5 shows some examples of different control
`ler uses of Such non-volatile RAM.
`0017 FIG. 6 is a schematic block diagram of a meta
`block management System.
`0018 FIG. 7 illustrates a hierarchy of the operations
`performed on control data structures shown in FIG. 6.
`0.019
`FIG. 8 is a schematic block diagram of the meta
`block management System as implemented in the controller
`and flash memory in an exemplary embodiment of the
`present invention.
`0020 FIG. 9 is block diagram schematically representing
`the use of a hybrid non-volatile System according to a
`non-volatile read/write cache embodiment of the present
`invention.
`0021
`FIG. 10 is a schematic representation of the logical
`to physical mapping of Sectors according to an aspect of the
`present invention.
`0022 FIG. 11 a prior art arrangement of the logical to
`physical mapping of Sectors.
`0023 FIG. 12 illustrates sequential sector programming
`using the arrangement of FIG. 10.
`
`0024 FIG. 13 illustrates a data relocation operation
`using the arrangement of FIG. 10.
`0025 FIG. 14 is a more extensive list of topologies for
`a hybrid non-volatile memory System.
`
`DESCRIPTION OF EXEMPLARY
`EMBODIMENTS OF THE INVENTION
`0026. Hybrid Nonvolatile Memory Systems
`0027. The present invention presents nonvolatile memory
`Systems using the various memory technologies. In a prin
`ciple aspect of the present invention, two different non
`Volatile memory technologies are used in order to exploit
`their relative advantages with respect to each other. An
`exemplary embodiment is a memory System having a con
`troller portion and a memory portion, where the memory
`portion for the Storage of user data is based on a flash
`EEPROM technology and the controller includes a non
`Volatile memory from another non-volatile technology, Such
`as FeRAM, for the Storage of control and data management
`information.
`0028 FIG. 1 is a block diagram showing a memory
`system 20 connected to a host 10. The memory system may
`be detachable from the host, as in the case of a memory card,
`or embedded in the host. The memory system 20 includes
`the non-volatile, here flash, memory 200 for the storage of
`user data and the controller 100 for the management of the
`transfer of data between the host 10 and the memory 200 and
`the storage of the data in the memory 200. The memory 200
`is typically made up of one or more Separate chips, with the
`controller 100 formed on another separate chip, although the
`controller 100 may be formed on the same substrate as the
`memory 200.
`0029 FIG. 1 also shows some of the components com
`monly found in a controller 100. The controller 100 includes
`an interface 110, a processor 120, an optional coprocessor
`121, ROM 122 (read-only-memory), RAM 130 (random
`access memory) and optionally programmable nonvolatile
`memory 124, which is discussed more in the following. The
`interface 110 has one component interfacing the controller to
`a host and another component interfacing to the memory
`200. Firmware stored in nonvolatile ROM 122 and/or the
`optional nonvolatile memory 124 provides codes for the
`processor 120 to implement the functions of the controller
`100. Error correction codes may be processed by the pro
`cessor 120 or the optional coprocessor 121. In an alternative
`embodiment, the controller 100 is implemented by a state
`machine (not shown.) In yet another embodiment, the con
`troller 100 is implemented within the host.
`0030 Various aspects of controllers are described further
`in International Patent Publication WO 03/029951 and WO
`00/49488 and U.S. patent publications US 2002/0065899
`and US 2003/0070036, all of which are hereby incorporated
`by reference. Various other aspects of non-volatile memo
`ries, presented primarily in the flash memory context are
`presented in U.S. patent applications Ser. Nos. 10/750,155
`and 10/750,157 and International Patent Publication WO
`03/027828, which are hereby incorporated by reference.
`0031) RAM memory 130 is a volatile memory and used
`to Store control parameters, file acceSS tables, and other
`management information. AS this information is updated or
`otherwise changed as the memory operates, it is Stored in
`
`Micron Ex. 1017, p. 15
`Micron v. Vervain
`IPR2021-01548
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`

`

`US 2005/025 1617 A1
`
`Nov. 10, 2005
`
`RAM 130 rather than ROM 122; as a copy of this informa
`tion is also needed to be maintained non-volatility, a version
`of this information is keep in memory 200 and then loaded
`in RAM 130 when the system first started or as needed, with
`updated copies periodically written back in the memory 200.
`RAM 130 is also used as a cache for user data transferred
`between host 10 and memory 200. It is also often preferable
`to maintain in RAM 130, rather then ROM 122, part or all
`of the system firmware that has been transferred from
`memory 200. When firmware is stored in ROM 122, it
`cannot be changed or updated. By keeping firmware in
`memory 200, it can be changed if desired; however, this then
`again requires that the firmware is copied into RAM 130
`when the System is first started up So that it may more readily
`be accessed by the controller as needed.
`0.032
`FIG. 1 shows, in one embodiment of a primary
`aspect of the present invention, the inclusion of an optional
`programmable nonvolatile memory 124 as part of the con
`troller. Although any of the various embodiments described
`here can be implemented for a non-volatile memory System
`based on only a single technology, the present invention is
`described mainly in terms of System that uses two or more
`different technologies in order to exploit the relative advan
`tages of one technology with respect to another. FIG. 1 is
`one example of a hybrid non-volatile memory System, where
`the memory 200 is formed of a first solid-state non-volatile
`memory technology and the programmable nonvolatile
`memory 124 is formed of second solid-state non-volatile
`memory technology. According to the Specific embodiment,
`the programmable nonvolatile memory 124 can augment
`ROM 122 (read-only-memory) and RAM 130 or replace
`either or both of ROM 122 (read-only-memory) and RAM
`130.
`0033. Various topologies for hybrid non-volatile systems
`are shown in FIGS. 2-4. In any of these arrangements, the
`benefits to the overall system include “Instant On” capabil
`ity, faster performance, lower power consumption, and oth
`ers described in the following.
`0034). In both of FIGS. 2 and 3, the host 10 is again
`connected to memory system 20 that includes controller 100
`and memory 200 using a first non-volatile memory technol
`ogy, which is taken as a Flash memory in the exemplary
`embodiments. A second non-volatile memory 150 is also
`included in both cases. In FIG. 2, the alternate non-volatile
`memory (NVM) 150 uses the same bus 141 as flash memory
`200 and may either be on a separate chip or share a chip with
`one of the flash memory chips forming memory 200. In this
`arrangement, memory System 20 can be taken to include
`controller 100 and memory 200', which in turn includes both
`memory 200 and alternate non-volatile memory 150,
`although in the exemplary embodiments discussed below the
`alternate non-volatile memory 150 is used for system and
`control data (and, as Such, can be taken as part of the
`controller structure for the system 20) rather than host data.
`In variation of FIG. 2, both the memory 200 and alternate
`non-volatile memory 150 are in the same chip, but do not
`share the same bus 141. They may share the same control
`State machine on the chip, but the two types of memory are
`controlled Via different protocols and/or commands.
`0035) In FIG. 3, the alternate non-volatile memory 150
`communicates with the controller 100 through the separate
`channel of bus 143, rather than using the same bus 141 as
`
`flash memory 200. This arrangement avoids the sharing
`traffic of on a single bus for the two types of non-volatile
`volatile memory. In this arrangement, controller 100 and
`alternate non-volatile memory 150 can be taken together as
`system controller 100', where in the exemplary embodi
`ments discussed below the alternate non-volatile memory
`150 is used for system and control data. When the controller
`100 and alternate NVM 150 are on separate chips and are
`connected by a dedicated bus, the number of pins needed by
`the controller can be reduced by multiplexing Some of the
`pins for different uses, Similar to the arrangement described
`in U.S. Pat. No. 6,282,130, which is hereby incorporated by
`reference.
`0036 FIG. 4 explicitly shows alternate NVM 150 as part
`of the controller 100, where the other elements of the
`controller are suppressed. FIG. 4 can be considered a
`particular case of FIG. 1, where alternate NVM 150 of FIG.
`4 corresponds to the optional programmable nonvolatile
`memory 124 of FIG. 124. This has been renumbered in FIG.
`4 to emphasize that, in the exemplary embodiments, the
`memory 150 is based on a different non-volatile technology
`than memory 200; additionally, in the exemplary embodi
`ments the alternate NVM 150 may partially or completely
`replace one or both of RAM 130 and ROM 122.
`0037. A number of other topologies can also be used,
`either as variations of FIGS. 2-4 or differing significantly.
`For example, for any of these arrangements, all of the
`elements of memory system 20, both the controller 100 and
`memories 150 and 200 can be formed as part of the same
`chip. For card Systems without controllers, Such as XD cards
`or Memory Stick, where the host performs all of the control
`operations and communicates directly to with the card, the
`controller 100 would be taken as part of the host system and
`the card would then consist Memory 200 and alternate NVM
`150, either on a Single chip or Separate chips and commu
`nicating with the host with the Single bus (141) arrangement
`of FIG. 2 or the two bus (141, 143) arrangement of FIG. 3.
`0038. In an embodiment for card systems with out con
`trollers, the control operations for the memory are moved to
`the host. The memory system will then consist of the
`primary memory 200 and the alternate memory 150, where
`now the host will maintain the management data it will use
`to transfer data between itself and the primary memory 200.
`The basic access functions to the primary memory 200 can
`then be controller by a State machine formed on the same
`chip as the primary memory.
`0039 Generally, both the primary non-volatile memory
`200 and the alternate non-volatile memory 150 can be
`formed from any of the various non-volatile technologies
`both known, Such as those described above, and being
`developed. For example, both of the non-volatile memories
`could be composed of the same type of non-volatile RAM,
`replacing even the volatile RAM on the controller; in this
`case, the entire Storage portion of the memory could be
`modeled on the cachestructure described below with respect
`to FIG. 5. Most of the following, however, will focus on
`using two different types of non-volatile memory, using a
`flash memory as the exemplary embodiment for the primary
`non-volatile memory 200. This is mainly as the focus in the
`following is on the alternate non-volatile memory 150, and
`due to flash EEPROM memories being a common technol
`ogy for the primary non-volatile memory 200. The following
`
`Micron Ex. 1017, p. 16
`Micron v. Vervain
`IPR2021-01548
`
`

`

`US 2005/025 1617 A1
`
`Nov. 10, 2005
`
`discussion readily extends to cases where the memory 200
`uses other forms of non-volatile memory with characteristics
`(for a given application) that are Superior to flash and would
`allow elimination of flash, e.g. a non-volatile memory with
`the ability to program or erase more data at a time.
`0040 Although any of the various embodiments pre
`Sented herein could be implemented using only a single one
`of various non-volatile memory technologies, one of the
`principle aspects of the present invention uses more than one
`of these technologies in order to exploit their relative
`advantages with respect to each other. For example, flash
`EEPROM memories are a well-developed, “mature” tech
`nology, having advantages Such as having high densities and
`relatively low costs that are well adapted for bulk Storage of
`logically continuous host data. Consequently, the exemplary
`embodiments of the present invention will use a flash
`EEPROM memory with, for example, a NAND architecture
`using a large block structure for memory 200. (For similar
`reasons, a set of variations on the present invention can be
`based on a disc storage system for the memory 200.) The
`alternate non-volatile memory 150 will use one of the other
`technologies that has a finer erase or write granularity, faster
`access speed, differing reprogramming abilities (such as
`being programmed without first being erased), and/or other
`relative advantages with respect to memory 200. Particular
`examples described below will use the alternate NVM 150
`as a faster non-volatile cache or for control/System data
`erasable at the bit or byte level. Examples include FeRAM),
`MRAM, or even non-flash EEPROM that is bit- or byte-wise
`erasable.
`0041) Non-Volatile Cache Structures
`0042. As a particular example, consider the case where
`host data is stored in flash memory 200, and alternate NVM
`150 is used as a cache-type structure to replace many or all
`of the functions of RAM 130 and ROM 122 using one of the
`arrangements of FIGS. 2-4. (Various aspects of cache usage
`in non-volatile memory Systems are described further in
`U.S. patent application Ser. No. 10/796,575, incorporated by
`reference above.) When there is need to refer to specific
`arrangement, that of FIG. 4 with alternate NVM based upon
`the FeRAM is used. FIG. 5 shows some examples of
`different controller uses of Such non-volatile RAM.
`0043. As noted above, flash memory based storage sys
`tem has Some problems that are similar to a disk Storage
`system and can benefit from an alternate NVM with a
`comparative advantage Such as faster random acceSS or finer
`erase granularity. For example, flash memory can Suffer
`latencies due to its large block architecture. Such latencies
`occur due to the need to move data around to keep it valid
`when these blocks need to be erased but still contain valid
`data. A non-volatile cache could allow host operations to
`continue without having to wait for the flash operation to
`complete.
`0044) In Some cases, Such caching can help avoid access
`ing the flash at all. In Such cases, not only is the performance
`of the system increased, but also the overall lifetime of the
`System is extended. This is a result of reduced program and
`erase cycling in the flash memory 200 that is the primary
`limiter of flash lifetime.
`004.5 The large-block nature of flash memory also
`requires the Storage System to maintain Sophisticated block
`
`management and address translation data Structures and
`algorithms. Such Sophistication is necessary to optimize
`performance in Systems that Still access flash Storage SyS
`tems using a sector size (512 bytes) that is relatively small
`compared with the effective erase block sizes (currently in
`the rage 16 kB to 512kB). The benefit of an alternate NVM
`in the system would be twofold. First, performance could be
`increased by removing the need to acceSS flash memory each
`time the data Structures were needed or were update, and
`Second, Some of the Sophistication could be reduced due to
`the performance enhancement of the cache behavior. It is
`reasonable to expect that with a reduction in the Sensitivity
`to block size, that the block size could be increased, further
`reducing the cost of the flash memory and the Storage System
`as a whole.
`0046) When memory 200 uses multi-level cells (MLC),
`program and erase operations are even longer than for binary
`memories, making them more Susceptible to problems
`resulting from power loSS and reducing performance. If this
`reliability and performance gap can be bridged, the MLC
`can address those markets previously only addressable with
`Binary memory. This provides significant cost benefits that
`can more than compensate for the added cost of a hybrid
`non-volatile memory System.
`0047 The storage of defective block information would
`be convenient even if only Small amounts of fast acceSS
`NVM memory were available. Another application would be
`the Storage of hot (or experience) count information for
`physical blocks. This would be an improvement in both
`performance and reliability Since no additional program time
`would be required during erase to program the hot count
`back and the window in which Such a count could be lost
`would not exist.
`0048 Returning to FIG. 5, an exemplary embodiment
`includes Parameter Storage 151, CPU Code Storage 153,
`Logical Data Structure Storage 157, Host Boot Sectors 159,
`Single-Sector Cache 161, Multi-Segment Read/Write Cache
`162, and Copy Buffers 163. The alternate NVM 150 can
`Store all the parameters that govern configuration and opera
`tion of the flash storage system 20 in Parameter Storage 151.
`Configura