Paper No. 30
`Trials@uspto.gov
`571-272-7822 Entered: March 1, 2023
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`___________
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`MICRON TECHNOLOGY, INC.,
`Petitioner,
`
`v.
`
`VERVAIN, LLC,
`Patent Owner.
`___________
`
`IPR2021-01547 Patent 8,891,298 B2
`IPR2021-01548 Patent 9,196,385 B2
`IPR2021-01549 Patent 9,997,240 B2
`IPR2021-01550 Patent 10,950,300 B2
`___________
`
`Record of Oral Hearing
`Held: January 12, 2023
`_____________
`
`
`
`Before STACEY G. WHITE, JON M. JURGOVAN, and
`STEVEN M. AMUNDSON, Administrative Patent Judges.
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`

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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`
`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
`
`
`JASON LANG, ESQUIRE
`
`JARED BOBROW, ESQUIRE
`Orrick, Herrington & Sutcliffe, LLP
`1000 Marsh Road
`Menlo Park, CA 94025-1015
`
`
`
`
`ON BEHALF OF PATENT OWNER:
`
`
`ALAN L. WHITEHURST, ESQUIRE
`ARVIND JAIRAM, ESQUIRE
`McKool Smith, PC
`
`1999 K Street, N.W.
`Suite 900
`
`Washington, D.C. 20006
`
`
`The above-entitled matter came on for hearing, on Thursday,
`January 12, 2023, commencing at 10:00 a.m., EDT, at the U.S. Patent and
`Trademark Office, by video, before Julie Souza, Notary Public.
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`
`
`P R O C E E D I N G S
` - - - - -
`JUDGE JURGOVAN: Good morning everyone. We will now go on
`
`the record. This is the consolidated trial hearing for the following cases
`IPR 2021-01547 concerning U.S. Patent No. 8,891,298 B2, IPR 2021-01548
`concerning U.S. Patent No. 9,196,385 B2, IPR 2021-01549 concerning U.S.
`Patent No. 9,997,240 B2 and IPR 2021-01550 concerning U.S. Patent No.
`10,950,300 B2. The date is January 12, 2023 at 10 a.m., Eastern. On the
`panel today are Lead APJ Stacey White, APJ Steven Amundson and myself
`Jon Jurgovan. Who will be speaking on behalf of Petitioner in each case,
`please?
`MR. LANG: Good morning, Your Honors. Jason Lang. On behalf
`of Micron. I will be presenting the arguments for the first two sessions, the
`’298, ’385 and the ’240 and my colleagues here, Jared Bobrow, will be
`presenting the arguments for the final session, the ’300.
`JUDGE JURGOVAN: Thank you. And who will be speaking on
`behalf of Patent Owner in each case?
`
`(Pause.)
`JUDGE JURGOVAN: I think we have a frozen frame. Mr. Mohan
`is not able to speak.
`THE REPORTER: Off the record.
`
`(Pause, due to technical difficulties.)
`MR. WHITEHURST: -- from McKool Smith for the Patent Owner
`Vervain. I will be handling the first three patents today, the ’298, ’385 and
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`--
`
`JUDGE JURGOVAN: Okay, hold on a second. Let’s go back on the
`record, please.
`THE REPORTER: We’re on the record. Please continue.
`MR. WHITEHURST: So, Your Honor, to continue I will be handling
`the first three patents and my colleague, Arvind Jairam, will be handling the
`’300 patent and also we’re pleased to have with us today the inventor of the
`four patents, Dr. Mohan Rao.
`JUDGE JURGOVAN: Thank you. Okay. As stated in the Hearing
`Order, each party will have up to 60 minutes to present their arguments for
`IPR 2021-01547 and IPR 2021-01548. We’ll then take a 30 minute break
`and then after the break each party will have up to 45 minutes to present
`their arguments for IPR 2021-01549 and 45 minutes to present for IPR
`2021-01550. Since the Petitioner bears the burden of proving its case by a
`preponderance of the evidence Petitioner will begin, followed by Patent
`Owner. Each party may reserve time for rebuttal limited to the opposing
`party’s presentation. We cannot see your demonstratives or exhibits, so
`please identify page numbers of demonstratives, papers and exhibits as you
`speak so the Judges can follow along with your presentation. Please identify
`yourselves as you begin speaking so that the court reporter will know who
`you are.
`After the hearing please remain on the line in case the court reporter
`has any questions to ask of you about terms that may have been used in the
`hearing or other matters not understood. As this hearing is public third
`parties may be listening on the line. Some of the information in this hearing
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`has been designated as confidential. If for some reason you need to discuss
`confidential information, please let the Judges know in advance so that we
`can address the matter.
`If at any time you experience technical difficulties that impair your
`ability to represent your client, please contact the phone number given to
`you to resolve the issues. Do the parties have any questions before we
`begin?
`MR. LANG: Yes, Your Honor. Just so I heard you correctly you
`cannot see our screen if we share it?
`JUDGE JURGOVAN: For the record, no we cannot. Assume we
`cannot.
`MR. LANG: Okay.
`JUDGE JURGOVAN: Thank you. Okay. So we’ll begin now with
`the hearing for IPR 2021-01547 and IPR 2021-01548 and this will be a
`consolidated hearing transcript so all four IPR hearings will be in one
`transcript. Petitioner, you’re to begin and how much time would you like to
`reserve for rebuttal?
`MR. LANG: I want you to reserve around 15 minutes, Your Honor.
`JUDGE JURGOVAN: Fifteen. Thank you. You may begin when
`you’re ready
`MR. LANG: I guess we’re ready to begin, Your Honors.
`So, to jump to the grounds slide No. 4. The main disclosures are at
`issue with respect to the two sets of grounds, the first set of grounds being
`Moshayedi, the second set of grounds being Sutardja. PO against both sets
`of grounds, they argued that one set of limitations, the hot block limitations,
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`are not rendered obvious by both sets of grounds.
`Turning to slide 5. The ’385 patent, very similar, two sets of grounds,
`again Moshayedi and Sutardja. The only unique challenges in this
`proceeding is with respect to the dependent claims which recite basically the
`hot block limitations in reverse, cold block limitations. However, as you’ll
`see, the challenges are effectively the same with respect to those dependent
`claims.
`Turning to slide No. 7. I’ll just start with a quick background of the
`patent. As you know, all four patents share a common specification and
`really the kind of heart of it is a hybrid memory system. The hybrid memory
`systems were well known. Hybrid memory systems include two types of
`memory in this context, SLC and MLC. SLC, the characteristics of SLC
`single level cell were well known. They have greater endurance, meaning
`they can be written to more times but it’s more expensive than MLC. MLC
`on the other hand, can be stored more data per unit cost.
`Turning to slide 8, another aspect of the specification is the controller
`and you’ll actually hear some discussion from the Patent Owner today about
`the controller that apparently it only operates on physical blocks. Not so the
`heart of the controller, as set forth here, is that it maintains an address map
`of the modules. That address map maps logical blocks to physical blocks
`and I’ll discuss that shortly. The controller also does remapping. It will, for
`example, in the event of a data integrity failure, it would remap a logical
`address, a logical block to a new physical location to a new in the SLC level.
`Turning to slide 9. Central to the disputes today, Your Honors, is this
`discussion about hot blocks and really we only have one description in the
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`specification at 6:24–35, and that description simply says if there’s hot
`blocks that receive a lot of writes, uses the generic term blocks, then on a
`periodic basis there’s a transfer of those blocks, again the generic term
`blocks, to SLC flash memory. The cold blocks, it’s just reversed. That’s
`infrequent writes to blocks, it goes to MLC.
`There are two limitations that correspond to that. As first you
`determine the blocks that are accessed most frequently by maintaining a
`count and then second, you would allocate those blocks to SLC by
`transferring content to SLC.
`Turning to slide 11. The only difference in claim 1 is that claim 1 of
`the ’385 basically swaps an FTL instead of controller. There’s no specific
`arguments to this. Again, at issue in the ’385, no unique issues for these
`dependent claims but the arguments are effectively the same.
`Turning to slide 13. There’s one express claim construction issue in
`this proceeding, and that is Patent Owner from the get-go in the preliminary
`response made the argument that the claim block actually means a physical
`block and they attempted to distinguish, for example, counts to logical
`blocks because they argued blocks actually means physical blocks. That
`was rejected at the Institution phase because the claim of course recites
`blocks, not physical blocks.
`Turning to slide 14. In the Patent Owner response, the Patent Owner
`doubled down on this construction and make no mistake about it, the issue is
`straightforward. Blocks, the claimed blocks, should be limited to physical
`blocks in Patent Owner’s own words as opposed to logical blocks.
`Turning to slide 15. There are at least five bases that this is
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`construction that would be legally erroneous and I’ll walk through each one
`briefly.
`Turning to slide 16. This is a classic case, Your Honors, where the
`Patentee knew how to use each of these terms. Logical block, logical block,
`physical block, physical block. Then in the relevant disclosure, the allocate
`(phonetic) disclosure, the patent uses the generic term block just as the
`Patentee does in the claim.
`Turning to slide 17. This situation has been dealt with by District
`Court, by the Federal Circuit and it’s the classic case of if you claim, for
`example, and know (audio interference) case a patient, you can’t just read
`that patient to be a human patient and the facts here, Your Honor, are much
`more compelling because in this case, this is the specification and this is a
`very clear demonstration that the Patentee knew how to use both terms, and
`there was a choice made to use the broader term, both in the relevant
`disclosure and more notably in the claim. This alone renders the
`construction legally erroneous.
`Turning to slide 18. The surrounding claim language confirms that
`block means both logical and physical. To start, Your Honors, know that in
`the context of a nonvolatile memory, you have basically two forms of a
`block, a physical manifestation, the logical manifestation. There is a map
`that ties those two together and where do we see that map?
`Turning to slide 19, right in the claim. Maintaining an address map of
`at least one of the MLC and SLC memory modules, a map of the modules, a
`map of California. That map delineates what’s in the module and what does
`that map include? The claim says it, logical addresses range that map to a
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`physical address range. What can those address ranges be? “Block.” Right
`in the claim you have that these blocks have both forms attached.
`JUDGE JURGOVAN: Can I ask you a question here? Is -- how is a
`logical block represented in a controller or is it just the logical address that
`represents the block, you know what I mean? Is there any data in the
`controller that actually represents a logical block?
`MR. LANG: Yes, Your Honor. The logical block is the logical
`address range. The data associated with that logical address range is the data
`of that logical block.
`JUDGE JURGOVAN: The addresses could represent the logical
`block, is that’s what you’re saying? Oh, it’s just not actually any separate
`data in the computer that designates a certain logical block, it’s the address
`range?
`MR. LANG: Yes --
`JUDGE JURGOVAN: -- the address range.
`MR. LANG: And it’s the address map that correlates the logical
`block to the physical block and that data is the same data for the logical
`block in a physical block and it’s the map that correlates the two.
`JUDGE JURGOVAN: Thank you.
`MR. LANG: Turning to slide 20, this table, this claim table, Dr.
`Khatri concedes. Yes, this is the table that creates the logical block to
`physical block correlation. So Patent Owner on sur-reply came back and
`said, well, the claim doesn’t logical block. Well, two points. No. 1, it
`recites a generic form of block. It doesn’t recite physical blocks, but it does
`reference a logical block. As I just demonstrated claim 2 expressly says
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`block, claim 1 creates the two forms of the block.
`Turning to slide 21. Further the claim would be rendered nonsensical,
`Your Honors, if block did not include a logical block within its scope. The
`claim refers to allocating blocks to SLC. How does that occur? A physical
`block does not move to SLC. What happens is, and this is explained by Dr.
`Liu with citation to evidence that when you remap a logical block, the
`pointer of the logical block goes to a new physical block. Data for that
`block goes to the physical, new physical block. So that original physical
`block doesn’t get allocated, doesn’t move, doesn’t change. The only thing
`that happens is the logical block goes to SLC, so it would be error to limit
`the first instance of block to a physical block. But there can be no doubt that
`in fact later the claim actually uses block to refer to a logical block, and for
`that reason as another legal basis on the Microprocessor Enhancement Corp.
`v. Texas Instruments, Inc. case, that block cannot be limited to the physical
`block.
`Turning to slide 22. Again, Dr. Khatri admitted this. The physical
`block does not yet move. As he said, all that happens is the pointer changes.
`That is the logical block. It gets moved down. If you look at the figures of
`the patent, the specification, that’s exactly what happens when there’s a
`remapping. The logical block moves to SLC. The physical block does not
`move, is not allocated.
`Turning to slide 23, Patent Owner at sur-reply argues well, the
`allocating limitation itself defines how the allocation happens and that’s true.
`It says that you transfer data from those blocks to SLC. Well, when you
`transfer the data, what do you have to do? You actually allocate the logical
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`block SLC. You move the logical block SLC. If you didn’t, the logical
`block would point to the incorrect data. There has been no rebuttal to this.
`This is flash 101. Dr. Liu cited the Weathers reference. There’s other
`references that describe this basic concept.
`JUDGE JURGOVAN: Can I ask another question here about this
`limitation? It says that you allocate by transferring the contents of the
`blocks. Doesn’t that seem like a misnomer to you, that it’s the transfer of
`the information that’s causing an allocation? It seems like to me you have
`the cart before the horse there.
`MR. LANG: Yes. I think, Your Honor, that both the ‘298 patent and
`in fact, the prior art at times when they discussed this process and it’s
`implied that two things were happening. One, the logical block is allocated
`and then the data is being transferred. When we discuss, for example,
`Sutardja, it talks about remapping the logical block and it doesn’t explain
`that yes, of course, when you remap you allocate a logical block. Of course
`you also transfer the data.
`JUDGE JURGOVAN: It’s a remapping that causes the transfer, not
`the other way around.
`MR. LANG: Right. I think the two go hand in hand. Once you
`remap, you have to transfer the data or once you transfer the data, you have
`to remap.
`JUDGE JURGOVAN: Okay. And as you were saying earlier, you
`said that the physical data doesn’t move. But it seems to me if you if you
`change the map at some point is there a background process that cleans
`things up and actually accomplishes the moving the data from MLC to SLC.
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`MR. LANG: Your Honor, if I said that I misspoke and I apologize.
`The physical block does not move.
`JUDGE JURGOVAN: I got you. I understand. Okay. Thank you.
`JUDGE AMUNDSON: This is Judge Amundson. Let me see if I
`understand this. So the way this would work in a memory is when you have
`this reallocating or revamping. The pointer changes and then the data that
`was in certain physical memory cells has to go to new physical memory cells
`as directed by the change pointer?
`MR. LANG: There is a dispute relating to that, actually, Your Honor.
`The data from the block has to be transferred to the new location. It could
`be from the physical block to the physical block, or it could be from a
`logical block to the new physical block, meaning that -- and if you look at it
`from a background operation which Moshayedi describes which I’ll get into
`-- in one flavor he describes taking the data from the physical MLC block
`and moving that to the physical SLC block and doing the remapping. In
`another flavor with the incoming write, that data is associated with the
`logical block and then he describes writing that to SLC and then doing the
`remapping. So we see here --
`JUDGE AMUNDSON: Oh, yes.
`MR. LANG: So there is a transfer to MLC. It can either be from a
`physical block to a logical block and then in either case with the transfer,
`there is a remapping.
`JUDGE AMUNDSON: All right. Thank you.
`MR. LANG: And, of course, briefly, Your Honors, to nakedly read in
`physical block, you need some type of definition, some type of disclaimer.
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`Patent Owner asserts none here.
`Turning to slide 25. Patent Owner’s whole basis, Dr. Khatri’s whole
`basis for its construction was that they say it right there, physical and not
`logical blocks can be erased. Their assertion was that logical blocks cannot
`be erased. That was just proven false during trial. They now admit that it’s
`false, that there’s one expert that’s been inconsistent as I’ll get into. It’s Dr.
`Khatri.
`Turning to slide 26. PO admits logical blocks are erasable by the
`host, but they argue, well, but the claim’s all about the controller operating
`in physical groups themselves and the controller deletes a, or erases, a
`physical block. This again is just wrong on our account. First of all the
`claim doesn’t say that the controller erases the blocks, in fact it disconnects
`the controller from the blocks
`Turning to slide 28. This notion that the controller only operates on
`physical blocks is just contradicted by the claim itself. The controller
`maintains an address map of logical blocks and physical blocks. It remaps
`the logical blocks in the event of a DIT failure, we just talked about it,
`allocates logical blocks.
`Finally turning to slide 29. A controller in fact does erase a logical
`block. Dr. Liu explained this again with citation to evidence that the host
`would issue a logical block erase. That logical block will be erased in
`various ways, one being that it would cause the erasure of the physical
`block.
`Patent Owner makes another argument in sur-reply. I’ll briefly touch
`on this, that somehow modules mean that they’re physical cells and the
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`Patent Owner actually says that the claim says that the MLC are within the
`modules or the blocks or within the modules. The claim does not say that.
`It says the module comprises blocks. That aside, the claims define what the
`modules are because they say there’s a map of them. It’s like a map of
`California and that map includes logical blocks and physical blocks. It’s a
`map of the module.
`So turning to the grounds. The Moshayedi set of grounds, turning to
`slide 32. The petition presented two sets of disclosures, an erase count set of
`disclosure that swaps data between MLC and SLC. I will focus on that
`because Patent Owner does not contend that those disclosures only count
`logical block accesses. The disclosures otherwise are the same to the extent
`the Board rejects Patent Owner’s claim construction argument. Illogical
`write count disclosures also render the patents unpatentable.
`So turning to slide 33. The erase count -- the number of erases for
`each block and when that number is above a threshold, it triggers a swap and
`the petition -- and that says part of a write operation, so as a write is coming
`in, it triggers a swap process. The petition also argued that it would be
`obvious as well to do the same swap as a background operation, meaning not
`in connection to a write, but during idle time.
`Turning to slide 34. Patent Owner’s arguments in the preliminary
`response centered around the fact that, well, this swap is just conducting an
`operation and therefore only new data is being written to the SLC area.
`But turning to 35. The Institution decision pointed out two important
`things. No. 1, this new data (audio interference) data associated with the
`logical address, that is the data and of the logical block and that is
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`transferred to SLC. No. 2, this is important. Moshayedi does not describe
`that the swap only involves transferring new data to SLC.
`Turning to slide 36. As far as the additional obviousness argument to
`the background operation, Patent Owner did not discredit any of that
`evidence showing that that was a beneficial operation, well known, had
`many benefits.
`Now I’ll jump forward to slide 38. Patent Owner against the erase
`count (audio interference) the respective contents of those blocks to the SLC
`module and this argument fails for three separate reasons, independent
`reasons. It’s based on erroneous claim construction. But Your Honors, even
`if you accepted that erroneous claim construction, it would still --
`Moshayedi still discloses it. At a bare minimum, Moshayedi discloses it as
`part of the obvious background operation, well, it’s rendered obvious as a
`background operation.
`So jumping to slide 39. What Patent Owner has done is effectively
`again doubled down on this construction of (audio interference) physical
`block. They have read the transferring of the respective contents not to be
`the contents of the block, but the contents of the physical block. So again,
`they’re reading blocks to mean physical block.
`But turning to slide 40, that’s incorrect for all the reasons that we
`discussed. But in addition, if you look at the relevant description in the
`specification here, there’s certainly no disclaimer that would limit block in
`this context to a physical block. If anything, the specification is suggesting
`that the transfer occurs as part of a write operation because it says the
`transfer happens every 1,000 or 10,000 writes.
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`And with that, turning to slide 42 the new data for the write is the
`respective content of those blocks, of the logical blocks. It’s new data.
`Moshayedi says it’s associated with a particular LDA. So that’s the data for
`the logical block. When it’s rendered, SLC it’s transferred in to the SLC.
`But if the Board does read block to be physical block that’s a no
`(indiscernible) for Moshayedi because the swap operation does not involve
`only new data and Your Honor noted in an earlier question about a process
`to clean up data, this is what Moshayedi does. The count is right here. The
`write operation the data will be written to SLC, but in addition, all of the
`data from MLC block is then copied to SLC. Why? Because then the MLC
`block can be erased. So the swap involves the transfer of all of the data from
`MLC including the contents of the physical MLC block to SLC.
`Slide 44. During the proceeding this became very clear. If you look
`at paragraph 59, the second paragraph there, the original data, that’s the data,
`the physical data in the MLC block plus the change data, that’s the new data
`on the right is copied to the new target block yet as part of a basic garbage
`collection block reclamation process described in the specification.
`Now it seems like this has been conceded in the reply or in the sur-
`reply. Patent Owner does not rebut this. It’s clear with Moshayedi the sway
`involves physical data from the block. They’ve argued effectively that, well,
`we’ve cited new paragraphs of Moshayedi. They make these new arguments
`in passing at various places and I’ll address it once. I think, Your Honors, I
`know you know the count new argument law very well, but I think that the
`good demarcation is Intelligent Bio-Systems, Inc. v. Illumina Cambridge,
`Ltd., which Patent Owner cites and in that case, as you know, there was a
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`reliance on a combination involving Zavgorodny and the Zavgorodny
`conditions and in reply, the Petitioners said, well, actually those conditions
`don’t work. I’m going to rely on, “conditions other than those in
`Zavgorodny.” Well, that’s a new ground, the Federal Circuit characterized
`as a new ground if we use this reference or not. Unlike that we pointed to
`the swap, we pointed to disclosures in Sutardja first and second showing.
`Those have been criticized, they’ve come up with a construction and we are
`explaining no, those disclosures disclose and render these limitations
`obvious. The Apple, Inc. v. Andrea Elecs. Corp., case, the Hytera
`Commnc’ns v. Motorola Sols. Inc., case exactly allow for that to address
`Patent Owner’s criticisms.
`Turning to slide 46. Again, at a bare minimum, it would be obvious
`to do the swap. It’s a pure background operation. The record evidence,
`plethora of evidence says you do these operations during idle time to be able
`to prepare for future write commands to improve performance. Dr. Khatri in
`fact admitted that it could be done prospectively and therefore save time and
`resources.
`Turning to slide 47. The only argument that Patent Owner has here is
`that Moshayedi teaches away. Not so. Moshayedi discloses background
`operations. In the particular case of MLC to SLC, Moshayedi said it’s not
`necessary. Why? Because of the write redirection that’s highlighted in red.
`In re Fulton recites In re Worley is dead on point and I’ll just read. In re
`Fulton states,
`“Choosing one alternative necessarily means rejecting the others.”
`That’s what Moshayedi did. He did pick one alternative, but he did
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`not discredit or say anything bad about background operations. To the
`contrary, he’s using background operations.
`With that, Your Honors, I’ll briefly turn to the Sutardja grounds.
`Again, there are two sets of disclosures with Sutardja. These were referred
`to as the first showing and the second showing in the papers in the
`Institution decisions. The, and just to start, both of the showings involve
`Sutardja’s first and second memories. The petition showed that the second
`memory can be SLC and in fact in all of the relevant embodiments it is SLC.
`Paragraph 106 has all the characteristics for the first memory as MLC, for
`the second memory as SLC. The petition lined up the evidence showing that
`claim 37 says that the second memory was SLC, first memory includes
`MLC. The petition relies on that scenario and the second memory is SLC.
`With that, Your Honors, the data shift discloses and it’s been
`undisputed now, Dr. Khatri originally refuted that this was a physical based
`on this logical or physical block construction, and he ultimately admitted at
`deposition, this is a physical block count. Why? Because it says write
`operations to a first block and then the second part highlighted. It says a
`logical block. Logical address corresponds to the first block. Therefore, this
`disclosure is saying if you add physical writes to a block and it goes above a
`threshold, you shift the data. It is a background operation. That’s not (audio
`interference) not connected to a write. Sutardja however also discloses write
`redirection and in this particular embodiment, a paragraph example given of
`write direction using a logical term.
`I’ll jump ahead to the Patent Owner arguments. Now, there’s some
`common arguments that they presented against both. Turning to slide 57.
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`IPR 2021-01547 2021-01548 2021-01549 2021-01550
`Patent 8,891,298 B2 9,196,385 B2 9,997,240 B2 10,950,300 B2
`Amazingly, despite the fact that two showings were made, the ID refers to
`those showings, the Patent Owner distinguishes those showings. Somehow
`they’ve argued that neither showing was made with limitation [1.F]. Well,
`the petition cites both the write redirection, both the data shift for limitation
`[1.F]. Both of them referred to as the first and second showing. Patent
`Owner understands that there can be no meaningful dispute that the petition
`properly presented presents those two showings.
`Next, Patent Owner argues well, maybe Sutardja’s second memory is
`an SLC despite all the evidence that I had just presented. Well, what
`developed at trial? Paragraph 145, which sets up the relevant disclosures
`146, 147, 149, says that the first memory has a lower life lifetime in a higher
`capacity than the second memory. Okay. Consistent.