Trials@uspto.gov
`571-272-7822
`
`Paper 11
`Date: April 11, 2022
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`v.
`VERVAIN, LLC,
`Patent Owner.
`
`IPR2021-01550
`Patent 10,950,300 B2
`
`
`
`
`
`
`
`
`
`Before SALLY C. MEDLEY, STACEY G. WHITE, and
`ROBERT J. WEINSCHENK, Administrative Patent Judges.
`WHITE, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`
`
`
`571-272-7822
`
`Paper 11
`Date: April 11, 2022
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`v.
`VERVAIN, LLC,
`Patent Owner.
`
`IPR2021-01550
`Patent 10,950,300 B2
`
`
`
`
`
`
`
`
`
`Before SALLY C. MEDLEY, STACEY G. WHITE, and
`ROBERT J. WEINSCHENK, Administrative Patent Judges.
`WHITE, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`
`
`
`
`IPR2021-01550
`Patent 10,950,300 B2
`
`INTRODUCTION
`I.
`Micron Technology, Inc. (“Petitioner”) filed a Petition requesting an
`inter partes review of claims 1–12 (“the challenged claims”) of U.S. Patent
`No. 10,950,300 B2 (Ex. 1007, “the ’300 patent”). Paper 1 (“Pet.”).
`Vervain, LLC (“Patent Owner”) filed a Preliminary Response. Paper 9
`(“Prelim. Resp.”).
`Under 35 U.S.C. § 314(a), an inter partes review may not be instituted
`unless the information presented in the petition “shows that there is a
`reasonable likelihood that the petitioner would prevail with respect to at
`least 1 of the claims challenged in the petition.” The following findings of
`fact and conclusions of law are not final, but are made for the sole purpose
`of determining whether Petitioner meets the threshold for initiating review.
`Any final decision shall be based on the full trial record, including any
`response timely filed by Patent Owner. Any arguments not raised by Patent
`Owner in a timely-filed response may be deemed waived, even if they were
`presented in the Preliminary Response.
`For the reasons stated below, we determine that Petitioner has
`established a reasonable likelihood that it would prevail with respect to at
`least one claim. We hereby institute an inter partes review as to all of the
`challenged claims of the ’300 patent on all of the asserted grounds of
`unpatentability.
`
`A. Related Matters
`The ’300 patent is part of a family of related patents including
`US 8,891,298 B2 (“’298 patent”); US 9,196,385 B2 (“’385 patent”);
`US 9,997,240 B2 (“’240 patent”). Ex. 1007, code (60). The parties indicate
`that the ’300 patent and the related ’298 patent, ’385 patent, and ’240 patent
`are the subject of the following district court proceedings: Vervain, LLC v.
`
`2
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`IPR2021-01550
`Patent 10,950,300 B2
`Micron Technology, Inc. et al., No. 6:21-cv-00487 (W.D. Tex.) and Vervain,
`LLC v. Western Digital Corporation et al., No. 6:21-cv-00488 (W.D. Tex.).
`Pet. 4–5; Paper 6, 2. The parties further indicate that the ’298 patent is the
`subject of IPR2021-01547; the ’385 patent is the subject of IPR2021-01548,
`and the ’240 patent is the subject of IPR2021-01549. Pet. 5; Paper 6, 2–3.
`B. The ’300 Patent
`The ’300 patent is titled “Lifetime Mixed Level Non-Volatile
`Memory System.” Ex. 1007, code (54). Generally, the ’300 patent
`describes a system that stores data in a second memory bank, in the case that
`data which was stored in a first memory bank fails a data integrity test. Id.
`at 5:10–17. Figure 1 of the ’300 patent is reproduced below.
`
`
`Figure 1 shows a block diagram of a computer system 10 that stores,
`i.e., writes, data from dynamic random access memory (“DRAM”) 20 onto
`non-volatile memory, e.g., multi-level cell (“MLC”) NAND flash
`memory 26 or single-level cell (“SLC”) NAND flash memory 28. Ex. 1007,
`4:60–61, 6:17–20; see id. at 5:23–42. DRAM 20, MLC NAND flash
`
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`memory 26, and SLC NAND flash memory 28 are controlled by device
`controller 14. Id. at 5:34–42. Further, device controller 14 “acts as the
`memory controller” in a process which “write[s] a quantum of data stored in
`DRAM to a particular location in NAND flash memory.” Id. at 6:17–22.
`In the write process, “the quantum of data [to be written] is read from
`DRAM into memory within the device controller.” Id. at 6:20–22. Then,
`the quantum of data is written to an identified physical address range in flash
`memory. Id. at 6:25–30; see id. Fig. 3A. In particular, the quantum of data
`initially is written to MLC NAND flash memory, rather than SLC NAND
`flash memory, because “MLC [NAND] flash memory is less expensive than
`SLC [NAND] flash memory.” Id. at 5:51–60; see id. at 5:12–14.
`Further, “[a]fter each write to an address within a particular address
`range,” of the MLC NAND flash memory, “the device controller 14 will . . .
`perform a read on the address range to ensure the integrity of the written
`data.” Ex. 1007, 5:61–64. In particular, the device controller compares
`“retained data representing” the quantum of data to be written with “newly
`stored data in the [MLC] NAND flash memory.” Id. at 6:33–39; see id. Fig.
`3B. If the data matches, “the write was a success.” Id. at 6:38–40; see id.
`Fig. 3B. “However, if the retained data does not match the newly stored
`data in the [MLC] NAND flash memory,” then a “quantum of available SLC
`NAND flash memory addresses” are identified, “the failed NAND flash
`physical address range is remapped to the next available quantum of SLC
`NAND flash memory,” and the quantum of data is written to SLC NAND
`flash memory. Id. at 6:40–52; see id. Fig. 3B.
`Additionally, in some embodiments, instead of device controller 15,
`“flash translation layer (FTL) 54 manages” the MLC and SLM NAND flash
`
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`IPR2021-01550
`Patent 10,950,300 B2
`memory banks and further conducts “control functions.” Id. at 7:3–15 see
`id. Fig. 4.
`
`C. Illustrative Claim
`Of the challenged claims, claims 1 and 12 are independent. Claims 2–
`11 depend from claim 1. Claim 1 is illustrative.
`1. A system for storing data comprising:
`memory space containing volatile memory space and nonvolatile
`memory space, wherein the nonvolatile memory space includes
`both multilevel cell (MLC) memory space and single level cell
`(SLC) memory space;
`at least one controller to operate memory elements and
`associated memory space;
`at least one MLC nonvolatile memory element that can be
`mapped into the MLC memory space;
`at least one SLC nonvolatile memory element that can be mapped
`into the SLC memory space;
`at least one random access volatile memory;
`an FTL flash translation layer, wherein the at least one controller,
`or FTL, or a combination of both maintain an address table in
`one or more of the memory elements and random access volatile
`memory;
`the controller controlling access of the MLC and SLC
`nonvolatile memory elements and the random access volatile
`memory for storage of data therein, the controller, in at least a
`Write access operation to the MLC nonvolatile memory element,
`operable to store data in the MLC nonvolatile memory element
`and retain such stored data in the random access volatile
`memory;
`the controller performing a data integrity test on stored data in
`the MLC nonvolatile memory element after at least a Write
`access operation performed thereon by comparing the stored data
`to the retained data in the random access volatile memory;
`
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`Patent 10,950,300 B2
`wherein the address table maps logical and physical addresses
`adaptable to the system, wherein the mapping is performed as
`necessitated by the system to maximize lifetime, and wherein the
`mapping maps blocks, pages, or bytes of data in either volatile or
`nonvolatile, or both, memories; and
`wherein a failure of the data integrity test performed by the
`controller results in a remapping of the address space to a
`different physical range of addresses and transfer of data
`corresponding to the stored data to those remapped physical
`addresses from those determined to have failed the data integrity
`test to achieve enhanced endurance.
`Ex. 1007, 7:37–8:11.
`
`D. Prior Art Relied Upon
`Petitioner relies upon the references listed below (Pet. 6):
`
`
`
`Reference
`Dusija, US 2011/0099460 A1, published Apr. 28, 2011
`(“Dusija”)
`Sutardja, US 2008/0140918 A1, published June 12, 2008
`(“Sutardja”)
`
`
`Exhibit No.
`1010
`
`1011
`
`E. Asserted Grounds of Unpatentability
`Petitioner, supported by the declaration of Dr. David Liu (Ex. 1009),
`asserts the following grounds of unpatentability (Pet. 6)1:
`
`Claim(s) Challenged
`1–9, 11, 12
`10
`
`35 U.S.C. §
`103
`103
`
`Reference(s)/Basis
`Dusija
`Dusija, Sutardja
`
`
`1 For purposes of this Decision, we assume the claims at issue have an
`effective filing date prior to March 16, 2013, the effective date of the
`Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284 (2011)
`(“AIA”), and we apply the pre-AIA version of 35 U.S.C. § 103. See Pet. 5–
`6 (assuming challenged claims are entitled to benefit of July 19, 2011 filing
`date).
`
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`Patent 10,950,300 B2
`
`II. ANALYSIS
`A. Discretionary Denial Under 35 U.S.C. § 314(a)
`Patent Owner argues that “the Board should exercise its discretion
`under 35 U.S.C. § 314 and deny institution because of the overlap with the
`parallel district court litigation.” Prelim. Resp. 36. Petitioner, however,
`contends that evaluation of the Apple v. Fintiv factors demonstrates we
`should not exercise discretion to deny institution of inter partes review. Pet.
`7–12.
`Institution of an inter partes review is discretionary. See 35 U.S.C.
`§ 314(a) (stating “[t]he Director may not authorize an inter partes review to
`be instituted unless the Director determines that the information presented in
`the petition . . . shows that there is a reasonable likelihood that the petitioner
`would prevail with respect to at least 1 of the claims challenged in the
`petition”) (emphasis added); Harmonic Inc. v. Avid Tech, Inc., 815 F.3d
`1356, 1367 (Fed. Cir. 2016) (“[T]he PTO is permitted, but never compelled,
`to institute an IPR proceeding.”). In determining whether to exercise that
`discretion on behalf of the Director, we are guided by the Board’s
`precedential decision in NHK Spring Co. v. Intri-Plex Techs, Inc., IPR2018-
`00752, Paper 8 (PTAB Sept. 12, 2018).
`In NHK, the Board found that the “advanced state of the district court
`proceeding” was a “factor that weighs in favor of denying” the petition
`under § 314(a). NHK, Paper 8 at 20. The Board determined that
`“[i]nstitution of an inter partes review under these circumstances would not
`be consistent with ‘an objective of the AIA . . . to provide an effective and
`efficient alternative to district court litigation.’” Id. (citing Gen. Plastic
`Indus. Co., v. Cannon Kabushiki Kaisha, IPR2016-01357, Paper 19 at 16–17
`(PTAB Sept. 6, 2017) (precedential in relevant part)).
`
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`Patent 10,950,300 B2
`The Board’s precedential decision in Apple Inc. v. Fintiv, Inc.,
`IPR2020-00019, Paper 11 (PTAB Mar. 20, 2020) (Fintiv”) sets forth the
`following six non-exclusive factors to consider when determining whether to
`exercise discretion to deny institution due to the advanced state of parallel
`litigation:
`
`1. whether the court granted a stay or evidence exists that
`one may be granted if a proceeding is instituted;
`2. proximity of the court’s trial date to the Board’s
`projected statutory deadline for a final written decision;
`3. investment in the parallel proceeding by the court and
`the parties;
`4. overlap between issues raised in the petition and in the
`parallel proceeding;
`5. whether the petitioner and the defendant in the parallel
`proceeding are the same party; and
`6. other circumstances that impact the Board’s exercise of
`discretion, including the merits.
`Id. at 6. “These factors relate to whether efficiency, fairness, and the merits
`support the exercise of authority to deny institution in view of an earlier trial
`date in the parallel proceeding.” Id. In evaluating these factors, we take “a
`holistic view of whether efficiency and integrity of the system are best
`served by denying or instituting review.” Id. (citing Patent Trial and Appeal
`Board Consolidated Trial Practice Guide 58 (November 2019),
`https://www.uspto.gov/TrialPracticeGuideConsolidated). We address the
`Fintiv factors below and detail our reasons for exercising discretion to deny
`institution based on § 314(a).
`
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`IPR2021-01550
`Patent 10,950,300 B2
`1. Whether a Stay Exists or Is Likely to Be Granted if a Proceeding Is
`Instituted
`Under the first Fintiv factor, we consider “whether the court granted a
`stay or evidence exists that one may be granted if a proceeding is instituted.”
`Finvtiv, Paper 11 at 6. Petitioner argues that “[n]either party has yet
`requested a stay, so at worst this factor is neutral because the Board ‘will not
`attempt to predict’ how the [D]istrict [C]ourt will proceed.” Pet. 11–12.
`Patent Owner argues that the District Court “rarely stay[s] a . . . patent case
`based on an IPR.” Prelim. Resp. 38. Thus, according to Patent Owner, the
`first factor “is neutral or weighs against institution.” Id.
`Neither party identifies any statements by the District Court or other
`evidence that specifically addresses a stay of this District Court Litigation.
`See Pet. 12; Prelim. Resp. 32. We decline to speculate based on the record
`in this case whether the District Court would grant a stay of the District
`Court Litigation. See Apple Inc. v. Fintiv, Inc., IPR2020-00019, Paper 15 at
`12 (PTAB May 13, 2020) (informative) (“Fintiv II”). As a result, we
`determine that the first Fintiv factor is neutral.
`2. Proximity of the Court’s Trial Date to the Board’s Projected Statutory
`Deadline
`Under the second Fintiv factor, we consider the “proximity of the
`court’s trial date to the Board’s projected statutory deadline for a final
`written decision.” Fintiv, Paper 11 at 6. Petitioner notes that the District
`Court “recently set a ‘first trial’ date . . . of 1/23/2023, ‘subject to the Court’s
`availability.’” Pet. 11. Petitioner argues that this trial date “falls a few
`months before the projected final written decision date,” but the District
`Court “has an exploding docket that has made it difficult . . . to hold trials on
`the dates they are scheduled.” Id. Thus, according to Petitioner, “the Board
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`is still likely to reach the merits of the Petition before or around the same
`time as the [D]istrict [C]ourt,” and the second factor favors institution. Id. at
`11. Patent Owner argues that the second factor favors denying institution
`because the trial date in the District Court Litigation “is almost three months
`prior” to the projected final written decision in this case. Prelim. Resp. 38.
`The current trial date in the District Court Litigation is January 23,
`2023. Ex. 1035, 3. The projected statutory deadline for a final written
`decision in this case is in April 2023. Because the trial date in the District
`Court Litigation is only a few months before the projected statutory deadline
`for a final written decision in this case, we determine that the second Fintiv
`factor slightly favors exercising our discretion to deny institution.
`3. Investment in the Parallel Proceeding by the Court and Parties
`Under the third Fintiv factor, we consider the “investment in the
`parallel proceeding by the court and the parties.” Fintiv, Paper 11 at 6.
`Petitioner argues that “to date, no court resources have been devoted to
`analyzing prior art, invalidity, or any other substantive issue,” “[n]o claim
`construction has occurred, a motion to dismiss is pending, and there has
`been no meaningful fact or expert discovery.” Pet. 8–9. Petitioner also
`argues that it “had no pre-suit notice of the 300 patent[, n]evertheless
`approximately four and a half months” after the District Court Litigation was
`filed Petitioner was able to get this Petition on file. Id. at 7, 8–9. Thus,
`according to Petitioner, the third factor favors institution. Id.
`Patent Owner argues that “[b]y the time the Board decides whether to
`institute this IPR in April 2022, the [D]istrict [C]ourt and the parties will
`have completed the following: briefing on a motion to dismiss, an amended
`complaint, an exchange of preliminary and final infringement and invalidity
`contentions, and claim construction.” Prelim. Resp. 39. Patent Owner also
`
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`IPR2021-01550
`Patent 10,950,300 B2
`argues that “[b]y . . . the estimated institution decision date, the parties will
`be halfway through fact discovery, have exchanged untold numbers of
`documents, and likely begun depositions.” Id. at 39–40. Thus, Patent
`Owner contends the third factor favors denying institution. Id.
`The evidence of record indicates that the District Court and the parties
`invested minimal resources in the District Court Litigation as to issues of
`unpatentability involving the ’300 patent. Also, the parties’ evidence shows
`that fact discovery is ongoing, expert discovery has not begun, and the
`deadline for dispositive motions is not until October 2022. Ex. 1035, 2–3.
`Further, Petitioner exercised reasonable diligence in filing the Petition six
`weeks after receiving Patent Owner’s infringement contentions in the
`District Court Litigation. Pet. 8. Thus, we determine that the third Fintiv
`factor weighs against discretionary denial of institution.
`4. Overlap Between Issues Raised in the Petition and in the Parallel
`Proceeding
`Under the fourth Fintiv factor, we consider the “overlap between
`issues raised in the petition and in the parallel proceeding.” Fintiv, Paper 11
`at 6. Petitioner argues that “should the Board institute an IPR proceeding on
`the [’]300 patent, [Petitioner] stipulates that it will not pursue any instituted
`grounds as invalidity defenses in the District Court thus, eliminating any
`overlap in issues.” Pet. 10; Ex. 2013, 2 n. 1 (repeating the same stipulation
`in its Invalidity Contentions for the District Court Litigation). Petitioner
`also notes that claim 6 is challenged in this proceeding even though it is not
`asserted in the District Court Litigation. Id.
`Patent Owner argues that the District Court Litigation “involves the
`same ’300 [p]atent” and “the Dusija and Sutardja prior art.” Prelim. Resp.
`40. Patent Owner also contends that “Petitioner’s narrow stipulation is
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`Patent 10,950,300 B2
`hollow in that it leaves open the possibility of parallel litigation for the same
`claims using printed publications and various system combinations not
`asserted in the Petition.” Id. at 41–42. Further, Patent Owner asserts “that
`Petitioner challenged dependent claim 6 in order to manufacture an
`argument on Fintiv factor 4.” Id. at 42. Thus, Patent Owner contends that
`the fourth factor favors denying institution. Id.
`The Petition challenges claims 1–12 and relies on Dusija for eleven of
`the challenged claims and the combination of Dusija and Sutardja for claim
`10. Pet. 6. Petitioner’s invalidity contentions in the District Court Litigation
`address claims 1–5 and 7–12 and rely on Dusija and Sutardja. Ex. 2013, 1,
`89–91. Nonetheless, Petitioner’s proposed stipulation that it will not pursue
`the same grounds in this case and the District Court Litigation mitigates to
`some degree concerns about duplicative efforts and potentially conflicting
`decisions. See Sand Revolution II, LLC v. Continental Intermodal Grp. –
`Trucking LLC, IPR2019-01393, Paper 24 at 12 (PTAB June 16, 2020)
`(informative). In addition, we are persuaded that Patent Owner’s assertions
`regarding the reason why Petitioner is challenging claim 6 in this proceeding
`are mere attorney argument based on speculation. We decline to speculate
`as to Petitioner’s rationale for challenging the patentability of claim 6. Thus,
`for all of the foregoing reasons, we determine that the fourth Fintiv factor
`weighs slightly against discretionary denial of institution.
`5. Whether the Petitioner and the Defendant in the Parallel Proceeding
`Are the Same Party
`Under the fifth Fintiv factor, we consider “whether the petitioner and
`the defendant in the parallel proceeding are the same party.” Fintiv,
`Paper 11 at 6. Here, Petitioner is the defendant in the District Court
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`Litigation. Pet. 10–11; Prelim. Resp. 43. Thus, this factor does not weigh
`against exercising discretionary denial.
`6. Other Circumstances that Impact the Board’s Exercise of Discretion,
`Including the Merits
`Under the sixth Fintiv factor, we consider “other circumstances that
`impact the Board’s exercise of discretion, including the merits.” Fintiv,
`Paper 11 at 6. Petitioner argues that the sixth factor favors institution
`because “the merits of the Petition are strong.” Pet. 9. Patent Owner argues
`that the sixth factor favors denial because “the merits of the Petition are
`weak for several limitations.” Prelim. Resp. 43.
`We considered the parties’ arguments and evidence of record. As
`discussed below, on this record, Petitioner demonstrates a reasonable
`likelihood of prevailing in showing that at least one of the challenged claims
`of the ’300 patent is unpatentable. Nonetheless, we need not decide whether
`the merits of Petitioner’s asserted grounds are particularly strong because it
`would not impact our ultimate determination under § 314(a). Thus, we
`determine that the sixth Fintiv factor is neutral.
`7. Balancing the Fintiv Factors
`Thus, based on our holistic view of the Fintiv factors, we decline to
`exercise our discretion under § 314(a) to deny the Petition.
`B. Level of Ordinary Skill in the Art
`In determining the level of ordinary skill in the art, various factors
`may be considered, including the “type of problems encountered in the art;
`prior art solutions to those problems; rapidity with which innovations are
`made; sophistication of the technology; and educational level of active
`workers in the field.” In re GPAC, Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995)
`(quotation omitted).
`
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`Here, Petitioner asserts that a person having ordinary skill in the art
`in the technology field of the 300 patent would be a person with
`at least a Bachelor of Science degree in electrical engineering,
`computer engineering, or a closely related field, along with at
`least 3–5 years of experience in the design of non-volatile
`memory devices. An individual with an advanced degree in a
`relevant field would require less experience in the design of non-
`volatile memory devices.
`Pet. 31.
`Patent Owner’s declarant Dr. Sunil Khatri provides the same
`description of a person of ordinary skill in the art. Ex. 2001 ¶ 22; see also
`id. ¶ 23 (noting agreement with Petitioner’s declarant on this definition).
`We adopt Petitioner’s description for purposes of this Decision, except that
`we delete the qualifier “at least” to prevent the description from extending
`beyond the level of ordinary skill in the art.
`C. Claim Construction
`In an inter partes review proceeding based on a petition filed on or
`after November 13, 2018, a patent claim shall be construed using the same
`claim construction standard that would be used to construe the claim in a
`civil action under 35 U.S.C. § 282(b). 37 C.F.R. § 42.100(b) (as amended
`Oct. 11, 2018).2 This rule adopts the same claim construction standard used
`by Article III federal courts, which follow Phillips v. AWH Corp., 415 F.3d
`1303 (Fed. Cir. 2005) (en banc), and its progeny. Under this standard, the
`words of a claim are generally given their “ordinary and customary
`meaning,” which is the meaning the term would have to a person of ordinary
`skill at the time of the invention, in the context of the entire patent including
`
`2 See Changes to the Claim Construction Standard for Interpreting Claims in
`Trial Proceedings Before the Patent Trial and Appeal Board, 83 Fed. Reg.
`51,340 (Oct. 11, 2018) (final rule).
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`the specification. See Phillips, 415 F.3d at 1312–13. Petitioner proposes
`constructions for the phrases “data integrity test,” “comparing the stored data
`to the retained data,” and the term “periodically.” Pet. 23–28. Patent Owner
`argues that each phrase should have its plain and ordinary meaning. Prelim.
`Resp. 17–23. We determine that no claim terms require express construction
`for purposes of this Decision.
`D. Overview of the Asserted Prior Art
`1. Dusija (Exhibit 1010)
`Dusija notes that “[d]ata errors in non-volatile memory inevitably
`increase with usage and with higher density of bits stored per cell.” Ex.
`1010, code (57). In an effort to purportedly address this issue, Dusija
`discloses a flash memory system having “an array of memory cells is
`configured with a first portion and a second portion” ; data written in the
`first portion is rewritten in the second portion if the data in the first portion
`has excessive errors. Id. at code (57), ¶ 18. Figure 1 is a block diagram
`showing a flash memory device, and is reproduced below. Id. ¶ 29.
`
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`Figure 1, reproduced above, “illustrates a host in communication with
`a memory device.” Id. As shown in Figure 1, host 80 “sends data to be
`stored at the memory device 90.” Id. ¶ 59. To write data to the memory
`array of memory device 90, host 80 communicates and interacts with
`memory chip 100 via controller 102, which manages memory chip 100. Id.
`¶¶ 59–60. Further, “memory chip 100 includes a memory array 200 of
`memory cells with each cell capable of being configured as a multi-level cell
`(‘MLC’) for storing multiple bits of data.” Id. ¶ 59. Figure 14B depicts
`memory array 200 and is reproduced below. Id. ¶ 116; see id. ¶ 109.
`
`
`Figure 14B, reproduced above, illustrates a rewrite of a second copy
`of a data page into the first portion of a memory array. Id. ¶ 45. As shown
`in Figure 14B, “array of memory cells 200 is partitioned into a first portion
`410 and a second portion 420.” Id. ¶ 109; see id. ¶ 116. “[S]econd portion
`420 has the memory cells configured as high density storage with each cell
`storing multiple bits of data” while “first portion 410 has the memory cells
`configured as lower density storage with each cell storing less number of
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`bits than that of the second portion.” Id. ¶ 109. “For example, a memory
`cell in the first portion is configured to store 1 bit of data as compared to 3
`bits of data in the second portion.” Id.
`Regarding the data writing process, Dusija explains that, “[w]hen a
`page of incoming data is to be written to the memory array 200, it is
`preferably stored in the high density second portion for the sake of
`efficiency and high capacity.” Id. ¶ 111. “Later, the first copy of the data
`page is read back in a ‘post write read’ to determine if there are any errors.”
`Id. ¶ 112. The post write read may be “accomplished . . . by comparison
`with the original copy which may be cached.” Id. If a “number of error bits
`in the data page has exceeded [a] predetermined amount, a second copy of
`the data page is rewritten to the first portion.” Id. ¶ 116. “The second copy
`is of the original data which may be cached.” Id.
`Furthermore, in “an alternative embodiment, the first portion serves as
`a cache for incoming data, so a cache copy of the input data is programmed
`into the cache.” Id. ¶ 127; see id. ¶¶ 131–134, Figs. 16A–16B. That is, in
`that embodiment, the first portion of the memory array acts as a cache for
`the original data to be written in the second portion of the memory array.
`See id. ¶¶ 127–129, 131–134.
`2. Sutardja (Ex. 1011)
`Sutardja notes that charge storage devices “can sustain a limited
`number of write cycles after which the charge storage devices can no longer
`reliably store data.” Ex. 1011 ¶ 4. In an effort to purportedly address this
`issue, Sutardja describes a system in which “[l]arge amounts of low cost
`memory may be combined with smaller amounts of memory having a higher
`write cycle lifetime. The memory having the higher write cycle lifetime can
`be used for storing frequently changing data.” Id. ¶ 102. Sutardja discloses
`
`17
`
`
`
`IPR2021-01550
`Patent 10,950,300 B2
`a memory system having a first nonvolatile semiconductor (NVS) memory
`and a second nonvolatile semiconductor (NVS) memory. Id. at code (57).
`Figure 3 of Sutardja is a functional block diagram of such a memory system
`and is reproduced below. Id. ¶ 87.
`
`
`As shown in Figure 3, the memory system is a solid state disk drive
`and includes “first solid-state nonvolatile memory 204 [that] may include
`single-level cell (SLC) flash memory or multi-level cell (MLC) flash
`memory” and “second solid-state nonvolatile memory 206 [that] may
`include single-level cell (SLC) flash memory or multi-level cell (MLC) flash
`memory.” Id. ¶¶ 108–109. Either the first or the second NVS memory is
`written to, based on respective wear levels. Id. ¶ 11; see id. ¶ 152.
`Further, “wear leveling module [260] may measure or estimate the
`wear across the solid-state nonvolatile memories and change the mapping to
`equalize wear across the solid-state nonvolatile memories.” Id. ¶ 110. “At
`various times, such as periodically, the wear leveling module may analyze
`the wear levels of the blocks” of data stored in an NVS memory “and remap
`relatively frequently rewritten logical addresses to blocks with low wear
`levels.” Id. ¶ 167. Such “[r]emapping may involve swapping data in two
`blocks.” Id.
`
`18
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`
`
`IPR2021-01550
`Patent 10,950,300 B2
`
`E. Obviousness over Dusija
`Petitioner asserts that claims 1–9, 11, and 12 are unpatentable under
`35 U.S.C. § 103(a) as obvious over Dusija, citing the Declaration of Dr.
`David Liu for support. Pet. 31–61 (citing Ex. 1009). Patent Owner,
`supported by the Declaration of Dr. Sunil P. Khatri (Ex. 2001), counters that
`Petitioner does not show that Dusija teaches or suggests every limitation
`recited by the claims and that Petitioner did not show it would have been
`obvious to modify Dusija in the manner asserted. Prelim. Resp. 44–61.
`1. Independent Claims 1 and 12
`Upon consideration of parties’ contentions and supporting evidence in
`this current record, we are persuaded by Petitioner’s showing and find that
`Petitioner has demonstrated sufficiently for purposes of this Decision that
`the limitations recited in claims 1 and 12 would have been obvious over
`Dusija. See Pet. 31–53, 58–61. Independent claims 1 and 12 recite
`substantially identical language and Petitioner relies on substantially the
`same arguments and evidence for these claims. See id. at 58–61 (arguments
`for claim 12 including several mentions that limitations are identical or
`effectively identical to limitations of claim 1); see also Ex. 1009 ¶¶ 208–216
`(Dr. Liu’s testimony noting that limitations of claim 12 are identical or
`effectively identical to limitations of claim 1). Thus, we will address these
`claims together.
`a) Summarizing Petitioner’s Contentions
`Petitioner’s arguments are summarized as follows: With respect to
`the preamble3 “[a] system for storing data comprising,” Petitioner asserts
`
`
`3 We need not decide whether the preamble recitation is limiting because,
`Petitioner establishes a reasonable likelihood that Dusija teaches it.
`
`19
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`IPR2021-01550
`Patent 10,950,300 B2
`that Dusija teaches this limitation through its discussion of a flash memory
`device that stores data in a memory array. Pet. 32 (citing Ex. 1010 ¶ 59, Fig.
`1; Ex. 1009 ¶ 125).
`As to the limitation “memory space containing volatile memory space
`and nonvolatile memory space,” Petitioner asserts that this limitation would
`have been obvious over Dusija. Pet. 33–36 (citing Ex. 1010 ¶¶ 59, 61–62,
`68, 111–117, Fig. 1; Ex. 1048, 497, 558; Ex. 1019 ¶ 132; Ex. 1028 ¶¶ 27,
`32, 119, 197, Fig. 1; Ex. 1049, 12:20–35, 13:24–42, 13:58–14:11; Ex. 1009
`¶¶ 127–138). As to the non-volatile memory space, Petitioner directs us to
`Dusija’s discussion of flash memory. Pet. 33.
`As to the recited volatile memory space, Petitioner directs us to
`Dusija’s discussion of caching data. Pet. 33 (citing Ex. 1010 ¶¶ 111–117).
`According to Petitioner, a person of ordinary skill in the art “would have
`understood (and certainly would have found it obvious) that a cache is
`typically implemented in random access volatile memory.” Id. In support
`of this assertion, Petitioner directs us to passages from the Microsoft
`Dictionary and the Examiner taking official notice of volatile memory often
`used as cache memory during the prosecution of the application that led to
`the ’300
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