United States Patent (19)
`
`Childs et al.
`
`-
`
`USOO5384737A
`Patent Number:
`Date of Patent:
`
`11)
`45
`
`5,384,737
`Jan. 24, 1995
`
`54 PIPELINED MEMORY HAVING
`SYNCHRONOUS AND ASYNCHRONOUS
`OPERATING MODES
`75) Inventors: Lawrence F. Childs; Kenneth W.
`Jones; Stephen T. Flannagan; Ray
`Chang, all of Austin, Tex.
`73 Assignee: Motorola Inc., Schaumburg, Ill.
`21 Appl. No.: 207,509
`22 Filed:
`Mar. 8, 1994
`5ll Int. Cl." .............................................. G11C 13/00
`52 U.S. Cl. .......................... 365/189,05; 365/189.04;
`365/230.08
`58 Field of Search ...................... 365/189.01, 18905,
`365/189.03, 189.04, 230.08, 230.05, 190
`References Cited
`U.S. PATENT DOCUMENTS
`4,899,317 2/1990 Hoekstra ............................ 365/190
`.. 7.
`Madland ............................. 365A233
`5i 1455 A: N.O.
`r 3/
`5, 121,015 6/1992 Ngo ..................................... 307/60s
`5,124,589 6/1992 Shiomi et al. ....................... 3O7/465
`5, 155,703 10/1992 Nogle .................................. 365/190
`
`56)
`
`5,223,755 6/1993 Richley ............................... 307/603
`OTHER PUBLICATIONS
`Terry I. Chappell et al., "A 2ns Cycle, 4ns Access
`512kb CMOS ECL SRAM", Feb. 1991 IEEE Interna
`tional Solid-State Circuits Conference, pp. 50, 51 & 288.
`Primary Examiner-Terrell W. Fears
`Attorney, Agent, or Firm-Daniel D. Hill
`(57)
`ABSTRACT
`A pipelined memory (20) has a synchronous operating
`mode and an asynchronous operating mode. The mem
`ory (20) includes output registers (34) and output enable
`registers (48) which are used to electrically switch be
`tween the asynchronous operating mode and the Syn
`chronous operating mode. In addition, in the synchro
`nous operating mode, the depth of pipelining can be
`changed between a three stage pipeline and a two stage
`pipeline. By changing the depth of pipelining, the mem
`ory (20) can operate using a greater range of clock
`frequencies. In addition, the operating frequency can be
`changed to facilitate testing and debugging of the mem
`ory (20).
`
`20 Claims, 18 Drawing Sheets
`
`WRITE
`CONTROL
`LOGIC
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`ADDRESS
`REGISTERS
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`STMicroelectronics, Inc., Ex. 1008
`IPR2021-01593
`Page 1
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`

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`U.S. Patent
`
`Jan, 24, 1995
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`Sheet 1 of 18
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`U.S. Patent
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`Jan. 24, 1995
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`STMicroelectronics, Inc., Ex. 1008
`IPR2021-01593
`Page 3
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`U.S. Patent
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`STMicroelectronics, Inc., Ex. 1008
`IPR2021-01593
`Page 4
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`U.S. Patent
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`IPR2021-01593
`Page 6
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`STMicroelectronics, Inc., Ex. 1008
`IPR2021-01593
`Page 7
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`STMicroelectronics, Inc., Ex. 1008
`IPR2021-01593
`Page 8
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`U.S. Patent
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`Jan. 24, 1995
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`STMicroelectronics, Inc., Ex. 1008
`IPR2021-01593
`Page 9
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`

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`U.S. Patent
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`Jan. 24, 1995
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`Sheet 9 of 18
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`STMicroelectronics, Inc., Ex. 1008
`IPR2021-01593
`Page 10
`
`

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`U.S. Patent
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`Jan. 24, 1995
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`Sheet 10 of 18
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`STMicroelectronics, Inc., Ex. 1008
`IPR2021-01593
`Page 11
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`IPR2021-01593
`Page 13
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`Jan. 24, 1995
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`STMicroelectronics, Inc., Ex. 1008
`IPR2021-01593
`Page 14
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`U.S. Patent
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`Page 15
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`STMicroelectronics, Inc., Ex. 1008
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`U.S. Patent
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`Jan. 24, 1995
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`STMicroelectronics, Inc., Ex. 1008
`IPR2021-01593
`Page 18
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`U.S. Patent
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`Jan. 24, 1995
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`IPR2021-01593
`Page 19
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`

`

`1.
`
`5,384,737
`
`PIPELINED MEMORY HAVING SYNCHRONOUS
`AND ASYNCHRONOUS OPERATING MODES
`
`5
`
`O
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`1. A related application entitled “Delay Locked
`Loop For Detecting the Phase Difference of Two Sig
`nals Having Different Frequencies', by Chang et al.,
`and having Attorney Docket Number SCO2252A, was
`filed concurrently herewith, and assigned to the as
`signee hereof.
`2. A related application entitled “Write Control For
`A Memory Using A Delay Locked Loop', by Flanna
`15
`gan et al., and having Attorney Docket Number
`SC02249A, was filed concurrently herewith, and as
`signed to the assignee hereof.
`3. A related application entitled "Synchronous Mem
`ory Having Parallel Output Data Paths”, by Flannagan
`et al., and having Attorney Docket Number SC02226A,
`was filed concurrently herewith, and assigned to the
`assignee hereof.
`4. A related application entitled “Memory Having Bit
`Line Load With Automatic Bit Line Precharge And
`25
`Equalization', by Flannagan et al., and having Attor
`ney Docket Number SC02376A, was filed concurrently
`herewith, and assigned to the assignee hereof.
`FIELD OF THE INVENTION
`30
`This invention relates generally to memories, and
`more particularly, to a pipelined memory having syn
`chronous and asynchronous operating modes.
`BACKGROUND OF THE INVENTION
`In integrated circuit memories, there are various
`ways of controlling the flow of data into and out of the
`memory. For example, a static random access memory
`(SRAM) may be operated asynchronously or synchro
`nously. In an asynchronous SRAM, timing for control
`ling the RAM is accomplished using external logic.
`A synchronous (SRAM) is a type of memory that has
`latches for all inputs and outputs, good drive capability,
`and a self timed write cycle, all on a single monolithic
`45
`integrated circuit. A synchronous SRAM is typically
`used as a high speed cache in a data processing system.
`When being used as a cache, the synchronous SRAM is
`under the control of a single system clock. The synchro
`nous SRAM can also be pipelined.
`SO
`The synchronous SRAM has several advantages over
`an asynchronous SRAM. First, the synchronous SRAM
`generally requires fewer external logic chips. Second,
`the synchronous SRAM can operate at higher system
`speeds than a comparable asynchronous memory. How
`55
`ever, as the synchronous SRAM is required to operate
`at higher system clock frequencies, timing specifications
`become increasingly more difficult to meet. For exam
`ple, it becomes more difficult to test and debug the high
`speed synchronous SRAM using existing testing equip
`ment. Also, the synchronous SRAM has a relatively
`small range of clock frequencies at which it can be
`operated, which prevents the speed of the memory from
`being reduced for testing and debugging purposes. In
`addition, manufacturing yields are reduced, and costs
`65
`increased, because process, power supply, and temper
`ture variations have more effect on the narrow margins
`that result from reduced cycle times.
`
`35
`
`2
`SUMMARY OF THE INVENTION
`Accordingly, there is provided, in one form, a pipe
`lined integrated circuit memory, having a plurality of
`memory cells, a column decoding circuit, an output
`register, and an output enable circuit. A memory cell of
`the plurality of memory cells is coupled to a bit line pair
`and to a word line. The column decoding circuit is
`coupled to the plurality of memory cells, and provides
`a data signal corresponding to data stored in a selected
`memory cell during a read cycle of the memory. The
`output register has an input terminal coupled to the
`column decoding circuit, and an output terminal. The
`output register receives the data signal from the column
`decoding circuit, and is responsive to a first clock sig
`nal. The output enable circuit is coupled to the output
`register and delays the data signal for three clock cycles
`of the first clock signal during operation of the pipelined
`integrated circuit in a three-stage pipelining mode. The
`output enable circuit delays the output data for two
`clock cycles of the first clock signal during operation of
`the pipelined integrated circuit memory in a two-stage
`pipelining mode. These and other features and advan
`tages will be more clearly understood from the follow
`ing detailed description taken in conjunction with the
`accompanying drawings.
`BRIEF DESCRIPTION OF THE DRAWENGS
`FIG. 1 illustrates in block diagram form, a memory in
`accordance with the present invention.
`FIG. 2 illustrates in partial block diagram form and
`partial logic diagram form, a portion of the memory of
`FIG. I.
`FIG. 3 illustrates in block diagram form, the read
`control delay locked loop of FIG. 1.
`FIG. 4 illustrates in block diagram form, the dummy
`path of FIG. 1.
`FIG. 5 illustrates in schematic diagram form, an out
`put path register of FIG. 2
`FIG. 6 illustrates in schematic diagram form, the
`output enable register of FIG. 2.
`FIG. 7 illustrates in schematic diagram form, the final
`amplifier of FIG. 2.
`FIG. 8 illustrates in partial logic diagram form and
`partial block diagram form, the arbiter circuit of FIG. 3.
`FIG. 9 illustrates in schematic diagram form, the
`voltage controlled delay circuit of FIG. 3.
`FIG. 10 illustrates in schematic diagram form, the
`VCD control circuit of FIG. 3.
`FIG. 11 illustrates in partial logic diagram form and
`partial schematic diagram form, the collapse detector
`circuit of FIG. 3.
`FIG. 12 illustrates in block diagram form the write
`control delay locked loop of FIG. 1.
`FIG. 13 illustrates in partial schematic diagram form
`and partial logic diagram form, the voltage controlled
`delay circuits of FIG. 12.
`FIG. 14 illustrates in partial schematic diagram form
`and partial logic diagram form, the arbiter circuit of
`F.G. 12.
`FIG. 15 illustrates in partial schematic diagram form
`and partial logic diagram form, the VCD control circuit
`of FIG. 12.
`FIG. 16 illustrates in partial schematic diagram form
`and partial logic diagram form, the collapse detector
`circuit of FIG. 12.
`
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`Page 20
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`15
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`10
`
`5,384,737
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`4.
`FIG. 17 illustrates in partial schematic diagram form
`dress registers 26. Read control delay locked loop cir
`and partial logic diagram form, the bit line load circuit
`cuit 44 receives clock signal CL2, clock signal KECL,
`of FIG. 1.
`and a mode control signal labeled "ASYNC', and in
`FIG. 18 illustrates a timing diagram of various signals
`response, provides a clock signal labeled "KU". Read
`of the memory of FIG. 1 in three stage pipeline mode.
`control delay locked loop circuit 44 is illustrated in
`FIG. 19 illustrates a timing diagram of various signals
`more detail in FIG. 3. Dummy path 46 receives clock
`of the memory of FIG. 1 in two stage pipeline mode.
`signal CL2, and in response, provides a clock signal
`FIG. 20 illustrates a timing diagram of various signals
`labeled “MD90'. Dummy path 46 is illustrated in more
`of the memory of FIG. 1 in asynchronous mode during
`detail in FIG. 4. Output enable registers 48 receives
`read and write cycles.
`clock signal KECL, a chip select signal labeled "CS', a
`write enable signal labeled "W", mode control signal
`DESCRIPTION OF A PREFERRED
`ASYNC", a pipelining control signal labeled
`EMBODIMENT
`“PIPE2", and in response, provides an output enable
`FIG. 1 illustrates in block diagram form, memory 20
`signal labeled "OE2'. Output enable registers 48 are
`in accordance with the present invention. Memory 20
`provided in more detail in FIG. 2. Output registers 34
`includes memory array 22, bit line loads/write drivers
`receives data signal MUX, output enable signal OE2,
`30, address registers 26, row decoders 28, column deco
`clock signals KU and MD90, mode control signal
`ding/sense amplifiers 32, output registers 34, output
`ASYNC, pipelining control signal PIPE2*, and in
`response, provides data signal Q. Output registers 34 are
`buffer 36, clock buffer 38, level converter 40, divide-by
`two circuit 42, read control delay locked loop circuit
`provided in more detail in FIG. 2. Mode control circuit
`20
`44, dummy path 46, output enable registers 48, write
`50 receives an external mode control signal labeled
`control delay locked loop circuit 52, and write control
`"MODE', and in response, provides mode control sig
`logic 54.
`nal ASYNC* and pipeline control signal PIPE2*. Write
`Memory array 22 includes a plurality of static ran
`control delay locked loop circuit 52 receives clock
`dom access memory cells. Each memory cell is coupled
`signal KCMOS, mode control signal ASYNC, and in
`25
`to a word line and a bit line pair. Each bit line pair
`response, provides a clock signal labeled "KSD'.
`serves as an input to the memory cells during a write
`During a read cycle of memory 20, column address
`cycle of memory 20 and as an output during a read
`signals COLUMN ADDRESS are provided to column
`cycle. A representative memory cell 24 is shown cou
`decoding/sense amplifiers 32 to select a column. Row
`pled to a word line labeled “WL', and to a pair of bit
`address signals ROW ADDRESS are provided to row
`30
`lines labeled 'BL' and 'BL'. Note that an asterisk “*”
`decoders 28 to select a word line. Memory cells located
`after a signal name indicates that the signal is a logical
`on the enabled word line provide data to their respec
`complement of a signal having the same name but lack
`tive bit line pairs. A data signal labeled "MUX', corre
`ing the asterisk". If the logically true state of a signal
`sponding to data provided by a bit line pair, is provided
`is a digital logic level one, the logically complement
`by column decoding/sense amplifiers 32. The sense
`35
`state is a digital logic level zero. And if the logically
`amplifiers sense and amplify the relatively small signals
`true state of a signal is a digital logic level zero, the
`received from a selected bit line pair, and provide a data
`logically complement state is a digital logic level one.
`signal labeled "MUX' to output registers 34. Output
`Also note that the signals shown in FIG. 1 and FIG. 2
`registers 34 then provide a data signal labeled "Q" to
`are differential signals, only the logically true signal
`output buffer 36. Output buffer 36 then provides an
`name is used to indicate which signal is the logically
`output data signal labeled "QPAD to an output pad (not
`true signal.
`shown). Note that for the purpose of illustration, only
`Address registers 26 receive ECL level address sig
`one output data path for one data signal is illustrated in
`nals labeled “ADDRESS', and provide row address
`the embodiment of FIG. 1. In other embodiments, addi
`signals labeled “ROW ADDRESS” to row decoders
`tional data paths may be used. Note that the number of
`45
`28, and column address signals labeled “COLUMN
`data signals and address signals provided to, or received
`ADDRESS' to column decoding/sense amplifiers 32.
`from memory 20 have no special significance and may
`Note that the particular address signals have no special
`be different in other embodiments.
`significance and may be different in other embodiments.
`During a write cycle, the flow of data is essentially
`Also, the amount of decoding performed by the row
`reversed. To write data to memory 20, row decoders 28
`50
`and column decoders may be different in other embodi
`receives row address signals ROW ADDRESS to se
`lect a word line. Column address signals COLUMN
`ninents.
`Data input buffers (not shown) provide input data
`ADDRESS are provided to column decoding/sense
`amplifiers 32. Column decoding/sense amplifiers 32 are
`signals labeled "DATA' to bit line loads/write drivers
`30. Bit line loads/write drivers 30 receive input data
`coupled to each bit line pair. Each memory cell of mem
`55
`signals DATA, a write control signal labeled “WCQ',
`ory array 22 that is coupled to the selected word line
`and a global equalization signal labeled "GEQ', and are
`receives a differential voltage on a corresponding bit
`coupled to each bit line pair of memory array 22.
`line pair. As in the read cycle, memory cells located on
`Clock buffer 38 receives an external ECL clock sig
`an enabled word line provide data to bit line pairs.
`nal labeled “CLK", and provides a buffered clock sig
`However, a voltage differential driven onto the bit line
`nal labeled "KECL'. Divide-by-two circuit 42 receives
`pairs by bit line loads/write drivers 30 is greater than
`buffered clock signal KECL and provides a clock signal
`the drive voltage of the memory cell and overwrites a
`labeled "CL2' at one-half the frequency of clock signal
`stored bit in the memory cell. At the end of the write
`KECL. Level converter circuit 40 also receives clock
`cycle the differential voltage on the bit line pair is re
`signal KECL and provides a CMOS (complementary
`duced to a level small enough so that the data is not
`65
`erroneously written into a memory cell during the fol
`metal-oxide semiconductor) level clock signal labeled
`"KCMOS'. Clock signal KCMOS is provided to write
`lowing read cycle. Equalization of the bit line pairs is
`control delay locked loop 52, dummy path 46, and ad
`achieved by bit line loads/write drivers 30. The bit line
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`nal for providing a control signal labeled "CSW".
`loads are illustrated later in more detail in FIG. 17, and
`are used to reduce, or equalize, a differential voltage on
`Inverter 79 has an input terminal for receiving clock
`the bit line pairs following a write cycle of memory 20.
`signal KECL, and an output terminal. NAND logic gate
`Equalization of the bit line pairs following a write cycle
`80 has a first input terminal for receiving pipeline con
`is commonly known as "write recovery'.
`trol signal PIPE2*, a second input terminal for receiv
`FIG. 2 illustrates in partial block diagram form and
`ing mode control signal ASYNC, and an output termi
`partial logic diagram form, output registers 34 and out
`nal. Inverter 81 has an input terminal connected to the
`put enable registers 48. Output registers 34 includes
`output terminal of NAND logic gate 80, and an output
`registers 56, 57, 60, and 61, switches 58, 59, and 64, and
`terminal. Register 73 has an input terminal connected to
`inverters 55, 65, and 66. Inverter 55 has an input termi
`the output terminal of inverter 72, a control terminal
`nal for receiving clock signal MD90, and an output
`connected to the output terminal of inverter 79, and an
`terminal. Register 56 has an input terminal for receiving
`output terminal for providing a signal labeled "NS".
`data signal MUX, a first control terminal for receiving
`Register 74 has an input terminal connected to the out
`put terminal of register 73, a control terminal for receiv
`clock signal MD90, a second control terminal for re
`ceiving mode control signal ASYNC, and an output
`ing clock signal KCMOS, and an output terminal. Regis
`15
`terminal for providing a data signal labeled "MUX1”.
`ter 75 has an input terminal connected to the output
`Register 57 has an input terminal for receiving data
`terminal of register 74, a first control terminal con
`signal MUX, a first control terminal connected to the
`nected to the output terminal of inverter 79, a second
`output terminal of inverter 55, a second control terminal
`control terminal connected to the output terminal of
`for receiving mode control signal ASYNC, and an
`inverter 81, and an output terminal for providing a
`20
`output terminal for providing a data signal labeled
`signal labeled "OE0”. Register 76 has an input terminal
`"MUX2'. Switch 58 has a first input terminal con
`connected to the output terminal of register 75, a first
`nected to the output terminal of register 56 for receiving
`control terminal for receiving clock signal KCMOS, a
`data signal MUX1, a second input terminal for receiving
`second control terminal connected to the output termi
`nal of inverter 81, and an output terminal for providing
`a reset logic value labeled 'O', a control terminal for
`25
`receiving output enable signal OE2, and an output ter
`a signal labeled “OE1'. Register 77 has an input termi
`minal for providing a data signal labeled "PT1'. Switch
`nal connected to the output terminal of register 76, a
`59 has a first input terminal connected to the output
`first control terminal connected to the output terminal
`terminal of register 57 for receiving data signal MUX2,
`of inverter 79, a second control terminal for receiving
`a second input terminal for receiving reset logic value
`mode control signal ASYNC, and an output terminal.
`30
`'0', and an output terminal for providing a data signal
`Register 78 has an input terminal connected to the out
`labeled "PT2'. Register 60 has an input terminal con
`put terminal of register 77, a first control terminal for
`nected to the output terminal of switch 58 for receiving
`receiving clock signal KCMOS, a second control termi
`nal for receiving mode control signal ASYNC, and an
`data signal PT1, a first control terminal, a second con
`trol terminal for receiving mode control signal
`output terminal for providing output enable signal OE2.
`35
`ASYNC, and an output terminal for providing a data
`Output registers 34 have two parallel, interleaved,
`signal labeled “QT1'. Register 61 has an input terminal
`output data paths. One output data path is through
`register 56, switch 58, and register 60 to final amplifier
`connected to the output terminal of switch 59 for re
`ceiving data signal PT2, a first control terminal, a sec
`62. The other output data path is through register 57,
`ond control terminal for receiving mode control signal
`switch 59 and register 61 to final amplifier 62. The par
`ASYNC, and an output terminal for providing a data
`allel data paths are controlled by clock signal MD90,
`signal labeled "QT2'. Final amplifier 62 has a first input
`and delayed clock signal KU. Output enable registers 48
`terminal connected to the output terminal of register 60
`provides output enable signal to switches 58 and 59
`for receiving data signal QT1, a second input terminal
`during a write cycle of memory 20. When clock signal
`connected to the output terminal of register 61 for re
`MD90 is a logic high, data signal MUX is sent through
`45
`ceiving data signal QT2, a first control terminal, a sec
`register 56 as data signal MUX1, while the data in the
`ond control terminal for receiving mode control signal
`other output data path is latched by register 57. When
`ASYNC, and an output terminal for providing data
`clock signal MD90 is low, data signal MUX, which was
`signal Q. Inverter 65 has an input terminal for receiving
`held in register 57 during the previous clock cycle, is
`delayed clock signal KU, and an output terminal.
`sent through register 57 as corresponding data signal
`50
`Switch 64 has a first input terminal for receiving de
`MUX2, while the next data signal MUX is latched in
`layed clock signal KU, a second input terminal con
`register 56.
`nected to the output terminal of inverter 65, a control
`Clock signal MD90 is generated from the falling edge
`terminal for receiving pipeline control signal PIPE2*,
`of clock signal CLK, whereas the data signal MUX is
`and an output terminal connected to the first control
`generated from the rising edge of CLK (see FIGS. 18
`55
`terminals of register 61 and final amplifier 62. Inverter
`and 19). There is an inherent propagation delay associ
`66 has an input terminal connected to the output termi
`ated with accessing a memory during a read or a write
`nal of switch 64, and an output terminal connected to
`cycle. In memory 20, a delay, measured from the time
`the first control terminal of register 60.
`an address is provided to address registers 26 to the time
`Output enable registers 48 includes inverters 70, 72,
`data signal MUX reaches output registers 34, is dupli
`79, and 81, NAND logic gate 71, and registers 73-78.
`cated by dummy path 46 during a read cycle. In other
`Inverter 70 has an input terminal for receiving chip
`words, dummy path 46 has various elements to track the
`select signal CS, and an output terminal. NAND logic
`propagation delay of memory 20, and provide clock
`gate 71 has a first input terminal connected to the output
`signal MD90 after a delay equal to the propagation
`terminal of inverter 70, a second input terminal for
`delay of memory 20. Because clock signal MD90 tracks
`65
`receiving write enable signal W, and an output termi
`the propagation delay of memory 20, MD90 switches in
`nal. Inverter 72 has an input terminal connected to the
`the middle of the data valid window of data signal
`output terminal of NAND gate 71, and an output termi
`MUX. (See FIG. 18 and FIG. 19.)
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`By using parallel data output paths, the validity per
`If output enable signal OE2 is a logic low, then logic
`iod of data signals MUX1 and MUX2 are greater than
`low data signals PT1 and PT2 are provided to the out
`the validity period of data signal MUX. During a read
`put terminal of final amplifier 62. In three-stage pipeline
`cycle, output enable signal OE2 is a logic high, so that
`mode, if write enable signal W' is a logic low, or chip
`data signals MUX1 and MUX2 will be provided to
`select signal CS' signal is a logic high, then the output
`registers 60 and 61, respectively. Data signals MUX1
`terminal of final amplifier 62 becomes a logic low three
`and MUX2 are changing only half as often as data signal
`cycles later after output enable signal OE2 becomes a
`logic low. In two-stage pipeline mode, the output termi
`MUX. Since the clock signal MD90 is correlated to the
`propagation delay of memory 20 by dummy path 46,
`nal of final amplifier 62 becomes a logic low two cycles
`clock signal MD90 tracks data signal MUX in terms of
`later.
`10
`process, supply, or temperature variations. Another
`Output enable signal OE2 is generated by output
`advantage of using parallel data paths controlled by a
`enable registers 48. Registers 73 and 74 are two phase
`dummy path is that if the frequency of clock signal
`clock registers that acquire and latch the logic state of
`CLK decreases, clock signal MD90 continues to match
`control signal CSW*. Register 73 is illustrated in more
`the propagation delay of memory 20, thereby staying
`detail in FIG. 6. Registers 75 and 76 register control
`signal CSW* for one clock cycle, and registers 77 and
`within the data valid window.
`Delayed clock signal KU controls the operation of
`78 register control signal CSW* for another clock cy
`registers 60 and 61. When pipelining control signal
`cle. In the three-stage pipeline mode, output enable
`PIPE2* is a logic high, clock signal KUOR is the same
`signal OE2 has the same logic state as control signal
`logic state as delayed clock signal KU. When clock
`CSW, registered for two clock cycles, and then pro
`20
`signal KUOR is a logic low, data signal PT1 is sent
`vided to output registers 34. In the two-stage pipeline
`through register 60 to become corresponding data sig
`mode, the logic state of output enable signal OE2 is
`nal QT1, while data signal QT2 is latched by register 61.
`equal to the logic state of control signal CSW, regis
`Also, while clock signal KUOR is a logic low, data
`tered for only one cycle. For operation in the two-stage
`signal QT2 is provided as output data signal Q by final
`pipeline mode, registers 75 and 76 are placed in a flow
`amplifier 62. While clock signal KUOR is a logic high,
`through mode. Registers 75 and 76 are similar to output
`data signal PT2 is sent through register 61 to become
`register 56 illustrated in FIG. 5.
`corresponding data signal QT2, while data signal QT1 is
`In the asynchronous mode, output data is generated
`latched by register 60. Also, data signal QT1 is provided
`directly from clock signal CLK. Clock signals MD90
`as output data signal Q through final amplifier 62. (See
`and KU, are ignored. The asynchronous mode is ac
`complished by adding a flow through mode to output
`FIG. 18 and FIG. 19)
`Delayed clock signal KU occurs slightly before the
`register 34. Registers 56, 57, 60, and 61 and final ampli
`rising edge of clock signal CLK, so that output data
`fier 62 receive mode control signal ASYNC" to provide
`signal Q will change at the same time as the rising edge
`the flow through mode. When mode control signal
`of clock signal CLK. Delayed clock signal KU is pro
`ASYNC is a logic low, data passes through output
`35
`vided by read control delay locked loop 44, which will
`registers 34 regardless of the state of the clock signals.
`be described later.
`Mode control signal ASYNC is also used to provided
`Memory 20 has a three-stage pipeline, that is, output
`a flow through mode for output enable registers 48.
`data signal Q corresponds to data located at an address
`When mode control signal ASYNC* is a logic low,
`which was accessed three clock cycles prior to receiv
`registers 75, 76, 77, and 78 are in flow through mode.
`ing output data signal Q. With reference to FIG. 18,
`An advantage of this method of mode control is that it
`note that the rising edge of delayed clock signal KU
`is accomplished electrically, allowing memory 20 to
`acquires data corresponding to address A0. On the
`operate in either mode by changing the logic state of an
`falling edge of delayed clock signal KU, data corre
`external input signal, instead of by changing a metal
`sponding to address A1 is acquired. Using parallel data
`layer, or some other manufacturing change.
`45
`registers reduces the possibility that wrong data will be
`Note that output registers 34 have two parallel data
`acquired during high speed operation by widening the
`paths in the illustrated embodiments. However, in other
`embodiments, more output data paths may be used. The