United States Patent (19)
`Shiomi et al.
`
`73) Assignee:
`
`(54) SEMICONDUCTOR INTEGRATED CIRCUIT
`CAPABLE OF SYNCHRONOUS AND
`ASYNCHRONOUS OPERATIONS AND
`OPERATING METHOD THEREFOR
`75 Inventors: Toru Shiomi; Shigeki Ohbayashi;
`Atsushi Ohba, all of Hyogo, Japan
`Mitsubishi Deniki Kabushiki
`Kabushiki Kaisha, Tokyo, Japan
`(21) Appl. No.: 691,615
`(22) Filed:
`Apr. 25, 1991
`30
`Foreign Application Priority Data
`Jun. 19, 1990 JP
`Japan .................................. 2-60847
`51) Int. C. ........................................... H03K 19/092
`52 U.S. C. ................................. 307/465; 307/272.2;
`307/475; 307/480, 365/189.05; 371/21.1
`58 Field of Search ................ 307/455, 480, 465-467,
`307/475, 272.2; 365/18905, 230.05; 371/21.1
`References Cited
`U.S. PATENT DOCUMENTS
`4,694,197 9/1987 Sprague .......................... 307/480 X
`4,756,006 7/1988 Rickard....
`... 307/480 X
`4,761,567 8/1988 Walters, Jr. et al.
`... 307/475 X
`4,766,572 8/1988 Kobayashi ...................... 365/89.05
`4,812,678 3/1989 Abe ..........
`... 307/465 X
`4,825,44 4/989 Kawata ........
`... 365/189,05
`4,857,773 8/1989 Takata et al. ....................... 307/.465
`4,942,318 7/1990 Kawana .............................. 307/.465
`
`(56)
`
`USOO5124589A
`Patent Number:
`11
`(45) Date of Patent:
`
`5,124,589
`Jun. 23, 1992
`
`... 307/480
`4,972,518 11/1990 Matsuo ..........
`5,003,204 3/1991 Cushing et al. ..................... 307/465
`5,017,813 5/1991 Galbraith et al. .............. 307/.465 X
`FOREIGN PATENT DOCUMENTS
`O161639 11/1985 European Pat. Off. ........... 371/21.1
`1-184798 7/1989 Japan .
`Primary Examiner-David Hudspeth
`Attorney, Agent, or Firm-Lowe, Price, LeBlanc &
`Becker
`ABSTRACT
`57
`A self-timed random-access memory device includes
`randomly accessible memory circuitry (7), a clock gen
`erator (9) responsive to an external clock signal for
`generating an internal clock signal, an input circuit (8)
`responsive to the internal clock signal for latching and
`outputting a supplied input signal, an output circuit (11)
`responsive to the internal clock signal for latching and
`outputting an output from the memory device, and
`circuitry (81, 82,85,86; 115,116,124, 125; 135,136,144,
`145) responsive to a through state specifying signal
`(TH, THM) for disabling the latch function of the input
`circuit and the output circuit. The memory device can
`be switched, in response to the through state specifying
`signal, between a mode operating synchronously with
`the externally supplied clock signal and another mode
`operating asynchronously with the externally supplied
`clock signal.
`
`24 Claims, 20 Drawing Sheets
`
`INPUT DATA
`
`D RETAIN G
`DS CLOCK
`
`STANDARD RAM
`CIRCUIT
`
`
`
`BLOCK
`
`OUTPUT
`DATA
`RETAIN
`DS CLOCK
`
`
`
`poo
`
`DOut
`
`
`
`
`
`BR
`CS
`W
`
`TH
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 1
`
`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 1 of 20
`
`5,124,589
`
`FIG.1
`
`PRIOR ART
`
`7
`
`
`
`
`
`
`
`MEMORY CEL
`
`ARRAY
`
`
`
`
`
`- - - - - - - - ,3
`
`Y ADDRESS BUFFER/DECODER
`
`Y ADDRESS
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 2
`
`

`

`U.S. Patent
`U.S. Patent
`
`June 23, 1992
`
`Sheet 2 of 20
`
`5,124,589
`5,124,589
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`STMicroelectronics, Inc., Ex. 1009
`~ TPR2021-01593
`Page 3
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 3
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`
`
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`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 3 of 20
`
`5,124,589
`
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`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 4
`
`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 4 of 20
`
`5,124,589
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`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 5
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`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 5 of 20
`
`5,124,589
`
`
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 6
`
`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 6 of 20
`
`5,124,589
`
`
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 7
`
`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 7 of 20
`
`5,124,589
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`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 8
`
`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 8 of 20
`
`5,124,589
`
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`STMicroelectronics, Inc., Ex. 1009
`" TPR2021-01593
`
`Page 9
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 9
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`
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`
`
`
`
`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 9 of 20
`
`5,124,589
`
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`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 10
`
`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 10 of 20
`
`5,124,589
`
`
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 11
`
`

`

`U.S. Patent
`U.S. Patent
`
`June 23, 1992
`
`Sheet 11 of 20
`
`5,124,589
`5,124,589
`
`
`
`FIG.11
`F1G.11
`
`
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`
`Page 12
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 12
`
`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 12 of 20
`
`5,124,589
`
`
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 13
`
`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 13 of 20
`
`5,124,589
`
`FIG13
`
`
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 14
`
`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 14 of 20
`
`5,124,589
`
`
`
`1 [[108] [9
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 15
`
`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 15 of 20
`
`5,124,589
`
` LINDYID
`
`TIWNYSLNI
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`
`Page 16
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 16
`
`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 16 of 20
`
`5,124,589
`
`
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 17
`
`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 17 of 20
`
`5,124,589
`
`
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 18
`
`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 18 of 20
`
`5,124,589
`
`
`
`BONE|83-338
`
`1100810
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 19
`
`

`

`U.S. Patent
`
`June 23, 1992
`
`Sheet 19 of 20
`
`5,124,589
`
`
`
`TVN}} BIN I
`
`11008 I O
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 20
`
`

`

`U.S. Patent
`U.S. Patent
`
`June 23, 1992
`
`Sheet 20 of 20
`
`5,124,589
`5,124,589
`
`
`
` LINIDYIO
`
`TWNUYSLNI
`T\/NHB1N I
`
`1 I (108 I O
`
`STMicroelectronics, Inc., Ex. 1009
`* IPR2021-01593
`
`Page 21
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 21
`
`

`

`1.
`
`SEMICONDUCTOR INTEGRATED CIRCUIT
`CAPABLE OF SYNCHRONOUS AND
`ASYNCHRONOUS OPERATIONS AND
`OPERATING METHOD THEREFOR
`
`5
`
`5,124,589
`2
`and transmits the data to the data output buffer 6. The
`data output buffer 6, controlled by a control signal from
`the R/W control circuit 1, provides output data Dout
`corresponding to the signal transmitted from the sense
`amplifier 5. The operation will be briefly described
`below.
`When the chip-select signal CS is in an inactivation
`state at 'H', the R/W control circuit 1 and data output
`buffer 6 are put into a disable state, where writing and
`reading of data are inhibited. At this time, the output
`data Dout delivered from the data output buffer 6 is
`brought to a predetermined level, for example, at "L",
`or a high impedance state.
`When the chip-select signal CS is turned into an acti
`vation state at "L', the X address buffer decoder 2 and
`the Yaddress buffer decoder 3, respectively, accept and
`decode external X address and Y address and generate
`a row select signal and a column select signal. The
`memory cell at the intersection of the row and column
`designated by the row and column select signals is se
`lected.
`When the write-enable signal WE is at "H" level, a
`data-read mode is designated. At this time, the R/W
`control circuit 1 puts the sense amplifier 5 and data
`output buffer 6 into an activated state. The activated
`sense amplifier 5 senses and amplifies the data in the
`selected memory cell and transmits the data to the data
`output buffer 6. The data output buffer 6 outputs the
`output data Dout corresponding to the transmitted data
`from the sense amplifier 5.
`When the write-enable signal WE is at "L", a data
`write mode is designated. At this time, the R/W control
`circuit 1 put the sense amplifier 5 into an inactivated
`state and at the same time put the data output buffer 6
`into an output disable state, thereby setting its output
`data Dout to a fixed level.
`Meanwhile, the R/W control circuit 1, responding to
`the signals CS and WE, generates internal data from the
`input signal Din and write the internal data into the
`selected memory cell. The internal data is generated
`from the externally supplied input signal Din when the
`writeenable signal WE is brought to the activation state
`at 'L'.
`Writing and sensing of data in the ECL RAM are
`performed according to a current value of the current
`flowing through the selected column (pair of bit lines).
`The R/W control circuit 1 applies a signal correspond
`ing to the input signal Din to the bases of the bipolar
`transistors for writing provided for each bit line,
`whereby a change of the current corresponding to the
`input data is produced in the selected column and writ
`ing of the data into the memory cell is achieved.
`The semiconductor menory of the above described
`ECL RAM or the like is frequently used in combination
`with a logic circuit. In such a case, to achieve high
`speed and accurate data inputting and outputting, it is
`preferred to synchronize the logical operation of the
`logic circuit with write/read operation in the semicon
`ductor memory. In consideration of such situation, a
`synchronous RAM, i.e., a self-timed RAM (hereinafter
`briefly called "STRAM"), in which input and output of
`signals are controlled according to a clock signal used
`as a synchronizing signal is developed.
`FIG. 2 is a block diagram schematically showing the
`basic circuit configuration of such STRAM. Referring
`to FIG. 2, the STRAM is integrated on a chip 900, and
`it includes a standard RAM circuit block 7 having the
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention generally relates to a semicon
`ductor integrated circuit operable in synchronous
`mode, and specifically to a synchronous semiconductor
`integrated circuit including an ECL (Emitter Coupled
`Logic) circuit as its component and performing input
`ting and outputting of signals using a clock signal as a
`synchronizing signal.
`15
`More particularly, the present invention relates to a
`synchronous semiconductor integrated circuit includ
`ing a bipolar RA (Random Access Memory) or a BiC
`MOSRAM as its internal circuit.
`20
`2. Description of the Related Art
`Various types of memories have been developed and
`put into practice using semiconductor circuit integra
`tion technics. Among these memories, there is a high
`speed memory referred to as ECL RAM. The ECL
`RAM includes a pair of emitter-coupled bipolar transis
`25
`tors as its basic memory cell and operates at ECL levels.
`The ECL RAM usually uses 0 V, or ground potential,
`as its first power source potential VCC and uses a nega
`tive potential of -4.5V or -5.2 Vas its second power
`source potential VEE. Of the ECL levels, the high level
`30
`("H") is about -09 V and the low level ("L') is about
`-1.7 V.
`FIG. 1 is a diagram schematically showing an overall
`arrangement of a conventional semiconductor memory
`comprising, for example, an ECL RAM. Referring to
`35
`FIG. 1, the semiconductor memory 7 includes a mem
`ory cell array 4 with memory cells arranged in a matrix
`of rows and columns. The memory cell array 4 includes
`a plurality of word lines arranged along the rows and a
`plurality of bit lines arranged along columns. A column
`40
`of an ECL RAM in general is made of a pair of bit lines
`and one memory cell is located at each intersection of
`the pairs of bit lines and word lines.
`In order to select a desired memory cell from the
`memory cell array 4, there are provided an X address
`45
`buffer decoder 2 and a Y address buffer decoder 3. The
`X address buffer decoder 2 buffers an X address exter
`nally supplied thereto, generates an internal row ad
`dress and decodes the internal row address, thereby
`selecting a corresponding word line from the memory
`50
`cell array 4. The Yaddress buffer decoder 3 buffers a Y
`address externally supplied thereto, generates an inter
`nal column address and decodes the internal column
`address, thereby selecting a column (a pair of bit lines)
`when the memory is of "x 1 bit" arrangement.
`55
`The semiconductor memory further includes an R/W
`control circuit 1, a sense amplifier 5, and a data output
`buffer 6. The R/W control circuit 1 is supplied with a
`chip-select signal CS, a write enable signal WE, and
`input data Din, and in data writing, it writes the data
`corresponding to the input data Din into a selected
`memory cell of the memory cell array 4 while disabling
`the sense amplifier 5. The R/W control circuit 1 also
`controls the operation of the data output buffer 6 in
`response to the chip-select signal CS and write-enable
`signal WE.
`The sense amplifier 5 senses and amplifies the data in
`a memory cell selected from the memory cell array 4
`
`10
`
`65
`
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`Page 22
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`O
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`15
`
`5,124,589
`4.
`3
`nals (corresponding to the signals WE and CS from the
`same structure as that of the RAM shown in FIG. 1, and
`retaining circuits 8c and 8d), various pulse signals neces
`it also includes an input data retaining circuit 8, a clock
`sary for data writing, which pulse signals control the
`signal generator 9, a write pulse generating circuit 10
`operations of the sense amplifier and R/W control cir
`and an output data retaining circuit 11, for performing
`cuit 1 included in the standard RAM circuit block 7.
`data inputting to and data outputting from the standard
`The output data retaining circuit 11 is formed of a
`RAM circuit block 7.
`master-slave register similarly to the input data retain
`The clock generator 9 buffers an externally supplied
`ing circuit 8, and includes a master circuit 79 which
`clock signal (for example, system clock) CLK and gen
`latches the signal applied to its D input in response to
`erates an internal clock signal.
`the rising of the internal clock signal from the clock
`The input data retaining circuit 8 receives the clock
`generator 9, and a slave circuit 80 which latches the Q
`signal from the clock generator 9 at its clock input
`output of the master circuit 79 in response to the falling
`CLOCK, latches input signals (address ADD, input
`of the internal clock signal from the clock generator 9.
`data Din, chip-select signal CS, and write-enable signal
`The output from the output data retaining circuit 11 is
`WE) supplied to its input terminal D, and outputs these
`supplied to an output buffer 13. The output buffer 13, in
`signals from its output terminal Q in response to the
`response to an output from the output data retaining
`clock signal.
`circuit 11, drives an output signal line at a high speed
`The write pulse generating circuit 10 generates a
`and outputs an output data Dout.
`write pulse for controlling data writing in response to
`The STRAM further includes a multiplex circuit 12.
`the internal clock signal from the clock generator 9 and
`The standard RAM 7 shown in FIG. 1 controls the
`the internal control signals (generated in response to the
`20
`signals CS and WE) from the input data retaining circuit
`output state of the data output buffer 6 by means of the
`8. The write pulse is a pulse signal having the pulse
`R/W control circuit 1. In the STRAM, however, an
`read out data signal is transmitted to the output buffer
`width corresponding to the period that the write-enable
`circuit 13 through the output data retaining circuit 11
`signal WE is held in an activation state in the RAM
`performing a clocked operation. In this way, the opera
`shown in FIG. 1.
`25
`tion of the output buffer circuit 13 is not controlled by
`The output data retaining circuit 11 receives the in
`an R/W control circuit, and the output state of the
`ternal clock signal from the clock generator 9 at its
`output buffer circuit 13 is essentially controlled by the
`clock input CLOCK, latches the data from the standard
`multiplex circuit 12.
`RAM circuit block 7 received at its input terminal D
`The multiplex circuit 12, depending on the operating
`outputs the output data Dout from its output terminal Q
`30
`mode of the STRAM, selectively supplies either of the
`in response to the internal clock signal.
`output data from the standard RAM circuit block 7 and
`The STRAM shown in FIG. 2 differs from the stan
`data generated from the signals transmitted from the
`dard RAM shown in FIG. 1 in that its write operation
`input data retaining circuits 8c and 8d to the output data
`is not started by the signals CS and WE, but started by
`retaining circuit 11.
`the clock signal CLK and that the write pulse is gener 35
`In the data-write operation (when both the signals CS
`ated by the write pulse generating circuit 10 within the
`and WE are in the activation state) and at the chip
`chip 900.
`unselect period (when the signal CS is in the inactiva
`FIG. 3 is a block diagram showing in more detail the
`tion state), the multiplex circuit 12 supplies a signal at a
`circuit configuration of the STRAM shown in FIG. 2.
`fixed level of, for example, "L", to the output data
`Referring to FIG. 3, the input data retaining circuit 8
`40
`retaining circuit 11. When the signal WE is in the inacti
`includes a retaining circuit 8a which latches and outputs
`vation state and the signal CS is in the activation state
`an externally applied address signal ADD (which in
`whereby the data-read operation is indicated, the multi
`cludes both X address and Y address), a retaining circuit
`plex circuit 12 transmits the signal sensed and amplified
`8b which latches and outputs an externally applied input
`by the sense amplifier of the standard RAM circuit
`signal Din, a retaining circuit 8c which latches and
`45
`block 7 to the output data retaining circuit 11.
`outputs the externally applied write-enable signal WE,
`The register type STRAM shown in FIG.3 has mas
`and a retaining circuit 8d which latches and outputs the
`externally applied chip select signal CS.
`ter-slave registers triggered by the edges of the internal
`clock signal as its signal input and output circuits and,
`Each of the retaining circuits 8a to 8d is formed of a
`although a read out data is output with a delay of one
`master-slave register which is triggered at an edge of
`50
`clock cycle, it has such an advantage that its cycle time
`the internal clock signal. More specifically, the retain
`can be made essentially shorter than that in the standard
`ing circuit 8a is formed of a master circuit 14a and a
`RAM because valid data is output in response to the
`slave circuit 15a which receives Q output from the
`rising of the clock signal. The data-read operation will
`master circuit 14a. The retaining circuit 8b includes a
`be described below with reference to FIG. 4
`master circuit 14b and a slave circuit 15b which receives
`The master circuits 14a to 14d and 79 are brought into
`Q output from the master circuit 14b. The retaining
`a latch state when the clock signal CLK is at "H" and
`circuit 8c includes a master circuit 14c and a slave cir
`into a through state when the clock signal CLK is at
`cuit 15c. The retaining circuit 8d includes a master cir
`"L". The slave circuits 15a to 15d and 80 are brought
`cuit 14d and a slave circuit 15d.
`into the through state when the clock signal CLK is at
`Each of the master circuits 14a to 14d latches a signal
`"H" and into the latch state when the clock signal CLK
`applied to the D input at the leading edge of the internal
`is at 'L'. Here, the latch state means a state that a cir
`clock signal from the clock generator 9. Each of the
`cuit continuously retains a latched signal and outputs
`slave circuits 15a to 15d latches the signal supplied from
`the signal regardless of the kind of the input signal. The
`its corresponding master circuit at the trailing edge of
`through state means a state that a circuit allows an
`the internal clock signal.
`65
`applied input signal to unchangedly pass therethrough.
`The write pulse generating circuit 10 is driven by the
`Signals latched by the master circuits 14a to 14d and 79
`clock signal from the clock signal generator 9 and gen
`are the input signals which have already been provided
`erates, at predetermined timings in response to the sig
`
`55
`
`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 23
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`10
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`5
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`20
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`thereto before the clock signal CLK rises to "H". The
`11. At this time, since the master circuit 79 of the output
`signals latched by the slave circuits 15a to 15d and 80
`data retaining circuit 11 is in the latch state, the data
`are the signals which have already been given thereto
`read out during the preceding cycle is output through
`before the clock signal CLK falls to "L".
`the output buffer circuit 13.
`In the data-read operation, the chip-select signal CS is
`Then, upon rising to "H" of the clock signal CLK
`set to "L" and the write-enable signal WE is set to "H".
`once again, the master circuits 14a to 14d and 79 are
`An external address ADD is set to the values designat
`brought to the latch state and the slave circuits 15a to
`ing a desired memory cell. When a time ts elapsed after
`15d and 80 are brought into the through state, and the
`above described operations are repeated. As a result,
`signals CS, WE, and ADD were settled, the clock signal
`the data read out in the preceding cycle is output as the
`CLK rises to "H". Here, the time tis called a setup time
`output data Dout through the master circuit 79 and the
`and each signal must be in the settled state when this
`time has passed. The signals CS, WE, and ADD are
`slave circuit 80 of the output data retaining circuit 11,
`required to be held unchanged at least for a period th
`and the output buffer circuit 13. The new output data
`after the rise to "H" of the clock signal CLK. The
`Dout is output with a delay time tipR after the rise of the
`period this called a hold time. Throughout the periods
`clock signal CLK, the delay time being provided by the
`output data retaining circuit 11 and the output buffer
`of the setup time ts and the hold time ts, each signal CS,
`WE, and ADD remains in the settled state.
`circuit 13. The delay time toR is shorter than the pulse
`With the rise to "H" of the clock signal CLK, the
`width CLK.PWH of the clock signal CLK (the period
`internal clock signal from the clock generator 9 also
`that the clock signal CLK is at "H'), so that a settled
`output data Dout is output before the slave circuit 80 of
`rises to "H'. The master circuits 14a to 14d and 79 are
`thereby brought into the latch state. At this time, since
`the output data retaining circuit 11 is brought to the
`the signals WE, CE, and ADD are already settled in
`latch state.
`specific states, the signals latched by the master 14a to
`As described in the foregoing, although memory cell
`14d and 79 are the signals which have already been
`data Qn corresponding to the address An given at the
`given thereto before the clock signals CLK rises to
`timing of the rise of the clock signal CLK is output
`25
`during the following clock cycle, there is no address
`'H'.
`On the other hand, in response to the rise to "H" of
`access time (the time required from application of an
`address signal to appearance of the output data in a
`the clock signal CLK, the slave circuits 15a to 15d and
`80 are brought into the through state. Therefore in
`settled state) as is present in the standard RAM shown
`response to the rise to "H" of the clock signal CLK, the
`in FIG. 1. Since the output data reaches a settled state
`signals which have been given are transmitted through
`with only the delay time toR after the rise of the clock
`signal through the output slave circuit 80 and the output
`the slave circuits to their associated circuits.
`When the clock signal CLK falls to "L", the slave
`buffer circuit 13, one cycle time toyc (READ) can be
`circuits 15a and 15d and 80 are brought into latch state
`shortened and high speed data reading can be achieved.
`and the master circuits 14a to 14d are brought into the
`In the data-read cycle, at the timing of the rise to "H"
`of the clock signal CLK, the chip-select signal CS is set
`through state. With the fall to "L" of the clock signal
`CLK, the addresses transmitted to the X decoder and Y
`to "L" and the write-enable signal WE is set to "L" and
`decoder are brought into their settled state, whereby
`further, an address ADD is settled, and the input data
`Din to the input data retaining circuit 8b is settled. In
`the selected row and selected column are made definite
`and a corresponding memory cell is selected from the
`this data-write cycle, selection of a memory cell by the
`memory cell array.
`X decoder and Y decoder is performed similarly as in
`The write pulse generating circuit 10 generates a
`the data-read cycle. At this time, the write pulse gener
`one-shot pulse signal in response to the rise of the inter
`ating circuit 10 receives signals from the input data
`nal clock signal and supplies a control signal obtained
`retaining circuits 15c and 15d in response to the rise of
`through the logical product of this one-shot pulse signal
`the clock signal from the clock generator 9 and gener
`and the signal WE to the R/W control circuit of the
`ates a control signal (write pulse) necessary for data
`writing at a predetermined timing. Thereupon, the
`block 7 as the write pulse. In response to this control
`signal from the write pulse generating circuit 10, the
`R/W control circuit accepts an input data Din and
`transmits the data to a selected memory cell, while it
`R/W control circuit within the standard RAM circuit
`block 7 is operated to activate the sense amplifier and, at
`brings the sense amplifier into an inactivated state.
`the same time, ignore an input data from the input data
`On the other hand, the multiplex circuit 12, in re
`retaining circuit 8. By the activated sense amplifier, the
`sponse to the state of the signals from the input data
`data in the memory cell selected by the X decoder and
`retaining circuits 8c and 8d indicating the data-write
`Y decoder is sensed and amplified to be applied to the
`mode, ignores the output data from the standard RAM
`multiplex circuit 12. The multiplex circuit 12, since the
`circuit block 7 and continuously transmits a signal at a
`55
`signals from the input data retaining circuits 8c and 8d
`predetermined level (for example, "L' level) produced
`are indicating the data-read mode, allows the data from
`from these signals to the output data retaining circuit 11.
`the standard RAM circuit block 7 to pass therethrough.
`Therefore, in the write cycle, the data writing is per
`When the data-read operations are successively per
`formed within one clock cycle (the period covering the
`period (a) and the period (B) in FIG. 4). The data writ
`formed as shown in FIG. 4, the states of the input data
`retaining circuits 8c and 8d are set so as to continuously
`ing is also performed in synchronization with the clock
`indicate the data-read mode, and during these periods,
`signal and, hence, CS- or WE- access time is not re
`the multiplex circuit 12 successively transmits the out
`quired. Since it is only required that some particular
`put data from the sense amplifier of the standard RAM
`signals are settled at the timing of the rise of the clock
`circuit block 7 to the output data retaining cirguit 11.
`signal CLK, high-speed data writing can be achieved.
`65
`Therefore, at the end of the periods (A) and
`indi
`In the above case, the decoding timing by the X de
`cated in FIG. 4, the data from a selected memory cell is
`coder and Y decoder is not controlled by the clock
`delivered at the input of the output data retaining circuit
`signal, and the decoding operation is performed in re
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`STMicroelectronics, Inc., Ex. 1009
`IPR2021-01593
`Page 24
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`The slave circuit 15 includes pairs of emitter coupled
`sponse to received signals, i.e., the decoding operation
`npn bipolar transistors 33/34, 41/42, and 35/43. The
`is performed in response to a settled address. Data writ
`transistor 33 has its collector connected with the first
`ing or data reading in the standard RAM circuit block 7
`power source potential 47 through a resistor 31 and its
`is performed upon generation of a signal for setting the
`base connected with the base of the transistor 27. The
`R/W control circuit in the data-write mode or the data
`transistor 34 has its collector connected with the first
`read mode, the signal being generated by the write pulse
`power source potential 47 through a resistor 32 and its
`generating circuit 10 at predetermined timing in re
`base connected with the base of the transistor 26.
`sponse to the rise of the clock signal CLK.
`The transistor 41 has its collector connected with the
`FIG. 5 is a diagram showing a specific example of a
`collector of the transistor 34 and the base of the transis
`circuit configuration of the input data retaining circuits
`tor 38 and its base connected with the first power
`8a to 8d shown in FIG. 3. Since the input data retaining
`source potential 47 through a transistor 37 and a diode
`circuits 8a to 8d all have the same circuit configuration,
`39 and, also, connected with a constant current source
`the input data retaining circuit 8, and the input master
`44. The transistor 42 has its collector connected with
`circuit 14 and input slave circuit 15 are representatively
`the base of the transistor 37 and the collector of the
`shown.
`transistor 33 and its base connected with the first power
`Referring to FIG. 5, the input data retaining circuit
`source potential 47 through a transistor 38 and a diode
`includes the input master circuit 14 and the input slave
`40 and, also, connected with a constant current source
`circuit 15 each of which is formed of an ECL circuit.
`45.
`The master circuit 14 and slave circuit 15 of such ECL
`The transistor 35 has its collector connected with the
`20
`circuit configuration have, as their operating power
`emitters in common of the transistors 33/34 and its base
`sources, a first power source potential Vcc 47 being, for
`supplied with the internal clock signal CLKBThe tran
`example, ground potential and a second power source
`sistor 43 has its collector connected with the common
`potential VEE48 being usually set to -5.2 V or -4.5V.
`emitter of the transistors 41/42 and its base supplied
`The master circuit 14 includes three pairs of emitter
`with the complimentary internal clock signal NCLKB.
`25
`coupled npn bipolar transistors 18/19, 26/27, and 20/28.
`The emitters in common of the transistors 35/43 are
`The npn bipolar transistor 18 has its base supplied
`connected with a constant current source 36. The slave
`with an input signal IN and its collector connected with
`circuit 15 further includes npn bipolar transistors 37 and
`the first power source potential 47 through a resistor 16.
`38 and diodes 39 and 40. The transistor 37 has its collec
`The npn bipolar transistor 19 has its base supplied with
`tor connected with the collectors of the transistors 42
`a reference potential VBB and its collector connected
`and 33, and its emitter connected with an output node
`with the first power source potential 47 through a resis
`NA. The transistor 38 has its collector connected with
`tor 17.
`the first power source potential 47, its base connected
`The npn bipolar transistor 26 has its collector con
`with the collectors of the transistors 39 and 34, and its
`nected with the collector of the transistor 19 and its base
`emitter connected with an output node A. The diode 39
`35
`connected with a constant current source 29 and also
`has its anode connected with the output node NA and
`connected with the first power source potential 47
`its cathode connected with the base of the transistor 41.
`through a transistor 22 and a diode 24. The transistor 27
`The diode 40 has its anode connected with the output
`has its coll