United States Patent 19
`Stephens, Jr. et al.
`
`||||||||||
`US00554.8560A
`5,548,560
`11
`Patent Number:
`Aug. 20, 1996
`45) Date of Patent:
`
`54 SYNCHRONOUS STATIC RANDOMACCESS
`MEMORY HAVING ASYNCHRONOUS TEST
`MODE
`
`(75
`
`Inventors: Michael C. Stephens, Jr.; Ajit K.
`Medhekar, both of San Jose;
`Chitranjan N. Reddy, Milpitas, all of
`Calif.
`
`73) Assignee: Alliance Semiconductor Corporation,
`San Jose, Calif.
`
`Appl. No.: 423,822
`21
`22 Filed:
`Apr. 19, 1995
`151) Int. Cl. ............................................ G11C 8/00
`52 U.S. C. ........................ 365/233.5; 365/233; 365/194
`58) Field of Search ................................. 365/233.5, 233,
`365/194, 201; 326/93; 327/14
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,047,984 9/1991 Monden ............................... 365,233.5
`5,107,465 4/1992 Fung et al.......
`... 365/230.08
`5,124,589
`6/1992 Shiomi et al. .......................... 307.465
`5,306,958 4/1994 Reddy et al. .......
`... 307/265
`5,357,480 10/1994 Vinal .................................... 365/233.5
`Primary Examiner-David C. Nelms
`Assistant Examiner-Son Dinh
`
`Attorney, Agent, or Firm-Bradley T. Sako
`(57)
`ABSTRACT
`A burst mode static random access memory (SRAM) (10) is
`disclosed that includes an address transition detect signal
`(ATD) generating circuit (14) that provides either an asyn
`chronous ATD signal (a-ATD) or a synchronous ATD signal
`(s-ATD) depending upon the logic state of a mode signal
`(ATM). A rising edge of the a-ATD signal is generated by a
`change in address. A falling edge is generated after a
`predetermined time period according an a-ATD circuit (60)
`within the ATD generating circuit (14). A falling edge of the
`S-ATD signal is generated by a rising edge of an internal
`synchronous clock pulse (CLAT). The rising edge of the
`S-ATD signal is generated when data are sensed on data lines
`(40) by an end-of-cycle circuit (20). If ATM is high, the
`a-ATD signal is used for timing on the SRAM (10). If ATM
`is low, timing is determined according to the s-ATD signal.
`An ATD control circuit (16) is provided to generate I/O
`control signals in response to the ATD signal (eithers-ATD
`or a-ATD). On a rising edge of the ATD signal the I/O
`control signals place the SRAM (10) in a precharge/equal
`ization state wherein I/O lines (24, 32,40) are equalized and
`sensing circuits (28, 34) are disabled. On a falling edge of
`the ATD signal, the SRAM (10) is placed in a read/write
`mode wherein the I/O lines (24, 32, 40) are ready to sense
`read data or be driven by written data, and sensing circuits
`(28, 34) are enabled for a read operation, or alternatively
`disabled for a write operation.
`22 Claims, 6 Drawing Sheets
`
`10 N NCLK ALE CLAT ALE ATM ADV
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ATD
`APR GENERATING
`CIRCUIT
`14
`
`NCLKCLATATM
`
`WRITE
`ENABLE
`CIRCUIT
`
`
`
`NCLK
`
`CLAT
`
`ATD
`CONTROL
`CIRCUIT
`16
`
`
`
`If OSAEN
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`U.S. Patent
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`Aug. 20, 1996
`
`Sheet 1 of 6
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`5,548,560
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`AYOWHW
`
`WLV
`
`IOULNOD
`
`aLv
`
`Navso/I
`
`91
`
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`LINOUIO
`dime
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`
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`
`AQVWLY4JTVLYTO
`ATVYION
`
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`Ol
`
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`
`LINDA
`
`vl
`
`
`
`WILVLVTOWTION
`
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`ALTIM
`
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`
`LINDUID
`
`81
`
`WLY
`
`avbr
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`WIONe|9P
`
`_
`
`ivi
`
`XyTO
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`U.S. Patent
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`Aug. 20, 1996
`
`Sheet 2 of 6
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`5,548,560
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`ADD
`
`
`
`-------
`
`ADD
`
`a-ATD
`CIRCUIT
`60
`
`
`
`
`
`
`
`
`
`ALE
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`
`
`ADV
`
`
`
`WES
`
`
`
`
`
`S-ATD
`CIRCUIT
`62
`
`ATM
`
`ATD
`SELECT
`CIRCUIT
`64
`
`a-ATD
`O
`s-ATD
`
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`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 3 of 6
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`5,548,560
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`ADD
`
`a-ATD
`CIRCUIT
`60
`
`- - - - - - -
`
`C
`
`
`
`WEP
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`U.S. Patent
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`Aug. 20, 1996
`
`Sheet 4 of 6
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`5,548,560
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`NCLK
`
`CLAT
`
`WRITE
`ENABLE
`BUFFER
`70
`
`
`
`X
`
`Cdo
`L
`
`L3 it 4
`
`y
`
`Y
`
`WES
`
`
`
`I/OSAEN Q
`
`NQ
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`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 5 of 6
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`5,548,560
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`ADD
`
`a-ATD
`
`BEQ
`
`SAEN
`
`V/OEQ
`
`\
`
`Q
`
`\
`
`Q
`
`Ww(;———
`
`dl
`
`VOSAEN
`
`\
`
`d2
`
`Fig. 8
`
`Q
`
`\
`
`CLAT
`
`s-ATD
`
`BEQ
`
`SAEN
`
`1/OEQ
`
`VOSAEN
`
`Q/NQ
`
`EOC
`
`Fig. 9
`
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`U.S. Patent
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`Aug. 20, 1996
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`Sheet 6 of 6
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`5,548,560
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`1.
`SYNCHRONOUS STATIC RANDOMACCESS
`MEMORY HAVING ASYNCHRONOUS TEST
`MODE
`
`5,548,560
`
`TECHNICAL FIELD
`The present invention relates generally to semiconductor
`random access memories, and more particularly to synchro
`nous static random access memories (SRAMs).
`
`10
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`15
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`30
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`35
`
`BACKGROUND OF THE INVENTION
`Static random access memories (SRAMs) may be
`designed as asynchronous or synchronous devices. The
`timing of an asynchronous SRAM typically operates in
`response to externally provided signals. For example, it is
`known in the prior art for asynchronous SRAMs to generate
`an internal timing signal in response to a change in address.
`Commonly-owned U.S. Pat. No. 5,306,958, entitled HIGH
`SPEED ADDRESSTRANSITION DETECTION CIRCUIT
`20
`and filed on May 6, 1992, discloses an address transition
`detection circuit for generating a timing pulse in response to
`either a low-to-high or high-to-low external address input
`transition.
`Unlike asynchronous SRAMs, most signals in synchro
`nous SRAMs are referenced to an external system clock.
`Input and output signals are latched synchronous with the
`system clock. While asynchronous SRAMs are presently
`more common than synchronous SRAMs, increasingly,
`more computer systems are designed to employ synchronous
`SRAMs (typically as cache memory for a microprocessor).
`A consequence of the two different types SRAMs (syn
`chronous and asynchronous) is that integrated circuit and
`systems manufacturers must employ different test programs
`and/or machines for the two different types of SRAMs.
`U.S. Pat. No. 5,124,589 issued to Shiomi et al. on Jun. 23,
`1992 discloses an SRAM device capable of synchronous and
`asynchronous operations. Shiomi et al. illustrates both bipo
`lar and BiCMOS embodiments of an asynchronous SRAM
`having additional input and output circuits. A signal (TH) of
`a predetermined level is used to disable a latch function of
`input and output circuits allowing externally supplied sig
`nals to the circuits to pass through. The input and output
`circuits include master and slave registers. The Shiomi et al.
`device has separate data inputs and outputs. During syn
`chronous operation of the Shiomi et al. device the master
`register latches on the rising edge of a clock signal while the
`slave register is disabled. On the subsequent falling edge of
`the clock signal the slave register is latched and the master
`register is disabled.
`In a bipolar embodiment of the Shiomi et al. patent, the
`disabling circuit requires a signal TH greater than the VEE
`voltage for the circuit. In a BiCMOS embodiment the
`disabling circuit requires a third voltage for placing an
`NMOS device into non-saturation. In both the bipolar and
`BiCMOS illustrations the third voltage is either provided
`separately via an additional pad or separate circuit provided
`to generate the voltage on the chip.
`
`45
`
`50
`
`55
`
`SUMMARY OF THE INVENTION
`It is an object of the present invention to provide a
`synchronous SRAM capable of asynchronous operation that
`includes data ports functioning as inputs or outputs.
`It is a further object of the present invention to provide a
`synchronous SRAM with a memory array that can be tested
`using conventional asynchronous SRAM test equipment.
`
`65
`
`2
`It is a further object of the present invention to provide a
`synchronous SRAM with a memory array that can be tested
`using conventional asynchronous SRAM test programs.
`It is a further object of the present invention to provide a
`low-power synchronous SRAM having an asynchronous
`mode of operation.
`It is a further object of the present invention to provide a
`CMOS synchronous SRAM having an asynchronous test
`mode.
`It is a further object of the present invention to provide a
`synchronous SRAM having an asynchronous mode for
`detecting slow or faulty memory cells.
`According to the present invention a synchronous SRAM
`having an asynchronous test mode is provided. During
`synchronous operation a rising clock edge is used to bring a
`synchronous timing signal (s-ATD) to an active state. Upon
`a change of state of data input/output lines, indicating data
`has been read from or written to the memory array, an end
`of cycle pulse is generated which returns s-ATD to its
`previous state. During asynchronous operation an asynchro
`nous timing signal (a-ATD) is generated according to a
`transition in address, and remains in an active state for a
`predetermined amount of time.
`According to one aspect of the present invention, an ATD
`generating circuit provides either the s-ATD signal or the
`a-ATD signal according to an external mode signal. The
`ATD signal (eithers-ATD or a-ATD) is provided to an ATD
`control circuit which provides the appropriate timing to a
`number of control signals for the input/output (I/O) portions
`of the circuit. In the preferred embodiment the timing
`controlled I/O portions include bit line equalization circuits,
`sense amplifier enable circuits, I/O line equalization circuits,
`and I/O sense amplifier enable circuits.
`Other objects and advantages of the invention will
`become apparent in light of the following description
`thereof.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block schematic diagram illustrating the
`preferred embodiment of the present invention.
`FIG. 2 is a schematic diagram illustrating the address
`buffer of the preferred embodiment of the present invention.
`FIG. 3 is a block diagram illustrating the ATD generating
`circuit of the preferred embodiment of the present invention.
`FIG. 4 is a schematic diagram illustrating the s-ATD
`generating circuit and the ATD select circuit of the preferred
`embodiment of the present invention.
`FIG. 5 is a block schematic diagram illustrating the ATD
`control circuit of the preferred embodiment of the present
`invention.
`FIG. 6 is a block schematic diagram illustrating the write
`enable circuit of the preferred embodiment of the present
`invention.
`FIG. 7 is a schematic diagram illustrating the end-of-cycle
`circuit of the preferred embodiment of the present invention.
`FIG. 8 is a timing diagram illustrating the asynchronous
`mode of operation of the preferred embodiment of the
`present invention.
`FIG. 9 is a timing diagram illustrating the synchronous
`mode of operation of the preferred embodiment of the
`present invention.
`FIG. 10 is a schematic diagram illustrating a circuit for
`generating an ATM signal.
`
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`5,548,560
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`DETAILED DESCRIPTION OF THE
`EMBODIMENTS
`FIG. 1 illustrates, generally, a block diagram of a burst
`mode synchronous static random access memory (SRAM)
`having an asynchronous test mode according to the present
`invention. The synchronous SRAM is designated by the
`general reference character 10, and is shown to include an
`address buffer circuit 12, an address transition detect signal
`(ATD) generating circuit 14, an ATD control circuit 16, a
`write enable circuit 18, and an end of cycle (EOC) circuit 20.
`Also included is a memory array 22 having a plurality of
`SRAM cells arranged in a number of columns and rows,
`each column including a bit line pair 24. In accordance with
`well known principles, each bit line pair 24 has an equal
`ization (or precharge) circuit 26 associated with it. Bit line
`precharge circuits 26 for SRAMs are well known in the art
`and so will not be discussed in detail herein. A sense
`amplifier array 28 is coupled to the bit lines 24 by way of a
`multiplexercircuit 29. The multiplexercircuit 29 provides a
`number of eight-into-one multiplexers to couple groups of
`eight bit line pairs 24 to one sense amplifier in the sense
`amplifier array 28.
`A column decoder 30 is coupled to the array to select a
`column according to a column address. A pair of I/O lines 32
`(shown as I/O and I/O) couples the column decoder 30 to an
`I/O sense amp 34. While FIG. 1 illustrates a single I/O line
`pair 32 coupled to the column decoder, it is understood that
`the present invention includes a memory array 22 divided
`into a number of array cores with a single I/O line pair 32
`being multiplexed between a number of these cores. Such
`decoding schemes are well known in the art and so will not
`be discussed in further detail herein. An I/O equalization
`circuit 36 is provided for equalizing the I/O lines 32. The I/O
`sense amp34 is coupled to an I/O buffer38 by two data lines
`40 (shown as Q and NQ). The data lines 40 are coupled to
`the EOC circuit 20.
`Additional input and logic circuits in the preferred
`embodiment include an external signal buffer circuit 42, an
`address latch enable (ALE) logic circuit 44, and a clock
`generating circuit 46. As set forth in FIG. 1, in the preferred
`embodiment, the external buffer circuit 42 receives an
`external mode signal (ATM), and external burst signal
`(ADV) and an external output enable signal (OE). These
`signals are buffered and provided to various portions of the
`SRAM 10 as internal control signals of the same name; a
`mode signal (ATM), a burst signal (ADV) and an output
`enable signal (OE). Thus, as shown in FIG. 1, the ATM,
`ADV, and OE outputs provided by the external signal buffer
`circuit are the same signals that are input to the ATD
`50
`generating circuit 14, ATD control circuit 16, write enable
`circuit 18, and clock generating circuit 46. The ATM signal
`is provided to place the SRAM 10 in an asynchronous mode
`when high. The ADV signal, if active when clocked, facili
`tates a burst mode of operation. The OE signal, as is well
`known in the art, enables the output during a read operation.
`In the preferred embodiment OE and ATM are asynchro
`nous, while ADV is latched according to an internal clock
`signal (NCLK).
`The clock generating circuit 46 receives the ATM signal
`and an external clock signal (CLK) as inputs and provides
`an inverted internal clock signal (NCLK) and a delayed
`internal clock pulse (CLAT) as internal signals to the SRAM
`10. The nature of the CLK and CLAT signals are determined
`according to the logic state of ATM. If ATM is high,
`indicating asynchronous operation, NCLK and CLAT are
`pulled high. If ATM is low, indicating synchronous opera
`
`30
`
`4
`tion, NCLK is synchronous with CLK, and CLAT is pulse
`of guaranteed width, generated by the rising edge of the
`system clock CLK As best understood with reference to
`FIG. 1, the NCLK output of the clock generating circuit 46
`is provided as an input to the address buffer 12, the write
`enable circuit 18, the I/O buffer 38, the external signal buffer
`circuit 42, and the ALE logic circuit 44. The CLAT output
`is provided as an input to the ATD generating circuit 14 and
`the write enable circuit 18.
`The ALE logic 44 circuit receives external control signals
`latched by NCLK to generate an ALE signal (ALE). The
`ALE signal is used to enable the address buffer 12 as will be
`described herein. While FIG. 1 illustrates an external chip
`enable signal (CE) as one of the external control signals,
`one skilled in the art would recognize that other external
`signals may be used to generate ALE according to the
`operation of the particular SRAM 10.
`Referring once again to FIG. 1 it is shown that the address
`buffer circuit 12 receives an external address (ADD), the
`NCLK signal, and the ALE signal. In response to these
`signals it generates an internal address signal (ADD). Refer
`ring now to FIG. 2, a block schematic diagram is set forth
`illustrating the address buffer 12 of the preferred embodi
`ment of present invention. The external address (ADD)
`consists of a number of address bits (A to A), and the
`address buffer 12 includes a buffer signal path 48 for each
`bit. Each buffer path 48 includes an input buffer 50, a first
`address passgate 52, a first address latch 54, a second
`address passgate 56 and a second address latch 58. The input
`buffer 50 includes two inverters in series. The first passgates
`52 are commonly controlled by the NCLK signal. The
`second passgates are commonly controlled by the ALE
`signal. When the SRAM 10 is in the asynchronous mode
`NCLK is high and passgates 52 are always on. If ALE is
`high in the asynchronous mode, the second passgates 56 are
`enabled, and the first and second latches (54 and 58) buffer
`the address signal. Thus, in asynchronous mode the ADD,
`signal propagates through the address buffer 12 and is
`provided as output ADD. In contrast, if the SRAM is in
`synchronous mode, ADD is latched on the falling edge of
`NCLK, and the ADD signal is allowed to change on the
`rising edge of the ALE signal. Accordingly, the output of the
`address buffer 12 is a clocked signal during synchronous
`operation. As shown in FIG. 1, ADD is provided as an input
`to the ATD generating circuit 14.
`One skilled in the art will recognize that the address signal
`(ADD) is also provided to row and column decoders (not
`shown). Such circuits are well understood in the art and will
`not be discussed in any further detail herein.
`FIG. 3 sets forth a block diagram of the ATD generating
`circuit 14 which is shown to include an asynchronous ATD
`circuit 60, a synchronous ATD circuit 62, and an ATD select
`circuit 64. According to well known principles, the asyn
`chronous ATD circuit 60 receives the address signal ADD
`and generates an asynchronous ATD signal (a-ATD) when
`ever a change in address occurs. In accordance with well
`understood design principles, a-ATD is a signal of prede
`termined, limited duration. ATD signal generating circuits
`for asynchronous SRAMs are known in the art and so will
`not be discussed in detail herein. It is understood that an
`a-ATD signal could also be generated from additional exter
`nal signals. As just one example, a chip enable signal or a
`combination of chip enable signals could be used to generate
`a-ATD.
`The synchronous ATD circuit 62 generates a synchronous
`ATD signal (s-ATD). It is understood that while the syn
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`chronous timing signal is called "s-ATD' herein, it is not
`generated by a change in address. The first edge of s-ATD (in
`the preferred embodiment a falling edge) is generated from
`a delay clock pulse CLAT edge and logic determined from
`the ALE, ADV and WES inputs. The second (rising) edge of
`s-ATD is created by a pull-up circuit activated by an
`end-of-cycle signal (EOC). The generation of both EOC and
`WES will be discussed at a later point herein. As shown in
`the figure, s-ATD and a-ATD are provided to the ATD select
`circuit 64. The ATD select circuit 64, receives the ATM
`signal, and if it is high (indicating asynchronous operation)
`it will output the a-ATD signal. If ATM is low, the ATD
`select circuit 64 provides the s-ATD signal as an output.
`Referring now to FIG. 4, preferred embodiments of the
`synchronous ATD circuit 62 and ATD select circuit 64 are
`illustrated. The synchronous ATD circuit 62 includes four
`NAND gates (G1-G4), inverter I1, p-channel MOS transis
`tor P1 and n-channel MOS transistors N1 and N2. P1 has its
`source coupled to the ATD select circuit 64 and its drain
`coupled to the drain of N1. N1 has its source coupled to the
`20
`drain of N2 and the source of N2 is coupled to ground. EOC
`is inverted by I1 and applied to the gates of P1 and N2. The
`outputs of G1-G3 are provided as inputs to G4, and the
`output of G4 drives the gate of N1. G1-G3 each have two
`inputs, one of which is CLAT. The other inputs to G1-G3 are
`ALE, ADV and WES, respectively.
`The generation of s-ATD begins with EOC low. With
`EOC low, P1 is turned off and N2 is turned on. Provided any
`of the signals ALE, ADV or WES are high, on the rising
`edge of CLAT, N1 will turn on, pulling the drains of N1 and
`P1 (node ND1) low by way of N2. This generates the falling
`edge of s-ATD. Provided the source of P1 is coupled to a
`high logic state, when EOC falls, N2 is turned off and P1 is
`turned on, pulling ND1 high. This is the subsequent rising
`edge of the s-ATD signal.
`35
`Referring once again to FIG. 4, it is shown that the ATD
`select circuit 64 includes two NAND gates (G5 and G6), a
`latch L1 and disable transistors P2 and N3. G5 is a two input
`gate that receives the ATD signal as a first input and the ATM
`signal at a second input. G6 is a two input gate that receives
`40
`the output of G5 and the output of L1 as inputs. As set forth
`in the figure, L1 receives s-ATD as an input. P2 has its drain
`coupled to the source of P1, and its source coupled to the
`positive supply voltage. N3 has its drain coupled to the input
`of L1 and its source coupled to ground. The gates of P2 and
`N3 are coupled to ATM. When ATM is high (asynchronous
`mode) P2 is turned off, disabling the pull-up abilities of the
`s-ATD circuit and N3 is turned on, pulling the input of L1
`low. In this manners-ATD is disabled. With the ATM input
`to G5 and the output of L1 both high, the output of G6
`50
`follows a-ATD. When ATM is low (synchronous mode) the
`output of G5 will always be high, disabling the a-ATD
`signal. The ATMsignal also turns off N3 and P2 is turned on,
`enabling P1. With P1 on and N3 off, the s-ATD signal
`generated by the s-ATD circuit 62 propagates through L1
`and is provided at the output of G6.
`Referring now to FIG. 5, a block schematic diagram is set
`forth illustrating the ATD control circuit 16 of the preferred
`embodiment. The control circuit input 66 receives an ATD
`signal (eithera-ATD or the s-ATD) from the ATD generating
`circuit 14. As shown in the figure, in response to the ATD
`signal and the write enable pulse (WEP), the ATD control
`circuit 16 provides a number of I/O control signals. In the
`preferred embodiment the I/O control signals are a bit line
`equalization signal (BEQ), a sense amplifier enable signal
`(SAEN), an I/O line equalization signal (I/OEQ), and an I/O
`sense amplifier enable signal (I/OSAEN). BEQ is generated
`
`6
`directly from the ATD signal. A falling ATD signal results in
`a falling BEQ signal, and a rising ATD signal results in a
`rising BEQ signal.
`The I/O control signals SAEN, I/OEQ and I/OSAEN are
`generated in a similar fashion to BEQ, but are further
`controlled by the WEP signal. The generation of WEP will
`be discussed at a later point herein. Referring once again to
`FIG. 5, it is shown that the ATD control circuit 16 also
`includes three, two input NAND gates G7, G8 and G9. The
`outputs of the NAND gates generate the SAEN, I/OEQ and
`I/OSAEN signals respectively, by way of inverters I2, I3 and
`I4. WEP is provided as an input to each NAND gate by way
`of an inverter I5. In the event WEP is high, a low input is
`received at each of the NAND gates (G7-G9) and the
`NAND gate outputs are driven high, regardless of the other
`inputs. The high NAND gate outputs are inverted by invert
`ers I2-14, and SAEN, I/OEQ and I/OSAEN are driven low.
`In this manner, a write operation (indicated by WEP being
`high) places SAEN, I/OEQ and I/OSAEN in a low (disable)
`mode.
`In the case where WEP is low, SAEN, I/OEQ and I/OS
`AEN change state according to the ATD signal (s-ATD or
`a-ATD). SAEN is generated by way of two input NOR gate
`G10, NAND gate G7 and inverter 12. ATD is applied to both
`inputs of G10, one of which includes a delay circuit 68. As
`a result, a falling edge of BEQ will generate a delayed, rising
`edge of SAEN. Conversely, a rising BEQ edge generates a
`falling SAEN edge, without additional delay. To generate
`I/OEQ, SAEN (inverted) is provided as one input to G8. As
`described previously, the output of G8 is applied to inverter
`I3 to generate I/OEQ. Accordingly, I/OEQ is the inverse of
`SAEN. To generate I/OSAEN, SAEN (inverted) is also
`provided as an input to G9 by way of the two input NOR
`gate G11 having a delay circuit 68 at one input. In a similar
`fashion to G10, a falling SAEN (inverted) signal will
`generate a delayed rising output at G11. This output results
`in a delayed rising I/OSAEN with respect to a rising SAEN.
`A falling SAEN will result in a falling G11 output, without
`additional delay. It is understood that the delay circuits 68
`set forth in FIG. 5 do not necessarily have the same delay
`values.
`Referring once again to FIG. 1, the arrangement of the
`various I/O control signals is illustrated. The BEQ signal is
`commonly coupled to the bit line equalization circuits 26. As
`BEQ goes high, the bit lines are equalized. SAEN drives the
`sense amplifier array 28, to couple a sense amplifier to a
`selected bit line pair 24. As SAEN goes high, the sense
`amplifiers will be enabled and will sense the differential
`voltage on the selected bit lines. The I/OEQ signal is coupled
`to the I/O equalization circuit 36, and when high, the I/O
`lines 32 are equalized. Like the sense amplifier array 28, the
`I/O sense amplifier 34 is alternately enabled or disabled
`according to a high or low I/OSAEN signal. The I/OSAEN
`signal is also applied to the end-of-cycle circuit 20. As will
`be recalled from the previous discussion, when WEP is high,
`SAEN, I/OEQ and I/OSAEN are all driven low. Thus,
`during a write operation (WEP high) the sense amplifiers,
`I/O equalization circuit, and I/O sense amplifier are all
`disabled.
`Referring once again to FIG. 1, it is shown that the write
`enable circuit 18 receives an external write enable signal
`WE, and in response to the NCLK, CLAT and ATM signals,
`generates either a synchronous write enable signal (s-WES)
`and write enable pulse (s-WEP), or an asynchronous write
`enable signal (a-WES) and write enable pulse (a-WEP). The
`write enable circuit 18 of the preferred embodiment is
`shown in FIG. 6. The external write enable signal WE is
`
`30
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`45
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`55
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`65
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`STMicroelectronics, Inc., Ex. 1010
`IPR2021-01593
`Page 10
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`5,548,560
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`10
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`15
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`20
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`25
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`7
`received by a write enable buffer 70. It is understood that
`WE, is a number of external signals controlling when a
`memory write may be executed. The write enable logic
`section 72, receives the buffered control signals and gener
`ates aWE signal if a write operation is to take place. The WE
`signal passes through inverter 16 and is clocked by NCLK
`at a first WE passgate 74 into a latch L2. The output of L2
`is clocked by CLAT at a second WE passgate 76 into latch
`L3. The output of L3 is applied to inverter I7 to generate the
`WES signal. Similar to the address buffer 12, in the syn
`chronous mode, the resulting WES signal (s-WES) is a
`clocked signal because NCLK and CLAT are synchronous
`with the external clock. In asynchronous mode, the resulting
`WES signal (a-WES) follows directly from WE, as both
`NCLK and CLAT are pulled high.
`Referring again to FIG. 6 it is shown that the write enable
`circuit 18 also includes a write enable control circuit 78
`which provides either an a-WEP signal or ans-WEP signal
`depending upon to the logic state of ATM. The WES signal
`(either s-WES or a-WES) is applied to both a write enable
`passgate 80 and inverter 8.
`If ATM is low (synchronous operation), passgate 80 is off
`and s-WES (a clocked signal) is not able to pass through.
`The signal s-WES is applied through inverters I9 and I10 to
`NAND gate G12 by way of a direct input, and a delayed,
`inverted input. The delayed, inverted input is created by a
`first WE delay circuit 82 and inverter I10. With ATM low,
`NAND gate G12 is enabled. Accordingly, on a rising WES
`edge, a delayed, low pulse is generated by G12. The low
`pulse turns on pull-up transistor P3 and the input of latch LA
`30
`is pulled high. The output of L4 passes through a second WE
`delay circuit 84 to NOR gate G13, by way of a direct input
`and a delayed, inverted input 86. With ATM low, the input
`to G13 generates a delayed, high pulse. The delayed high
`pulse turns on pull-down transistor N4, and the input to LA
`is pulled down. The output of LA is applied to inverter I11
`to generate WEP. In this manner, in synchronous mode,
`s-WEP is a pulse that is generated by arising edge of s-WES.
`If ATM is high, the ATM signal is applied to G13 and
`inverted ATM is applied to G12. This forces the output of
`G12 high and the output of G13 low, regardless of the logic
`of the other inputs to the gates. In this manner P3 and N4 are
`turned off, disabling the pulse generating circuit which
`generates s-WEP. At the same time, passgate 80 is enabled
`and a-WES is applied through LA and I11 to generate
`a-WEP. Accordingly, in the asynchronous mode of opera
`tion, the a-WEP output follows the a-WES signal.
`As mentioned previously, in synchronous operation the
`EOC signal is generated by the end-of-cycle circuit 20. The
`end-of-cycle circuit 20 of the preferred embodiment is set
`forth in FIG. 7, and includes a two input XOR gate 88, a
`precharge low circuit 90, an inverter 112, and a pulse
`generating circuit 91. The two inputs of XOR gate 88 are
`data lines 38 Q and NQ. The output of the XOR gate 88 is
`provided as an input to the pulse generating circuit 91. The
`precharge low circuit 90 is connected to the data lines 38 and
`is activated by the I/OSAEN signal by way of inverter I12.
`Thus, provided I/OSAEN is in a high state, any change of
`state across Q and NQ will cause the output of XOR gate 88
`to go high. In response to the high output, the pulse
`60
`generator 91 outputs a high going pulse, which is the EOC
`signal. The output of XOR gate 88 goes low when the falling
`edge of the I/OSAEN signal disables the I/O sense amplifier
`(not shown in FIG. 7) and precharges Q and NQ to a low
`State.
`Referring now to FIG. 8, a timing diagram illustrating the
`typical asynchronous test mode of the preferred embodiment
`
`50
`
`8
`is set forth. The timing diagram is best understood in
`conjunction with FIGS. 1 and 5. As mentioned previously, to
`place the SRAM 10 in the asynchronous test mode ATM is
`brought high. The ATD generating circuit 14 detects a
`change in address and generates a rising edge of the a-ATD
`signal. The a-ATD signal has a preset duration determined
`by the a-ATD generating circuit 60. The a-ATD signal is
`applied to the ATD control circuit 16 where it drives signal
`BEQ high, equalizing bit lines 24. SAEN is driven low by
`the rising edge of BEQ, disabling the sense amplifiers 28.
`I/OEQ is driven high by the falling edge of SAEN and
`equalizes the I/O lines 32. I/OSAEN is driven low by the
`falling edge of SAEN and disables the I/O sense amplifier
`34. This series of timing signals places the SRAM 10 in a
`precharge/equalization state which precharges all the data
`I/O lines in preparation for either a read or a write operation.
`After the predetermined duration of the a-ATD signal,
`a-ATD returns low. The falling edge of a-ATD drives BEQ
`low. Following a delay (d1) BEQ forces SAEN high,
`enabling the sense amplifier array 28. The rising edge of
`SAEN drives I/OEQ low which disables the I/O equalization
`circuit 36. A high going SAEN drives I/OSAEN high
`following a delay (d2), enabling the I/O sense amplifier 34.
`This series of timing signals places the SRAM 10 in an
`access state in which the memory array 22 may be written
`to or read from. During a read operation, the sensing circuits
`(sense amplifiers 28 and I/O sense amplifiers 34) are
`enabled, while the equalization circuits are disabled. Such a
`read operation is reflected by the timing signals of FIG.8. As
`will be recalled, during a write operation WEP is high
`forcing SAEN, I/OEQ and I/OSAEN low. As a result, the
`sense amplifiers 28, the I/O equalization circuit 36, and the
`I/O sense amplifier 34 are all disabled.
`FIG. 9 is a timing diagram illustrating the synchronous
`mode of operation. Unlike the asynchronous mode of opera
`tion, which generates a rising a-ATD signal upon a change
`in address, in the synchronous mode the s-ATD signal is
`driven low on the rising clock edge of CLAT. The generation
`of signals BEQ, SAEN, I/OEQ, and I/OSAEN occurs in the
`same manner as in the falling edge of the a-ATD signal in the
`asynchronous mode of operation described above. In con
`trast to the a-ATD signal, the s-ATD signal is not of a
`predetermined duration. Following the falling edge of
`a