UNITED STATES PATENT AND TRADEMARK OFFICE
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`Hewlett Packard Enterprise Co.,
`Petitioner,
`v.
`Intellectual Ventures II LLC,
`Patent Owner.
`
`Patent No. 7,464,240 to Caulkins et al.
`Issued: December 9, 2008
`Filed: May 23, 2006
`Title: Hybrid Solid State Disk Drive With Controller
`IPR Case No.: IPR2022-00115
`
`DECLARATION OF VIVEK SUBRAMANIAN, PH.D.
`
`1
`
`HPE, Exh. 1003, p. 1
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`
`III.
`
`IV.
`V.
`
`TABLE OF CONTENTS
`TABLE OF EXHIBITS ............................................................................................. 4
`I.
`INTRODUCTION ........................................................................................... 6
`II.
`QUALIFICATIONS ........................................................................................ 7
`A.
`Educational Background ....................................................................... 8
`B.
`Professional Experience ........................................................................ 8
`C.
`Prior Expert Testimony .......................................................................10
`D.
`Patents and Publications ......................................................................11
`E.
`Other Relevant Qualifications .............................................................11
`LEGAL STANDARDS .................................................................................12
`A.
`Anticipation .........................................................................................13
`B.
`Obviousness .........................................................................................13
`LEVEL OF ORDINARY SKILL IN THE ART ...........................................17
`KNOWLEDGE OF A POSITA .....................................................................19
`A.
`Data Storage Devices ..........................................................................19
`B.
`Caching ................................................................................................23
`C.
`Destaging in Write Back Caches .........................................................25
`VI. OVERVIEW OF THE ’240 PATENT ..........................................................28
`A.
`Priority Date ........................................................................................28
`B.
`The ’240 Patent Specification .............................................................28
`1.
`Disclosed Solid State Device ................................................... 28
`2.
`Read and Write Operations ...................................................... 30
`3.
`Destaging Operation ................................................................ 32
`The Challenged Claims .......................................................................34
`1.
`Claim 1 ..................................................................................... 35
`2.
`Claim 3 ..................................................................................... 36
`3.
`Claim 7 ..................................................................................... 36
`4.
`Claim 8 ..................................................................................... 36
`
`C.
`
`2
`
`HPE, Exh. 1003, p. 2
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`D.
`The ’240 Patent Prosecution History ..................................................36
`VII. CLAIM CONSTRUCTION ..........................................................................38
`VIII. OVERVIEW OF PRIOR ART ......................................................................39
`A.
`Harari (Ex. 1004) .................................................................................39
`B.
`Tobita (Ex. 1005) ................................................................................42
`C.
`Hu (Ex. 1006) ......................................................................................46
`IX. ANALYSIS ....................................................................................................48
`A.
`GROUNDS 1 AND 2: Harari anticipates Claims 1, 3, and 7 and/or
`renders Claims 1, 3, and 7 obvious in view of the knowledge of a
`POSITA ...............................................................................................48
`1.
`Challenged Claims: .................................................................. 49
`GROUND 3: Harari in view of Hu and the knowledge of a POSITA
`render obvious the Challenged Claims ...............................................66
`1.
`Scope and Content of the Prior Art and Motivation to
`Combine ................................................................................... 66
`Challenged Claims: .................................................................. 70
`2.
`GROUNDS 4 & 5: Tobita anticipates Claims 1, 3, and 7 and/or
`renders Claims 1, 3, and 7 obvious in view of the knowledge of a
`POSITA ...............................................................................................74
`1.
`Challenged Claims: .................................................................. 75
`GROUND 6: Tobita in view of Hu and the knowledge of a POSITA
`renders obvious the Challenged Claim ...............................................93
`1.
`Scope and Content of the Prior Art and Motivation to
`Combine ................................................................................... 94
`Challenged Claims: .................................................................. 97
`2.
`CONCLUSION ............................................................................................102
`X.
`XI. DECLARATION IN LIEU OF OATH .......................................................102
`
`D.
`
`B.
`
`C.
`
`3
`
`HPE, Exh. 1003, p. 3
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`
`TABLE OF EXHIBITS
`
`Exhibit
`1001
`
`Description
`U.S. Patent No. 7,464,240 (“the ’240 Patent”)
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`Certified File History of the ’240 Patent
`
`Declaration of Vivek Subramanian, Ph.D.
`
`U.S. Patent No. 6,523,132 to Harari et al. (“Harari”)
`
`U.S. Patent No. 5,862,083 to Tobita et al. (“Tobita”)
`
`Hu, Yiming, Tycho Nightingale, and Qing Yang. “RAPID-
`Cache—A Reliable and Inexpensive Write Cache for High
`Performance Storage Systems.” IEEE Transactions on Parallel
`and Distributed Systems, vol. 13, no. 3 (March 2002): 290-307.
`(“Hu”)
`
`U.S. Patent No. 7,574,556 to Gill et al.
`
`U.S. Patent No. 7,464,221 to Nakamura et al.
`
`U.S. Patent No. 7,058,850 to Cochran
`
`Menon, Jai, and Jim Cortney. “The Architecture of a Fault-Tolerant
`Cached RAID Controller.” In Proceedings of the 20th Annual
`International Symposium on Computer Architecture (pp. 76-87).
`Los Alamitos, CA: Computer Society Press, 1993.
`
`Nam, Young Jin, and Chanik Park. “An Adaptive High-Low Water
`Mark Destage Algorithm for Cached RAID5.” In Proceedings of
`the 2002 Pacific Rim International Symposium on Dependable
`Computing (pp. 177-184). PRDC ’02. Los Alamitos, CA: IEEE
`Computer Society Press, 2002.
`
`Varma, Anujan, and Quinn Jacobson. “Destage Algorithms for
`Disk Arrays with Non-Volatile Caches.” In Proceedings of the
`22nd Annual International Symposium on Computer Architecture
`
`4
`
`HPE, Exh. 1003, p. 4
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`Exhibit
`Description
`(pp. 83-95). New York: Association for Computing Machinery,
`1995.
`
`1013
`
`1014
`
`Declaration of Sylvia Hall-Ellis, Ph.D.
`
`October 28, 2021 letter to Patent Owner’s counsel stipulating to
`non-use of IPR grounds prior art in the WDTX Proceeding
`
`5
`
`HPE, Exh. 1003, p. 5
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`I, Vivek Subramanian, Ph.D., declare as follows:
`
`I.
`
`INTRODUCTION
`1.
`I am over the age of 21 and am competent to make this declaration.
`
`2.
`
`I have been retained on behalf of Hewlett Packard Enterprise Co.
`
`(“HPE”) to provide my opinions regarding the validity of claims 1, 3, 7, and 8 of
`
`U.S. Patent No. 7,464,240 (“’240 Patent”). I submit this declaration based on my
`
`personal knowledge and in support of HPE’s inter partes review petition against the
`
`’240 Patent (the “Petition”).
`
`3.
`
`I have been asked to review and provide my independent analysis of
`
`the ’240 Patent in light of the materials cited below and my knowledge and
`
`experience in this field during the relevant period. I have been asked to consider
`
`whether the references cited in the Petition anticipate and/or render obvious the
`
`invention described by claims 1, 3, 7, and 8 of the ’240 Patent.
`
`4.
`
`I am being compensated according to my normal hourly rate for my
`
`time providing my independent analysis in this aforementioned IPR proceeding, but
`
`my compensation is not contingent in any way on the content of my analysis or the
`
`outcome of this proceeding. I am not, and never was, an employee or agent of HPE.
`
`5.
`
`My findings, as explained below, are based on my study, experience,
`
`and background discussed below, informed by my extensive experience in the field
`
`6
`
`HPE, Exh. 1003, p. 6
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`of memory devices, including semiconductor memory. My findings are also based
`
`on my education as an electrical engineer, in addition to the subsequent decades of
`
`work in research and development in these fields. As described in more detail below,
`
`based on my experiences, I understand and know of the capabilities of persons of
`
`ordinary skill in the field of memory devices, including semiconductor memory, in
`
`2006, when the application to which the ’240 Patent claims priority was filed.
`
`Indeed, I have extensive relevant personal knowledge and experience, in addition to
`
`working directly with many such persons in these fields during that time frame. I
`
`have also relied on my review and analysis of the prior art cited in the Petition and
`
`the other materials cited herein, including those itemized in the “Table of Exhibits”
`
`list preceding this declaration.
`
`II. QUALIFICATIONS
`6.
`Attached as Appendix A is my curriculum vitae, which includes a more
`
`detailed statement of my professional qualifications,
`
`including education,
`
`publications, honors and awards, professional activities, consulting engagements,
`
`and other relevant experience. While I incorporate Appendix A by reference, below
`
`is a brief summary of my background, including my background and experience
`
`relevant to this case.
`
`7
`
`HPE, Exh. 1003, p. 7
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`A.
`Educational Background
`7.
`I earned a B.S. degree in Electrical Engineering from Louisiana State
`
`University in 1994. For the last two years of my B.S. work, I worked on
`
`characterization of advanced, highly scaled MOSFETs as part of my senior honors
`
`thesis in a collaborative project with IBM. I received M.S. and Ph.D. degrees in
`
`Electrical Engineering from Stanford University in 1996 and 1998, respectively.
`
`While at Stanford, I was a co-instructor in the Electrical Engineering Department
`
`where I taught, among other courses, a class on Advanced Integrated Circuit
`
`Fabrication Processes. I also acted as the Head Teaching Assistant within Stanford’s
`
`Integrated Circuit Fabrication Laboratory. Throughout the course of my M.S. and
`
`Ph.D. work, I performed research on advanced transistor and memory technologies,
`
`including process development, circuit design, device
`
`integration, and
`
`characterization and modeling.
`
`B.
`8.
`
`Professional Experience
`In 1997, I interned at the Advanced Products Research and
`
`Development Laboratory at Motorola, in Austin, Texas, where I developed advanced
`
`transistor technologies for high-performance microprocessors, with a particular
`
`focus on strained silicon MOSFETs, including development and characterization of
`
`memory test circuits based on the same.
`
`8
`
`HPE, Exh. 1003, p. 8
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`9.
`Following graduation, I co-founded Matrix Semiconductor, where I
`
`was also a member of the technical staff until 2000. While at Matrix Semiconductor,
`
`I was responsible for research, design, and development of three-dimensional (3-D)
`
`integrated circuits, including a non-volatile 3-D memory chip as well as advanced
`
`transistor technology for driving the same. In this role, I was involved in several
`
`aspects of technology development, including defining the process technology,
`
`developing various aspects of the chip design and architecture, and establishing
`
`product strategy. Matrix Semiconductor was nominated to the Scientific American
`
`SA50 list for visionary technology, in recognition of the innovations it developed.
`
`10.
`
`From 1998 to 2000, while working at Matrix, I served as a Consulting
`
`Assistant Professor at Stanford University in the Department of Electrical
`
`Engineering. During this period, I was also a Visiting Research Engineer in the
`
`Electronics Research Laboratory at the University of California, Berkeley. In these
`
`roles, I worked on the development of high-performance transistors for advanced
`
`microprocessor applications and developed various classes of memory devices.
`
`11.
`
`Since 2000, I have been a faculty member in the Department of
`
`Electrical Engineering and Computer Sciences at the University of California,
`
`Berkeley. Between 2000 and 2005, I was an assistant professor. From 2005 until
`
`2011, I was a tenured associate professor. Between 2011 and 2020, I was a full
`
`9
`
`HPE, Exh. 1003, p. 9
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`professor. Over the past twenty years, I have taught numerous courses relating to
`
`semiconductor manufacturing and circuit design, including both undergraduate and
`
`graduate courses on digital electronics, analog circuit design, semiconductor devices
`
`and technology, and semiconductor manufacturing technology. I had primary
`
`responsibility for the main graduate course focused on advanced transistors and on
`
`semiconductor memories. As of July of 2020, I have transitioned to an adjunct
`
`professor role as I complete my move to EPFL, as discussed below.
`
`12.
`
`Since 2018, I have been a Professor of Microengineering at École
`
`polytechnique fédérale de Lausanne (EPFL) in Switzerland. I lead an initiative
`
`focused on the development of advanced manufacturing technologies for future
`
`electronic and electromechanical systems. Currently, I maintain a dual affiliation
`
`with both Berkeley and EPFL as I migrate my research activities over to EPFL and
`
`graduate my remaining Ph.D. students at Berkeley.
`
`C.
`13.
`
`Prior Expert Testimony
`I have previously submitted declarations or otherwise worked on
`
`several IPRs / sets of IPRs, as summarized in Appendix A. Additionally, I have
`
`testified as an expert witness in Federal Court and the ITC, as summarized in
`
`Appendix A.
`
`10
`
`HPE, Exh. 1003, p. 10
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`D.
`Patents and Publications
`14.
`I have published more than 200 technical papers in international
`
`journals and conferences covering various aspects of semiconductor devices,
`
`materials, circuit design, process technology, and memory architecture. In addition,
`
`I have authored numerous papers relating to various aspects of semiconductor
`
`technology. I am also a named inventor on more than 60 patents, the majority of
`
`which are directed towards various aspects of semiconductor memory technology.
`
`15. My Curriculum Vitae, including my publications and patents, is
`
`submitted herewith as Appendix A.
`
`E.
`16.
`
`Other Relevant Qualifications
`In addition to my roles in academia, I am also the founder and chief
`
`technology officer of Locix
`
`Inc. Locix
`
`is a venture-funded company
`
`commercializing advanced IoT solutions for commercial applications such as
`
`factories and warehouses. Locix has successfully developed several products for
`
`these markets, including security cameras, asset tracking systems, and cloud-based
`
`solutions. I led all technical aspects of this development, including the development
`
`of a custom system-on-chip for wireless communication and an ultra-low-power
`
`wireless sensor platform including sensing, computation, memory functionality, and
`
`communication.
`
`11
`
`HPE, Exh. 1003, p. 11
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`17. My current research interests include various aspects of semiconductor
`
`technology, including advanced CMOS devices and technology, large area
`
`electronics, material science, process technology, and memory technology. Included
`
`in this work is my group’s research and investigation into advanced high-
`
`performance transistors and memory technologies.
`
`18.
`
`I am a member of and have been actively involved with a number of
`
`industry organizations, including the Institute of Electrical and Electronics
`
`Engineers (“IEEE”). For example, I have served on the technical committee for the
`
`Device Research Conference and the International Electron Device Meeting. In
`
`2002, I was nominated to Technology Review’s list of top 100 young innovators. In
`
`2003, I was nominated to the National Academy of Engineering’s “Frontiers of
`
`Engineering,” and I was awarded a National Science Foundation Young Investigator
`
`Award (CAREER).
`
`III. LEGAL STANDARDS
`19.
`I understand that the prior art references cited herein qualify as prior art
`
`to the ’240 Patent under U.S. law. In formulating my opinions, I have applied certain
`
`legal standards.
`
`20.
`
`I am not a lawyer. I do not expect to offer any testimony regarding what
`
`the law is. Instead, the following sections summarize the law as I understand it in
`
`12
`
`HPE, Exh. 1003, p. 12
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`formulating and rendering my opinions found in this declaration. I understand that,
`
`in an inter partes review proceeding, patent claims may be deemed unpatentable if
`
`it is shown that they were anticipated by a single patent or printed publication or
`
`rendered obvious by one or more prior art patents or printed publications. I
`
`understand that questions of claim clarity (definiteness) and enablement cannot be
`
`considered as a ground for considering the patentability of a claim in these
`
`proceedings.
`
`A.
`21.
`
`Anticipation
`I understand that a patent claim may be invalid as “anticipated” if each
`
`and every feature of the claim is found, expressly or inherently, in a single item of
`
`prior art, such as in a single prior art patent or printed publication. In determining
`
`whether the single item of prior art anticipates the claim, one considers not only what
`
`is expressly/implicitly disclosed in the particular item of prior art, but also what is
`
`inherently present or disclosed in that prior art or what inherently results from its
`
`practice.
`
`B.
`22.
`
`Obviousness
`I understand that a claim may be invalid if the subject matter described
`
`by the claim as a whole would have been obvious to a POSITA in view of a prior art
`
`reference, or in view of a combination of references at the time the claimed invention
`
`13
`
`HPE, Exh. 1003, p. 13
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`was made. Therefore, I understand that obviousness is determined from the
`
`perspective of a POSITA, and that the asserted claims of the patent should be read
`
`from the point of view of such a person at the time the claimed invention was made.
`
`I further understand that a POSITA is assumed to know and to have all relevant prior
`
`art in the field of endeavor covered by the patent in suit and all analogous prior art.
`
`I understand that obviousness in an inter partes review proceeding is evaluated using
`
`a preponderance of the evidence standard, which means that the claims must be more
`
`likely obvious than nonobvious.
`
`23.
`
`I also understand that an analysis of whether a claimed invention would
`
`have been obvious should be considered in light of the scope and content of the prior
`
`art, the differences (if any) between the prior art and the claimed invention, and the
`
`level of ordinary skill in the pertinent art involved. I understand as well that a prior
`
`art reference should be viewed as a whole. I understand that in considering whether
`
`an invention for a claimed combination would have been obvious, I may assess
`
`whether there are apparent reasons to combine known elements in the prior art in the
`
`manner claimed in view of interrelated teachings of multiple prior art references, the
`
`effects of demands known to the design community or present in the marketplace,
`
`and/or the background knowledge possessed by a POSITA. I also understand that
`
`14
`
`HPE, Exh. 1003, p. 14
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`other principles may be relied on in evaluating whether a claimed invention would
`
`have been obvious, and that these principles include the following:
`
` A combination of familiar elements according to known methods is likely to
`
`be obvious when it does no more than yield predictable results;
`
` When a device or technology is available in one field of endeavor, design
`
`incentives and other market forces can prompt variations of it, either in the
`
`same field or in a different one, so that if a POSITA can implement a
`
`predictable variation, the variation is likely obvious;
`
` If a technique has been used to improve one device, and a POSITA would
`
`have recognized that it would improve similar devices in the same way, using
`
`the technique is obvious unless its actual application is beyond his or her skill;
`
` An explicit or implicit teaching, suggestion, or motivation to combine two
`
`prior art references to form the claimed combination may demonstrate
`
`obviousness, but proof of obviousness does not depend on or require showing
`
`a teaching, suggestion, or motivation to combine;
`
` Market demand, rather than scientific literature, can drive design trends and
`
`may show obviousness;
`
`15
`
`HPE, Exh. 1003, p. 15
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`
` One of the ways in which a patent’s subject can be proved obvious is by noting
`
`that there existed at the time of invention a known problem for which there
`
`was an obvious solution encompassed by the patent’s claims;
`
` Any need or problem known in the field of endeavor at the time of invention
`
`and addressed by the patent can provide a reason for combining the elements
`
`in the manner claimed;
`
` “Common sense” teaches that familiar items may have obvious uses beyond
`
`their primary purposes, and in many cases a POSITA will be able to fit the
`
`teachings of multiple patents together like pieces of a puzzle;
`
` A POSITA is also a person of ordinary creativity, not an automaton;
`
` A patent claim can be proved obvious by showing that the claimed
`
`combination of elements was “obvious to try,” particularly when there is a
`
`design need or market pressure to solve a problem and there are a finite
`
`number of identified, predictable solutions such that a POSITA would have
`
`had good reason to pursue the known options within his or her technical grasp;
`
`and
`
` One should be cautious of using hindsight in evaluating whether a claimed
`
`invention would have been obvious.
`
`16
`
`HPE, Exh. 1003, p. 16
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`IV. LEVEL OF ORDINARY SKILL IN THE ART
`24.
`I understand that my assessment of the claims of the ’240 Patent and
`
`the teachings of the prior art and my analysis and opinions herein must be undertaken
`
`from the perspective of what would have been known or understood by a person
`
`having ordinary skill in the art, reading the ’240 Patent on its priority date and in
`
`light of the specification and file history of the ’240 Patent. I will refer to such a
`
`person as a “POSITA.”
`
`25.
`
`I further understand that in determining the level of ordinary skill in the
`
`art, I am to consider factors including:
`
`(a) the type of problems encountered in the art or field of invention,
`(b)prior art solutions to those problems,
`(c) the rapidity with which innovations are made,
`(d)sophistication of the technology, and
`(e) the educational level of active workers in the field.
`26.
`I understand that a person of ordinary skill in the art is not a specific
`
`real individual, but rather a hypothetical individual having the qualities reflected by
`
`the factors above. This hypothetical person has knowledge of all prior art in the
`
`relevant field and takes from each reference what it would teach to a person having
`
`the skills of a POSITA.
`
`17
`
`HPE, Exh. 1003, p. 17
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`27.
`I understand that a POSITA is a person of ordinary creativity, but not
`
`an automaton, and that a POSITA can often fit multiple patents or prior art references
`
`together like pieces of a puzzle as a result of this ordinary creativity. I also
`
`understand that I may consider the inferences and creative steps that a POSITA
`
`would employ. In addition, I understand that a POSITA would necessarily have been
`
`capable of understanding the scientific and engineering principles applicable to the
`
`pertinent art.
`
`28. Based on my review and analysis of the ’240 Patent, the prior art cited
`
`herein, and the ordinary skill factors described in this section, a POSITA in the field
`
`of the ’240 Patent at the time of the earliest possible priority date (May 23, 2006)
`
`would have had at least a bachelor’s degree in electrical engineering or an
`
`equivalent, plus three years of experience in the field of memory device design.
`
`Additional education in the field of electrical engineering such as a masters or
`
`doctorate degree may serve as a substitute for experience in the field. A person with
`
`less education but more relevant practical experience may also meet this standard.
`
`The prior art also evidences the level of skill in the art.
`
`29. As of May 23, 2006, i.e., the earliest possible priority date of the ’240
`
`Patent, I had more than ordinary skill in the art. I am, however, familiar with the
`
`skills and knowledge possessed by those I would have considered a POSITA as of
`
`18
`
`HPE, Exh. 1003, p. 18
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`that date. When I refer to the understanding of a POSITA, I am referring to the
`
`understanding of such a person as of May 23, 2006.
`
`V.
`
`KNOWLEDGE OF A POSITA
`A.
`Data Storage Devices
`30. Data storage devices are critical components of computer systems that
`
`provide high-capacity, long-term, non-volatile memory for storing persistent
`
`information. Non-volatile memory here refers to memory that retains data even when
`
`there is no power to the device. Non-volatile memory includes mechanically
`
`addressed media, such as magnetic tape and hard disks, as well as semiconductor
`
`memories, such as Flash memory.
`
`31. A standard disk drive is shown below. (See Ex. 1009 at FIG. 3.) “The
`
`disk drive 301 receives input/output (‘I/O’) requests from remote computers” (hosts)
`
`via a “communications medium 302 such as a computer bus [or] fibre channel.” (Ex.
`
`1009 at 1:64-2:1.)
`
`19
`
`HPE, Exh. 1003, p. 19
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`
`32. A host retrieves or stores data from the data storage device through
`
`“read” and “write” requests. A “read” request means that the data storage device
`
`returns some requested amount of electronic data stored within that data storage
`
`device to the computer that requests it. A “write” request means that the data storage
`
`device stores electronic data furnished by the computer within that data storage
`
`device. (Ex. 1009 at 2:4-9.) As shown, the standard disk drive includes a “controller”
`
`that handles “[c]ommunication between remote computers and the disk drive,
`
`translation of I/O requests into internal I/O commands,” and other management and
`
`control. (Ex. 1009 at 2:28-34.)
`
`33.
`
`To increase storage capacity and the capacity for parallel I/O requests,
`
`individual disk drives can also be combined into a “disk array device,” as shown
`
`below. (Ex. 1009 at FIG. 4.)
`
`20
`
`HPE, Exh. 1003, p. 20
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`
`34.
`
`Such disk arrays have been known for decades, and typically include
`
`multiple disk drive devices, a cache memory, and a controller for controlling both.
`
`(Ex. 1009 at 2:63-64.) Electronic data within a disk array is stored at “specific
`
`addressable locations.” (Ex. 1009 at 3:10-11.) But, because a disk array can include
`
`numerous disk drives, the address space can be “immense.” As a result, it is normally
`
`partitioned into logical units (“LUNs”) representing a “defined amount of electronic
`
`data storage space” mapped to one or more disk drives within the array. (Ex. 1009
`
`at 3:10-21.) Each host request typically includes a “data address” within the logical
`
`21
`
`HPE, Exh. 1003, p. 21
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`data address space allocated to the LUN, and the disk array controller translates that
`
`into a location of a particular disk drive within the array. (Ex. 1009 at 3:28-39.)
`
`35. Beginning in the 1990s, the use of Flash memory as the non-volatile
`
`memory medium in a storage device rose to prominence. Flash memory uses
`
`transistors in a semiconductor device to store data and generally is divided into
`
`“blocks,” each block consisting of multiple “pages,” and each page consisting of
`
`multiple “bytes” of data. There are two well-known types of Flash memory: NOR
`
`and NAND. Between the two, NAND Flash is more suitable for data storage systems
`
`since it provides the ability to write a large page at once and has a smaller cell size,
`
`resulting in a higher density and thus lower cost per bit of storage.
`
`36.
`
`Flash was known to have several benefits over hard disks. Unlike hard
`
`disks, Flash memory has no moving parts. Flash memory also has faster read times,
`
`requires less power, and is smaller and lighter weight than hard disk drives. (Ex.
`
`1004 at 3:42-52; see also Ex. 1008 at 1:40-45.) In view of these benefits, companies
`
`like SanDisk, founded by Eliyahou Harari, introduced “solid state” drives in the
`
`1990s that used Flash memory (instead of magnetic hard disk devices) that
`
`“emulate[d]” a conventional hard disk drive, as described in the Harari patent that I
`
`discuss further below. (Ex. 1004 at 7:44-48.)
`
`22
`
`HPE, Exh. 1003, p. 22
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`B.
`Caching
`37. Caches have been used in computing since the late 1960s. A cache has
`
`been described as a “high speed memory or storage device used to reduce the
`
`effective time required to read data from or write data to a lower speed memory or
`
`device.” (Ex. 1007 at 1:31-34.) When a host requests data from or provides data to
`
`a specific address, the controller first checks if data for that address is already in
`
`cache (a “cache hit”) or not (a “cache miss”). If there is a cache hit, the data can then
`
`be retrieved quickly from the cache (for a read request) or overwritten quickly into
`
`the cache (for a write request).
`
`38.
`
`“Caching is a fundamental technique in hiding I/O latency and is widely
`
`used in storage controllers….” (Ex. 1007 at 1:35-36.) Indeed, for decades, cache
`
`memory has been used as a key component of standard hard disk and solid state
`
`drives to address the typically slow write performance of non-volatile memory.
`
`Caches were known to be particularly useful for Flash memory, which can wear out
`
`or lose functionality over time due to constant writes for data from a host device; by
`
`limiting the number of write cycles to the Flash memory, caches efficiently prolong
`
`the useful life of the Flash. (Ex. 1004 at 1:31-39.)
`
`39. A type of cache referred to as a “write back” cache has specifically been
`
`used to address these performance issues. A write back cache stores write data
`
`23
`
`HPE, Exh. 1003, p. 23
`
`

`

`Declaration of Vivek Subramanian, Ph.D.
`IPR2022-00115
`U.S. Patent No. 7,464,240
`entries in the cache, and only writes that data to non-volatile memory later based on
`
`some defined parameters, such as when the cache becomes too full or on a